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Environment_transition.cpp @ 134

Last change on this file since 134 was 134, checked in by rosiere, 15 years ago
1) valgrind fix 2) debug file on/off
Property svn:keywords set to `Id`
File size: 32.7 KB

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1	#include "../include/Environment.h"
2
3	#define CYCLE_MAX 0
4	#include "../../processor/Morpheo/Common/include/Test.h"
5	#include "../../processor/Morpheo/Common/include/Systemc.h"
6
7	using namespace morpheo;
8
9	namespace environment {
10
11	void Environment::transition (void)
12	{
13	_cout(ENVIRONMENT, " [%d] <Environment::transition>\n",static_cast<uint32_t>(simulation_cycle()));
14
15	if (NRESET->read() == 0)
16	{
17	reset ();
18	}
19	else
20	{
21	//=============================================================================
22	//===== [ ICACHE - RESPONS ]===================================================
23	//=============================================================================
24	for (uint32_t i = 0; i < param->nb_entity; i++)
25	for (int32_t j=param->icache_dedicated_nb_port [i]-1; j>=0; j--)
26	{
27	_cout(ENVIRONMENT, " * ICACHE_RSP [%d][%d] (%d - %d)\n",i,j,icache_rsp_val [i][j],ICACHE_RSP_ACK [i][j]->read());
28
29	if (icache_rsp_val [i][j] and ICACHE_RSP_ACK [i][j]->read())
30	{
31	// _cout(ENVIRONMENT, " * ICACHE_RSP [%d][%d] : Transaction accepted\n",i,j);
32
33	uint32_t num = icache_rsp_num [i][j];
34
35	delete component_buffer_irsp [i]->read(num)._data;
36	component_buffer_irsp [i]->pop(num);
37	}
38	}
39	//=============================================================================
40	//===== [ DCACHE - RESPONS ]===================================================
41	//=============================================================================
42	for (uint32_t i = 0; i < param->nb_entity; i++)
43	for (int32_t j=param->dcache_dedicated_nb_port [i]-1; j>=0; j--)
44	{
45	_cout(ENVIRONMENT, " * DCACHE_RSP [%d][%d] (%d - %d)\n",i,j,dcache_rsp_val [i][j],DCACHE_RSP_ACK [i][j]->read());
46
47	if (dcache_rsp_val [i][j] and DCACHE_RSP_ACK [i][j]->read())
48	{
49	// _cout(ENVIRONMENT, " * DCACHE_RSP [%d][%d] : Transaction accepted\n",i,j);
50
51	uint32_t num = dcache_rsp_num [i][j];
52
53	delete component_buffer_drsp [i]->read(num)._data;
54	component_buffer_drsp [i]->pop(num);
55	}
56	}
57
58	//=============================================================================
59	//===== [ ICACHE - RESPONS ]===================================================
60	//=============================================================================
61	for (uint32_t i=0; i<param->nb_entity; i++)
62	for (uint32_t j=0; j <param->icache_dedicated_nb_port [i]; j++)
63	if (ICACHE_REQ_VAL [i][j]->read() and icache_req_ack [i][j])
64	{
65	_cout(ENVIRONMENT, " * ICACHE_REQ [%d][%d] : Transaction accepted\n",i,j);
66
67	Ticache_context_t context = ICACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence
68	Ticache_packet_t packet = ICACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence
69	Ticache_address_t address = ICACHE_REQ_ADDRESS [i][j]->read()<<2;
70	Ticache_type_t type = ICACHE_REQ_TYPE [i][j]->read();
71	uint32_t size = (param->iaccess_size_address [i]+2)/8;
72
73	_cout(ENVIRONMENT," * information\n");
74	_cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));
75	_cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));
76	_cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));
77	_cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));
78	_cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));
79
80	// search the entity
81	data::Entity entity = component_data->entity(static_cast<uint32_t>(address),size);
82
83	bool uncached ;
84	bool bus_error;
85	bool must_read = (type == ICACHE_TYPE_LOAD);
86	bool must_ack = (type == ICACHE_TYPE_LOAD);
87	bool must_ack_on_error = (type == ICACHE_TYPE_LOAD);
88
89	// Test the type of the address : if != MEMORY -> error
90	if ((entity.present == true) and
91	(entity.segment->getType() == data::TYPE_TARGET_MEMORY))
92	{
93	_cout(ENVIRONMENT," * OK !\n");
94	bus_error = false;
95	uncached = entity.segment->getUncached();
96
97	if (must_read == true) // Test if must read the ram
98	{
99	_cout(ENVIRONMENT," * must read\n");
100	// Read all instruction
101	for (unsigned int k=0; k<param->iaccess_nb_instruction[i]; k++)
102	{
103	uint32_t addr = address+k*(size);
104	_cout(ENVIRONMENT," * addr : %.8x - ",addr);
105
106	bus_error \|= !component_data->read(addr,size,read_iram[k]);
107
108	// Swap if endienness is different
109	if (endianness::isSameEndianness(context) == false)
110	{
111	read_iram[k] = endianness::swapBytes(read_iram[k],size,size);
112	}
113
114	//_cout(ENVIRONMENT," * inst : ");
115	for (int32_t cpt=(param->iaccess_size_instruction[i]/8)-1; cpt>=0; --cpt)
116	__cout(ENVIRONMENT, "%.2x",0xff&static_cast<uint32_t>(read_iram[k][cpt]));
117	__cout(ENVIRONMENT, "\n");
118	}
119	}
120	}
121	else
122	{
123	_cout(ENVIRONMENT, " * KO !\n");
124	_cout(ENVIRONMENT, " * present : %d\n",entity.present);
125	if (entity.present)
126	_cout(ENVIRONMENT, " * type : %d must be data::TYPE_TARGET_MEMORY (%d)\n",entity.segment->getType(), data::TYPE_TARGET_MEMORY);
127
128	// entity is not present, or is present but is not a memory : have a bus error
129	bus_error = true;
130	uncached = true;
131	}
132
133	Cache_Access cache_type = ireq_type2cache_type (type,uncached);
134	uint32_t latence = component_cache->latence(cache::INSTRUCTION_CACHE,
135	i,
136	j,
137	address,
138	context,
139	cache_type.type,
140	cache_type.direction);
141
142	_cout(ENVIRONMENT, " * latence : %d\n",latence);
143
144	// If is a respons -> compute the latence and push in the write_buffer
145	if (must_ack or (must_ack_on_error and bus_error))
146	{
147	_cout(ENVIRONMENT, " * must ack\n");
148
149	if (bus_error == true)
150	{
151	_cout(ENVIRONMENT," * Icache : have a bus error\n");
152	_cout(ENVIRONMENT," * entity : %d\n",i);
153	_cout(ENVIRONMENT," * port : %d\n",j);
154	_cout(ENVIRONMENT," * req_addr : %x\n",address);
155	_cout(ENVIRONMENT," * req_trdid : %d\n",context);
156	_cout(ENVIRONMENT," * req_pktid : %d\n",packet );
157
158	// Write in instruction [0] the bad address (only 32bit ....)
159	itoa<Ticache_address_t>(address,read_iram[0],param->iaccess_size_instruction[i]/8);
160	}
161
162	// Simplification : the size of a line is a multiple of size_iword (no test)
163	_cout(ENVIRONMENT, " * push in buffer_irsp[%d]\n",i);
164
165	irsp_t * rsp = new irsp_t(j,
166	context,
167	packet,
168	param->iaccess_nb_instruction[i],
169	size,
170	read_iram,
171	(bus_error==true)?ICACHE_ERROR_BUS_ERROR:ICACHE_ERROR_NONE);
172	component_buffer_irsp [i]->push(latence,rsp);
173	}
174
175	_cout(ENVIRONMENT, " * End request\n");
176	}
177
178	//=============================================================================
179	//===== [ DCACHE - REQUEST ]===================================================
180	//=============================================================================
181	for (uint32_t i=0; i<param->nb_entity; i++)
182	for (uint32_t j=0; j <param->dcache_dedicated_nb_port [i]; j++)
183	if (DCACHE_REQ_VAL [i][j]->read() and dcache_req_ack [i][j])
184	{
185	_cout(ENVIRONMENT, " * DCACHE_REQ [%d][%d] : Transaction accepted\n",i,j);
186
187	Tdcache_context_t context = DCACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence
188	Tdcache_packet_t packet = DCACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence
189	Tdcache_address_t address = DCACHE_REQ_ADDRESS [i][j]->read();
190	Tdcache_data_t wdata = DCACHE_REQ_WDATA [i][j]->read();
191	Tdcache_type_t type = DCACHE_REQ_TYPE [i][j]->read();
192	uint32_t size = param->daccess_size_data [i]/8;
193
194	_cout(ENVIRONMENT," * information\n");
195	_cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));
196	_cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));
197	_cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));
198	_cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));
199	_cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));
200
201	bool uncached = false;
202	bool bus_error = false;
203
204	uint32_t nb_bytes = size;
205	bool must_read ;
206	bool must_write;
207	bool must_ack ;
208	bool must_ack_on_error;
209
210	switch (type)
211	{
212	case DCACHE_TYPE_LOAD_8 :{nb_bytes=1; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
213	case DCACHE_TYPE_LOAD_16 :{nb_bytes=2; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
214	case DCACHE_TYPE_LOAD_32 :{nb_bytes=4; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
215	case DCACHE_TYPE_LOAD_64 :{nb_bytes=8; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
216	case DCACHE_TYPE_LOCK :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
217	case DCACHE_TYPE_INVALIDATE :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
218	case DCACHE_TYPE_PREFETCH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
219	case DCACHE_TYPE_FLUSH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
220	case DCACHE_TYPE_SYNCHRONIZATION :{ must_read=false; must_write=false; must_ack=true ; must_ack_on_error=false; break;}
221	case DCACHE_TYPE_STORE_8 :{nb_bytes=1; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
222	case DCACHE_TYPE_STORE_16 :{nb_bytes=2; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
223	case DCACHE_TYPE_STORE_32 :{nb_bytes=4; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
224	case DCACHE_TYPE_STORE_64 :{nb_bytes=8; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
225	default :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
226	}
227
228	// search the entity
229	data::Entity entity = component_data->entity(static_cast<uint32_t>(address),nb_bytes);
230
231	// std::cout << entity << std::endl;
232
233	// Test the type of the address
234	if (entity.present == true)
235	{
236	switch (entity.segment->getType())
237	{
238	//**************************************************************
239	//***[ TTY ]************************************************
240	//**************************************************************
241	case data::TYPE_TARGET_TTY :
242	{
243	// Can't read a tty, must write
244	if (must_write == false)
245	{
246	bus_error = true;
247	break;
248	}
249
250	uint32_t num_tty = (address - entity.segment->getBase())>>4;
251	uint32_t num_print = ((address>>2) & 0x3);
252	_cout(true," * TYPE_TARGET_TTY : num_tty : %d, num_print : %d\n",num_tty, num_print);
253
254	switch (num_print)
255	{
256	case 0 : // Write TTY
257	{
258	uint32_t num_component_tty = entity.segment->getIndex();
259	char char_write = static_cast<char>(wdata&0xff);
260	bus_error \|= !component_tty [num_component_tty]->write(num_tty,char_write);
261	break;
262	}
263	case 1 : // STOP
264	{
265	_cout(true,"\n");
266	_cout(true,"***********************************************************************************************\n");
267	_cout(true,"*** [ STOP ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x ***\n"
268	,static_cast<uint32_t>(sc_simulation_time())
269	,static_cast<uint32_t>(address )
270	,static_cast<uint32_t>((wdata>>24)&0xff)
271	,static_cast<uint32_t>((wdata>>16)&0xff)
272	,static_cast<uint32_t>((wdata>> 8)&0xff)
273	,static_cast<uint32_t>((wdata>> 0)&0xff)
274	);
275	_cout(true,"***********************************************************************************************\n");
276	_cout(true,"\n");
277	_cout(true,"%s\n",(wdata == 0)?STR_OK:STR_KO);
278	_cout(true,"\n");
279
280	stop (context);
281
282	break;
283	}
284	case 2 : // PRINT
285	{
286	_cout(true,"\n");
287	_cout(true,"-----------------------------------------------------------------------------------------------\n");
288	_cout(true,"----- [ PRINT ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"
289	,static_cast<uint32_t>(sc_simulation_time())
290	,static_cast<uint32_t>(address )
291	,static_cast<uint32_t>((wdata>>24)&0xff)
292	,static_cast<uint32_t>((wdata>>16)&0xff)
293	,static_cast<uint32_t>((wdata>> 8)&0xff)
294	,static_cast<uint32_t>((wdata>> 0)&0xff)
295	);
296	_cout(true,"-----------------------------------------------------------------------------------------------\n");
297	_cout(true,"\n");
298
299	break;
300	}
301	default :
302	{
303	_cout(true,"[address : %.8x] tty %d, reg %d don't exist\n",static_cast<uint32_t>(address),num_tty,num_print);
304	bus_error = true;
305	}
306	}
307	break;
308	}
309
310	//**************************************************************
311	//***[ MEMORY ]*********************************************
312	//**************************************************************
313	case data::TYPE_TARGET_MEMORY :
314	{
315	_cout(ENVIRONMENT," * TYPE_TARGET_MEMORY\n");
316	_cout(ENVIRONMENT," * access : %x\n",address);
317
318	if (must_read == true)
319	{
320	// Read
321	_cout(ENVIRONMENT," * Read (%d bytes)\n",size);
322	bus_error \|= !component_data->read(address,nb_bytes,read_dram[0]); // always read a complete word
323
324	// Multiple copy
325	for (unsigned int it_size_data = nb_bytes; it_size_data < size; it_size_data+=nb_bytes)
326	memcpy(&(read_dram[0][it_size_data]),&(read_dram[0][0]),nb_bytes);
327
328	// Permutation if problem of endianness
329	if (endianness::isSameEndianness(context) == false)
330	read_dram[0] = endianness::swapBytes(read_dram[0] , size, nb_bytes);
331	}
332
333	if (must_write == true)
334	{
335	// Write
336	_cout(ENVIRONMENT," * Write (%d bytes)\n",size);
337	_cout(ENVIRONMENT," * Wdata : %x\n",wdata);
338	itoa<Tdcache_data_t>(wdata,write_dram,nb_bytes);
339
340	// for (unsigned int it_nb_bytes = 0; it_nb_bytes < size; it_nb_bytes ++)
341	// write_dram [it_nb_bytes] = wdata.range(8(it_nb_bytes+1)-1,8it_nb_bytes);
342	}
343
344	break;
345	}
346	//**************************************************************
347	//***[ RAMLOCK ]********************************************
348	//**************************************************************
349	case data::TYPE_TARGET_RAMLOCK :
350	{
351	_cout(ENVIRONMENT," * TYPE_TARGET_RAMLOCK\n");
352
353	// Access is on a byte, else error
354	if (nb_bytes != 1)
355	{
356	bus_error = true;
357	break;
358	}
359
360	uint32_t num_ramlock = (address - entity.segment->getBase()); // Char access
361	uint32_t num_lock = num_ramlock % (param->daccess_size_data [i]/8);
362	uint32_t num_component_ramlock = entity.segment->getIndex();
363
364	_cout(ENVIRONMENT," * num_ramlock : %d\n",num_ramlock );
365	_cout(ENVIRONMENT," * num_lock : %d\n",num_lock );
366	_cout(ENVIRONMENT," * num_component_ramlock : %d\n",num_component_ramlock);
367	// _cout(true," * num_ramlock : %d\n",num_ramlock );
368	// _cout(true," * num_lock : %d\n",num_lock );
369	// _cout(true," * num_component_ramlock : %d\n",num_component_ramlock);
370
371	// No test : because out of range
372
373	// bus_error \|= !component_ramlock [num_component_ramlock]->test(num_ramlock);
374
375	// if (bus_error == true)
376	// break;
377
378	memset (read_dram[0],0,size);
379
380	if (must_read == true)
381	read_dram [0][num_lock] = static_cast<char>(component_ramlock [num_component_ramlock]->read (num_ramlock));
382	if (must_write == true)
383	read_dram [0][num_lock] = static_cast<char>(component_ramlock [num_component_ramlock]->write(num_ramlock));
384
385	// _cout(true," * lock : %d\n",(int)read_dram [0][num_lock]);
386	_cout(ENVIRONMENT," * lock : %d\n",(int)read_dram [0][num_lock]);
387
388	break;
389	}
390
391	//**************************************************************
392	//***[ SIM2OS ]*********************************************
393	//**************************************************************
394	case data::TYPE_TARGET_SIM2OS :
395	{
396	_cout(ENVIRONMENT," * TYPE_TARGET_SIM2OS\n");
397
398	// Mapping :
399	// [0] number of service - Wonly - A write in this register lunch the execution of service
400	// [1] result - Ronly - Content the result of the service
401	// [2] error - Ronly - Content the code of errno
402	// [3+] argument - Wonly - it's all argument to execute the service
403
404	uint32_t num_reg = (address - entity.segment->getBase())>>2;
405
406	_cout(ENVIRONMENT," * num_reg : %d\n",num_reg);
407
408	switch (num_reg)
409	{
410	case 0 : // ---> number of service
411	{
412	if (must_write == false)
413	{
414	_cerr("<Environment::transition> SIM2OS[0] is not accessible in Read\n");
415	bus_error = true;
416	}
417	else
418	{
419	_cout(ENVIRONMENT," * service : %x\n",wdata);
420	component_sim2os->execute(sim2os::int2service(static_cast<uint32_t>(wdata)));
421	}
422	break;
423	}
424	case 1 : // ---> result
425	{
426	if (must_read == false)
427	{
428	_cerr("<Environment::transition> SIM2OS[1] is not accessible in Write\n");
429	bus_error = true;
430	}
431	else
432	{
433	// Decomposition en groupe octect
434	Tdcache_data_t result = static_cast<Tdcache_data_t>(reinterpret_cast<uint64_t>(component_sim2os->result));
435	_cout(ENVIRONMENT," * result : %x\n",result);
436
437	itoa<Tdcache_data_t>(result,read_dram[0],size);
438	}
439	break;
440	}
441	case 2 : // ---> error
442	{
443	if (must_read == false)
444	{
445	_cerr("<Environment::transition> SIM2OS[2] is not accessible in Write\n");
446	bus_error = true;
447	}
448	else
449	{
450	// Decomposition en groupe octect
451	Tdcache_data_t error = (Tdcache_data_t)component_sim2os->error;
452	_cout(ENVIRONMENT," * error : %x\n",error);
453
454	itoa<Tdcache_data_t>(error,read_dram[0],size);
455	}
456
457	break;
458	}
459	default : //---> argument
460	{
461	if (must_write == false)
462	{
463	_cerr("<Environment::transition> SIM2OS[%d] is not accessible in Read\n",num_reg);
464	bus_error = true;
465	}
466	else
467	{
468	_cout(ENVIRONMENT," * argument[%d] : %x\n",num_reg-1,wdata);
469	component_sim2os->parameter(num_reg-2,(void *)wdata);
470	}
471	break;
472	}
473	}
474
475	break;
476	}
477
478	default :
479	{
480	_cerr("<Environment::transition> Dcache_req : Unknow type\n");
481	exit(1);
482	break;
483	}
484	}
485	uncached \|= entity.segment->getUncached();
486	}
487	else
488	{
489	// entity is not present, or is present but is not a memory : have a bus error
490	bus_error = true;
491	uncached = true;
492	}
493
494	if ((must_write == true) and (bus_error == false))
495	{
496	// Permutation if problem of endianness
497	if (endianness::isSameEndianness(context) == false)
498	write_dram = endianness::swapBytes(write_dram, size, nb_bytes);
499
500	bus_error \|= !component_data->write(address, nb_bytes, write_dram); // take the good access
501	}
502
503	// Acces at the cache !!!
504	// Cache WRITE ALLOCATE (becauce compute latence always; )
505	Cache_Access cache_type = dreq_type2cache_type (type,uncached);
506	uint32_t latence = component_cache->latence(cache::DATA_CACHE,
507	i,
508	j,
509	address,
510	context,
511	cache_type.type,
512	cache_type.direction);
513
514	// If is a respons -> compute the latence and push in the write_buffer
515	if (must_ack or (must_ack_on_error and bus_error))
516	{
517	if (bus_error == true)
518	{
519	_cout(ENVIRONMENT," * Dcache : have a bus error\n");
520	_cout(ENVIRONMENT," * entity : %d\n",i);
521	_cout(ENVIRONMENT," * port : %d\n",j);
522	_cout(ENVIRONMENT," * req_addr : 0x%x\n",address);
523	_cout(ENVIRONMENT," * req_trdid : %d\n",context);
524	_cout(ENVIRONMENT," * req_pktid : %d\n",packet );
525
526	// Write in data [0] the bad address (32bit or 64bits )
527	itoa<Tdcache_data_t>(address,read_dram[0],param->daccess_size_data[i]/8);
528	}
529
530	_cout(ENVIRONMENT," * Rdata : ");
531	for (uint32_t x=0; x<nb_bytes; x++)
532	__cout(ENVIRONMENT,"%.2x",0xff&static_cast<uint32_t>(read_dram[0][x]));
533	_cout(ENVIRONMENT,".\n");
534
535	// Simplification : the size of a line is a multiple of size_iword (no test)
536	drsp_t * rsp = new drsp_t(j,
537	context,
538	packet,
539	1,
540	size,
541	read_dram,
542	(bus_error==true)?DCACHE_ERROR_BUS_ERROR:DCACHE_ERROR_NONE);
543	component_buffer_drsp [i]->push(latence,rsp);
544	}
545	}
546
547	//=============================================================================
548	//===== [ OTHERS ]=============================================================
549	//=============================================================================
550
551	// Transition for each component
552	component_cache -> transition();
553	for (uint32_t i=0; i<param->nb_entity; i++)
554	{
555	component_buffer_irsp [i]->transition();
556	component_buffer_drsp [i]->transition();
557	}
558	component_sim2os->transition();
559	}
560	}
561
562	// // ******************
563	// // *** DCACHE ***
564	// // ******************
565
566	// for (uint32_t j = 0; j < nb_dport [i]; j ++)
567	// {
568	// // Test if transaction
569
570	// if ( (DCACHE [i][j].REQ_VAL.read() && dreq_ack [i][j]) == false)
571	// continue;
572
573	// entity_t entity = component_data->entity((uint32_t)DCACHE [i][j].REQ_ADDR.read(), SIZE_DDATA/8);
574
575	// bool uncached = DCACHE [i][j].REQ_UNC.read();
576	// bool bus_error = false;
577
578	// uint32_t addr = (uint32_t) DCACHE [i][j].REQ_ADDR.read();
579	// sc_uint<SIZE_DDATA> wdata = DCACHE[i][j].REQ_WDATA .read();
580	// sc_uint<3> type = DCACHE[i][j].REQ_TYPE .read();
581	// uint32_t nb_bytes = access_nb_bytes(DCACHE[i][j].REQ_ACCESS.read());
582	// // A lot of flag
583	// bool must_read = ((type == DTYPE_READ ));
584	// bool must_write = ((type == DTYPE_WRITE ) \|\|
585	// (type == DTYPE_WRITE_ACK ) );
586	// bool must_ack = ((type == DTYPE_READ ) \|\|
587	// (type == DTYPE_WRITE_ACK ) );
588
589	// // Test the type of the address
590	// if (entity.present == true)
591	// {
592	// switch (entity.segment->getType())
593	// {
594	// // ACCESS AT A RAM
595	// case data::TYPE_TARGET_MEMORY :
596	// {
597	// if (must_read == true)
598	// {
599	// // Read
600	// bus_error \|= !component_data->read(addr ,
601	// SIZE_DDATA/8 , // always read a complete word
602	// read_dram );
603
604	// for (unsigned int it_size_data = nb_bytes; it_size_data < SIZE_DDATA/8; it_size_data+=nb_bytes)
605	// memcpy(&(read_dram[it_size_data]),&(read_dram[0]),nb_bytes);
606
607	// // Permutation if problem of endianness
608	// if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false)
609	// read_dram = swapBytes(read_dram , SIZE_DDATA/8, nb_bytes);
610	// }
611
612	// if (must_write == true)
613	// {
614	// // Write
615	// for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_DDATA / 8; it_nb_bytes ++)
616	// write_dram [it_nb_bytes] = wdata.range(8(it_nb_bytes+1)-1,8it_nb_bytes);
617	// }
618	// break;
619	// }
620	// //ACCESS AT THE TTY
621	// case TYPE_TTY :
622	// {
623	// if (must_write == false)
624	// {
625	// bus_error = true;
626	// break;
627	// }
628	// uint32_t num_tty = (addr - entity.segment->getBase())>>4;
629	// uint32_t num_print = ((addr>>2) & 0x3);
630
631	// switch (num_print)
632	// {
633	// case 0 : // Write TTY
634	// {
635	// uint32_t num_component_tty = entity.segment->getIndex();
636	// char char_write = (char)wdata.range( 7, 0);
637	// bus_error \|= !component_tty [num_component_tty]->write(num_tty,char_write);
638	// break;
639	// }
640	// case 1 : // STOP
641	// {
642	// cout("\n\t*** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x ***\n"
643	// ,(unsigned int)sc_simulation_time()
644	// ,(unsigned int)addr
645	// ,(unsigned int)wdata.range(31,24)
646	// ,(unsigned int)wdata.range(23,16)
647	// ,(unsigned int)wdata.range(15, 8)
648	// ,(unsigned int)wdata.range( 7, 0)
649	// );
650
651	// uint32_t trdid = (uint32_t) DCACHE[i][j].REQ_TRDID.read();
652
653	// if (context_stop [trdid] == false)
654	// {
655	// context_stop [trdid] = true;
656	// nb_context_stop ++;
657
658	// if (nb_context_stop >= nb_context)
659	// sc_stop();
660	// }
661
662	// break;
663	// }
664	// case 2 : // PRINT
665	// {
666	// cout("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"
667	// ,(unsigned int)sc_simulation_time()
668	// ,(unsigned int)addr
669	// ,(unsigned int)wdata.range(31,24)
670	// ,(unsigned int)wdata.range(23,16)
671	// ,(unsigned int)wdata.range(15, 8)
672	// ,(unsigned int)wdata.range( 7, 0)
673	// );
674
675	// break;
676	// }
677	// default :
678	// {
679	// cout("<%s> : [address : %.8x] tty %d, reg %d don't exist\n",NAME,(unsigned int)addr,num_tty,num_print);
680	// exit(1);
681	// }
682	// }
683
684	// break;
685	// }
686	// case TYPE_RAMLOCK :
687	// {
688	// // Access is on a byte, else error
689	// if (nb_bytes != 1)
690	// {
691	// bus_error = true;
692	// break;
693	// }
694	// uint32_t num_ramlock = (addr - entity.segment->getBase()); // Char access
695	// uint32_t num_component_ramlock = entity.segment->getIndex();
696	// bus_error \|= !component_ramlock [num_component_ramlock]->test(num_ramlock);
697
698	// if (bus_error == true)
699	// break;
700
701	// memset (read_dram,0,SIZE_DDATA/8);
702
703	// if (must_read == true)
704	// read_dram [0] = (char)component_ramlock [num_component_ramlock]->read (num_ramlock);
705	// if (must_write == true)
706	// read_dram [0] = (char)component_ramlock [num_component_ramlock]->write(num_ramlock);
707
708	// /*
709	// cout("Access ramlock ( %d )\n" ,(uint32_t)sc_simulation_time());
710	// cout(" * addr : %.8x\n" ,(uint32_t)addr);
711	// cout(" * trdid : %d\n" ,(uint32_t)DCACHE[i][j].REQ_TRDID.read());
712	// cout(" * r/w : %d/%d\n",must_read,must_write);
713	// cout(" * val : %d\n" ,(uint32_t)read_dram[0]);
714	// */
715	// break;
716	// }
717	// case TYPE_SIM2OS :
718	// {
719	// // Mapping :
720	// // [0] number of service - Wonly - A write in this register lunch the execution of service
721	// // [1] result - Ronly - Content the result of the service
722	// // [2] error - Ronly - Content the code of errno
723	// // [3+] argument - Wonly - it's all argument to execute the service
724
725	// uint32_t num_reg = (addr - entity.segment->getBase())>>2;
726
727	// switch (num_reg)
728	// {
729	// case 0 : // ---> number of service
730	// {
731	// if (must_write == false)
732	// {
733	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[0] is not accessible in Read" << endl;
734	// bus_error = true;
735	// }
736	// else
737	// {
738	// cout("<sim2os> service : %.8x\n",(uint32_t)wdata);
739	// component_sim2os->execute(int2service((uint32_t)wdata));
740	// }
741	// break;
742	// }
743	// case 1 : // ---> result
744	// {
745	// if (must_read == false)
746	// {
747	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[1] is not accessible in Write" << endl;
748	// bus_error = true;
749	// }
750	// else
751	// {
752	// // Decomposition en groupe octect
753	// uint32_t result = (uint32_t) component_sim2os->result;
754	// cout("<sim2os> result : %.8x (%d)\n",result,result);
755
756	// read_dram = itoa(result,read_dram,SIZE_DDATA/8);
757	// }
758	// break;
759	// }
760	// case 2 : // ---> error
761	// {
762	// if (must_read == false)
763	// {
764	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[2] is not accessible in Write" << endl;
765	// bus_error = true;
766	// }
767	// else
768	// {
769	// // Decomposition en groupe octect
770	// uint32_t error = (uint32_t) component_sim2os->error;
771	// cout("<sim2os> error : %.8x\n",error);
772	// read_dram = itoa(error ,read_dram,SIZE_DDATA/8);
773	// }
774	// break;
775	// }
776	// default : // ---> argument
777	// {
778	// if (must_write == false)
779	// {
780	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[" << num_reg << "] is not accessible in Write" << endl;
781	// bus_error = true;
782	// }
783	// else
784	// {
785	// uint32_t data = (uint32_t)wdata;
786	// cout("<sim2os> argument[%d] : %.8x\n",num_reg-1,data);
787	// component_sim2os->parameter(num_reg-2,(void *)data);
788	// }
789	// break;
790	// }
791	// }//end switch num_reg
792
793	// break;
794	// }
795	// default :
796	// {
797	// // Have a bus error
798	// bus_error = true;
799	// break;
800	// }
801	// }// switch
802	// uncached \|= entity.segment->getUncached();
803	// }
804	// else
805	// uncached = true; // If segment don't exist : it's the system bus that determine if the segment exist
806
807
808	// if ((must_write == true) && (bus_error == false))
809	// {
810	// // Permutation if problem of endianness
811	// if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false)
812	// write_dram = swapBytes(write_dram, SIZE_DDATA/8, nb_bytes);
813
814	// bus_error \|= !component_data->write(addr ,
815	// nb_bytes, // take the good access
816	// write_dram );
817	// }
818
819
820	// // Acces at the cache !!!
821	// Cache_Access cache_type = dreq_type2cache_type (type, uncached);
822
823	// uint32_t latence = component_cache->latence(DATA_CACHE ,
824	// i ,
825	// j ,
826	// (uint32_t)DCACHE [i][j].REQ_ADDR .read() ,
827	// (uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
828	// cache_type.type ,
829	// cache_type.direction );
830
831	// // If is a respons -> compute the latence and push in the write_buffer
832	// if ( must_ack == true)
833	// {
834	// if (bus_error == true)
835	// cout("Dcache : have a bus error");
836	// component_buffer_drsp [i]->push(latence,
837	// Entry((uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
838	// (uint32_t)DCACHE [i][j].REQ_PKTID.read() ,
839	// 1 ,
840	// SIZE_DDATA/8 ,
841	// &read_dram ,
842	// (bus_error==true)?ERR_BUS:ERR_NO )
843	// );
844	// }
845	// }// dnb_port
846	// }//i
847
848
849	};

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source: trunk/IPs/systemC/Environment/src/Environment_transition.cpp @ 134

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