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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp @ 59

Last change on this file since 59 was 59, checked in by rosiere, 17 years ago
Add Load store queue -> but not terminated and tested Add article to sympa 2007 -> but no started
File size: 29.7 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include <queue>
10	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
11	#include "Common/include/Test.h"
12
13	#define NB_ITERATION 1
14	#define CYCLE_MAX (128*NB_ITERATION)
15
16	#define LABEL(str) \
17	{ \
18	cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \
19	} while(0)
20
21	static uint32_t cycle = 0;
22
23	#define SC_START(cycle_offset) \
24	do \
25	{ \
26	/cout << "SC_START (begin)" << endl;/ \
27	\
28	uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
29	if (cycle_current != cycle) \
30	{ \
31	cycle = cycle_current; \
32	cout << "##########[ cycle "<< cycle << " ]" << endl; \
33	} \
34	\
35	if (cycle_current > CYCLE_MAX) \
36	{ \
37	TEST_KO("Maximal cycles Reached"); \
38	} \
39	sc_start(cycle_offset); \
40	/cout << "SC_START (end )" << endl;/ \
41	} while(0)
42
43
44
45	class MemoryRequest_t
46	{
47	public : double _cycle ;
48	public : Tcontext_t _context_id ;
49	public : Tpacket_t _packet_id ;
50	public : Toperation_t _operation ;
51	public : Ttype_t _type ;
52	public : Tlsq_ptr_t _store_queue_ptr_write;
53	public : Tlsq_ptr_t _load_queue_ptr_write ;
54	public : Tgeneral_data_t _immediat ;
55	public : Tgeneral_data_t _data_ra ;
56	public : Tgeneral_data_t _data_rb ;
57	public : Tcontrol_t _write_rd ;
58	public : Tgeneral_address_t _num_reg_rd ;
59	public : bool _write_spec_ko ;
60
61	MemoryRequest_t (void)
62	{
63	_cycle = 0;
64	_context_id = 0;
65	_packet_id = 0;
66	_operation = 0;
67	_type = 0;
68	_store_queue_ptr_write = 0;
69	_load_queue_ptr_write = 0;
70	_immediat = 0;
71	_data_ra = 0;
72	_data_rb = 0;
73	_write_rd = 0;
74	_num_reg_rd = 0;
75	_write_spec_ko = 0;
76	};
77
78	MemoryRequest_t (double cycle ,
79	Tcontext_t context_id ,
80	Tpacket_t packet_id ,
81	Toperation_t operation ,
82	Ttype_t type ,
83	Tlsq_ptr_t store_queue_ptr_write,
84	Tlsq_ptr_t load_queue_ptr_write ,
85	Tgeneral_data_t immediat ,
86	Tgeneral_data_t data_ra ,
87	Tgeneral_data_t data_rb ,
88	Tcontrol_t write_rd ,
89	Tgeneral_address_t num_reg_rd ,
90	bool write_spec_ko )
91	{
92	_cycle = cycle ;
93	_context_id = context_id ;
94	_packet_id = packet_id ;
95	_operation = operation ;
96	_type = type ;
97	_store_queue_ptr_write = store_queue_ptr_write;
98	_load_queue_ptr_write = load_queue_ptr_write ;
99	_immediat = immediat ;
100	_data_ra = data_ra ;
101	_data_rb = data_rb ;
102	_write_rd = write_rd ;
103	_num_reg_rd = num_reg_rd ;
104	_write_spec_ko = write_spec_ko ;
105	}
106
107	void modif (double cycle ,
108	Tcontext_t context_id ,
109	Tpacket_t packet_id ,
110	Toperation_t operation ,
111	Ttype_t type ,
112	Tlsq_ptr_t store_queue_ptr_write,
113	Tlsq_ptr_t load_queue_ptr_write ,
114	Tgeneral_data_t immediat ,
115	Tgeneral_data_t data_ra ,
116	Tgeneral_data_t data_rb ,
117	Tcontrol_t write_rd ,
118	Tgeneral_address_t num_reg_rd ,
119	bool write_spec_ko )
120	{
121	_cycle = cycle ;
122	_context_id = context_id ;
123	_packet_id = packet_id ;
124	_operation = operation ;
125	_type = type ;
126	_store_queue_ptr_write = store_queue_ptr_write;
127	_load_queue_ptr_write = load_queue_ptr_write ;
128	_immediat = immediat ;
129	_data_ra = data_ra ;
130	_data_rb = data_rb ;
131	_write_rd = write_rd ;
132	_num_reg_rd = num_reg_rd ;
133	_write_spec_ko = write_spec_ko ;
134	}
135
136	bool operator< (const MemoryRequest_t & right) const
137	{
138	return _cycle > right._cycle;
139	}
140
141	friend ostream& operator<<(ostream &, const MemoryRequest_t &);
142	};
143
144	ostream & operator << (ostream& os, const MemoryRequest_t & x)
145	{
146	return os << "<" << toString(x._cycle) << "> : "
147	<< "{" << toString(static_cast<uint32_t>(x._packet_id)) << "}" << endl
148	<< "\t * " << toString(static_cast<uint32_t>(x._context_id)) << endl
149	<< "\t * " << toString(static_cast<uint32_t>(x._operation)) << " " << toString(static_cast<uint32_t>(x._type)) << " " << toString(static_cast<uint32_t>(x._write_spec_ko)) << endl
150	<< "\t * " << toString(static_cast<uint32_t>(x._store_queue_ptr_write)) << " " << toString(static_cast<uint32_t>(x._load_queue_ptr_write)) << endl
151	<< "\t * " << toString(static_cast<uint32_t>(x._immediat)) << " - " << toString(static_cast<uint32_t>(x._data_ra)) << " - " << toString(static_cast<uint32_t>(x._data_rb)) << endl
152	<< "\t * " << toString(static_cast<uint32_t>(x._write_rd)) << " " << toString(static_cast<uint32_t>(x._num_reg_rd)) << endl;
153	}
154
155	void test (string name,
156	morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param)
157	{
158	cout << "<" << name << "> : Simulation SystemC" << endl;
159
160	#ifdef STATISTICS
161	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
162	#endif
163
164	Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(),
165	#ifdef STATISTICS
166	_parameters_statistics,
167	#endif
168	_param);
169
170	#ifdef SYSTEMC
171	/*********************************************************************
172	* Déclarations des signaux
173	*********************************************************************/
174	string rename = "";
175
176	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
177	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
178
179	sc_signal<Tcontrol_t > * in_MEMORY_IN_VAL = new sc_signal<Tcontrol_t > (rename.c_str());
180	sc_signal<Tcontrol_t > * out_MEMORY_IN_ACK = new sc_signal<Tcontrol_t > (rename.c_str());
181	sc_signal<Tcontext_t > * in_MEMORY_IN_CONTEXT_ID = new sc_signal<Tcontext_t > (rename.c_str());
182	sc_signal<Tpacket_t > * in_MEMORY_IN_PACKET_ID = new sc_signal<Tpacket_t > (rename.c_str());
183	sc_signal<Toperation_t > * in_MEMORY_IN_OPERATION = new sc_signal<Toperation_t > (rename.c_str());
184	sc_signal<Ttype_t > * in_MEMORY_IN_TYPE = new sc_signal<Ttype_t > (rename.c_str());
185	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
186	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
187	//sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str());
188	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_IMMEDIAT = new sc_signal<Tgeneral_data_t > (rename.c_str());
189	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RA = new sc_signal<Tgeneral_data_t > (rename.c_str());
190	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RB = new sc_signal<Tgeneral_data_t > (rename.c_str());
191	//sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str());
192	sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str());
193	sc_signal<Tgeneral_address_t> * in_MEMORY_IN_NUM_REG_RD = new sc_signal<Tgeneral_address_t> (rename.c_str());
194	//sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str());
195	//sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str());
196
197	sc_signal<Tcontrol_t > * out_MEMORY_OUT_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
198	sc_signal<Tcontrol_t > * in_MEMORY_OUT_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
199	sc_signal<Tcontext_t > * out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
200	sc_signal<Tpacket_t > * out_MEMORY_OUT_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
201	sc_signal<Toperation_t > * out_MEMORY_OUT_OPERATION = new sc_signal<Toperation_t >(rename.c_str());
202	sc_signal<Ttype_t > * out_MEMORY_OUT_TYPE = new sc_signal<Ttype_t >(rename.c_str());
203	sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RD = new sc_signal<Tcontrol_t >(rename.c_str());
204	sc_signal<Tgeneral_address_t> * out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str());
205	sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_DATA_RD = new sc_signal<Tgeneral_data_t >(rename.c_str());
206	//sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str());
207	//sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str());
208	//sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str());
209	sc_signal<Texception_t > * out_MEMORY_OUT_EXCEPTION = new sc_signal<Texception_t >(rename.c_str());
210
211	sc_signal<Tcontrol_t > * out_DCACHE_REQ_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
212	sc_signal<Tcontrol_t > * in_DCACHE_REQ_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
213	sc_signal<Tcontext_t > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
214	sc_signal<Tpacket_t > * out_DCACHE_REQ_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
215	sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS = new sc_signal<Tdcache_address_t >(rename.c_str());
216	sc_signal<Tdcache_type_t > * out_DCACHE_REQ_TYPE = new sc_signal<Tdcache_type_t >(rename.c_str());
217	sc_signal<Tcontrol_t > * out_DCACHE_REQ_UNCACHED = new sc_signal<Tcontrol_t >(rename.c_str());
218	sc_signal<Tdcache_data_t > * out_DCACHE_REQ_WDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
219
220	sc_signal<Tcontrol_t > * in_DCACHE_RSP_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
221	sc_signal<Tcontrol_t > * out_DCACHE_RSP_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
222	sc_signal<Tcontext_t > * in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
223	sc_signal<Tpacket_t > * in_DCACHE_RSP_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
224	sc_signal<Tdcache_data_t > * in_DCACHE_RSP_RDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
225	sc_signal<Tdcache_error_t > * in_DCACHE_RSP_ERROR = new sc_signal<Tdcache_error_t >(rename.c_str());
226
227	sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_size_load_queue];
228	sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_CONTEXT_ID = new sc_signal<Tcontext_t > * [_param->_size_load_queue];
229	sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_size_load_queue];
230	sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_size_load_queue];
231
232	for (uint32_t i=0; i<_param->_size_load_queue; i++)
233	{
234	out_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t >;
235	out_BYPASS_MEMORY_CONTEXT_ID [i] = new sc_signal<Tcontext_t >;
236	out_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t>;
237	out_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t >;
238	}
239
240	/********************************************************
241	* Instanciation
242	********************************************************/
243
244	cout << "<" << name << "> Instanciation of _Load_store_unit" << endl;
245
246	((_Load_store_unit->in_CLOCK)) ((in_CLOCK));
247	((_Load_store_unit->in_NRESET)) ((in_NRESET));
248
249	((_Load_store_unit-> in_MEMORY_IN_VAL ))(( in_MEMORY_IN_VAL ));
250	((_Load_store_unit->out_MEMORY_IN_ACK ))((out_MEMORY_IN_ACK ));
251	((_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID ))(( in_MEMORY_IN_CONTEXT_ID ));
252	((_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(( in_MEMORY_IN_PACKET_ID ));
253	((_Load_store_unit-> in_MEMORY_IN_OPERATION ))(( in_MEMORY_IN_OPERATION ));
254	((_Load_store_unit-> in_MEMORY_IN_TYPE ))(( in_MEMORY_IN_TYPE ));
255	((_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
256	((_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
257	//((_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(( in_MEMORY_IN_HAS_IMMEDIAT ));
258	((_Load_store_unit-> in_MEMORY_IN_IMMEDIAT ))(( in_MEMORY_IN_IMMEDIAT ));
259	((_Load_store_unit-> in_MEMORY_IN_DATA_RA ))(( in_MEMORY_IN_DATA_RA ));
260	((_Load_store_unit-> in_MEMORY_IN_DATA_RB ))(( in_MEMORY_IN_DATA_RB ));
261	//((_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(( in_MEMORY_IN_DATA_RC ));
262	((_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(( in_MEMORY_IN_WRITE_RD ));
263	((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD ))(( in_MEMORY_IN_NUM_REG_RD ));
264	//((_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(( in_MEMORY_IN_WRITE_RE ));
265	//((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(( in_MEMORY_IN_NUM_REG_RE ));
266
267	((_Load_store_unit->out_MEMORY_OUT_VAL ))((out_MEMORY_OUT_VAL ));
268	((_Load_store_unit-> in_MEMORY_OUT_ACK ))(( in_MEMORY_OUT_ACK ));
269	((_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))((out_MEMORY_OUT_CONTEXT_ID ));
270	((_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))((out_MEMORY_OUT_PACKET_ID ));
271	((_Load_store_unit->out_MEMORY_OUT_OPERATION ))((out_MEMORY_OUT_OPERATION ));
272	((_Load_store_unit->out_MEMORY_OUT_TYPE ))((out_MEMORY_OUT_TYPE ));
273	((_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))((out_MEMORY_OUT_WRITE_RD ));
274	((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))((out_MEMORY_OUT_NUM_REG_RD ));
275	((_Load_store_unit->out_MEMORY_OUT_DATA_RD ))((out_MEMORY_OUT_DATA_RD ));
276	//((_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))((out_MEMORY_OUT_WRITE_RE ));
277	//((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))((out_MEMORY_OUT_NUM_REG_RE ));
278	//((_Load_store_unit->out_MEMORY_OUT_DATA_RE ))((out_MEMORY_OUT_DATA_RE ));
279	((_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))((out_MEMORY_OUT_EXCEPTION ));
280
281	((_Load_store_unit->out_DCACHE_REQ_VAL ))((out_DCACHE_REQ_VAL ));
282	((_Load_store_unit-> in_DCACHE_REQ_ACK ))(( in_DCACHE_REQ_ACK ));
283	((_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))((out_DCACHE_REQ_CONTEXT_ID));
284	((_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))((out_DCACHE_REQ_PACKET_ID ));
285	((_Load_store_unit->out_DCACHE_REQ_ADDRESS ))((out_DCACHE_REQ_ADDRESS ));
286	((_Load_store_unit->out_DCACHE_REQ_TYPE ))((out_DCACHE_REQ_TYPE ));
287	((_Load_store_unit->out_DCACHE_REQ_UNCACHED ))((out_DCACHE_REQ_UNCACHED ));
288	((_Load_store_unit->out_DCACHE_REQ_WDATA ))((out_DCACHE_REQ_WDATA ));
289
290	((_Load_store_unit-> in_DCACHE_RSP_VAL ))(( in_DCACHE_RSP_VAL ));
291	((_Load_store_unit->out_DCACHE_RSP_ACK ))((out_DCACHE_RSP_ACK ));
292	((_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(( in_DCACHE_RSP_CONTEXT_ID));
293	((_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(( in_DCACHE_RSP_PACKET_ID ));
294	((_Load_store_unit-> in_DCACHE_RSP_RDATA ))(( in_DCACHE_RSP_RDATA ));
295	((_Load_store_unit-> in_DCACHE_RSP_ERROR ))(( in_DCACHE_RSP_ERROR ));
296
297	if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
298	{
299	for (uint32_t i=0; i<_param->_size_load_queue; i++)
300	{
301	((_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))((out_BYPASS_MEMORY_VAL [i]));
302	((_Load_store_unit->out_BYPASS_MEMORY_CONTEXT_ID [i]))((out_BYPASS_MEMORY_CONTEXT_ID [i]));
303	((_Load_store_unit->out_BYPASS_MEMORY_NUM_REG [i]))((out_BYPASS_MEMORY_NUM_REG [i]));
304	((_Load_store_unit->out_BYPASS_MEMORY_DATA [i]))((out_BYPASS_MEMORY_DATA [i]));
305	}
306	}
307	cout << "<" << name << "> Start Simulation ............" << endl;
308	Time * _time = new Time();
309
310	/********************************************************
311	* Simulation - Begin
312	********************************************************/
313
314	// Initialisation
315
316	const uint32_t seed = 0;
317	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
318
319	srand(seed);
320
321	const uint32_t nb_request = _param->_nb_packet;
322	const uint32_t nb_word = nb_request;
323
324	const uint32_t cst_max_cycle = 2;
325
326	const int32_t percent_transaction_memory_in = 100;
327	const int32_t percent_transaction_memory_out = 100;
328	const int32_t percent_transaction_dcache = 100;
329
330	const int32_t percent_exception = 5;
331	const int32_t percent_type_load = 0;
332	const int32_t percent_type_store = 100;
333	const int32_t percent_miss_spec = 100;
334
335	if ((percent_type_load +
336	percent_type_store ) > 100)
337	TEST_KO("sum of percent_type > 100");
338
339	const int32_t seuil_type_load = seuil_type_load;
340	const int32_t seuil_type_store = seuil_type_store+percent_type_load;
341
342	uint32_t nb_request_memory_in ;
343	uint32_t nb_request_memory_out;
344	uint32_t nb_request_dcache ;
345
346	MemoryRequest_t tab_request [nb_request];
347	priority_queue<MemoryRequest_t> fifo_request;
348
349	Tdcache_data_t cache_data [_param->_nb_context][nb_word];
350
351	SC_START(0);
352
353	LABEL("Initialisation");
354
355	// emulate a memory
356	for (uint32_t i=0; i<_param->_nb_context; i++)
357	for (uint32_t j=0; j<nb_word; j++)
358	cache_data [i][j] = rand()%(1<<_param->_size_general_data);
359
360	in_MEMORY_IN_VAL ->write(0);
361	in_MEMORY_OUT_ACK->write(0);
362	in_DCACHE_REQ_ACK->write(0);
363	in_DCACHE_RSP_VAL->write(0);
364
365	in_NRESET ->write(0);
366	SC_START(5);
367	in_NRESET ->write(5);
368
369	LABEL("Loop of Test");
370
371	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
372	{
373	nb_request_memory_in = 0;
374	nb_request_memory_out = 0;
375	nb_request_dcache = 0;
376
377	LABEL("Iteration "+toString(iteration));
378
379	// Fill the request_queue
380
381	Tlsq_ptr_t store_queue_ptr_write = 0;
382	Tlsq_ptr_t load_queue_ptr_write = 0;
383
384	bool store_queue_use [_param->_size_store_queue];
385	bool load_queue_use [_param->_size_load_queue ];
386
387	for (uint32_t i=0; i<_param->_size_store_queue; i++)
388	store_queue_use [i] = false;
389	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
390	load_queue_use [i] = false;
391
392	double store_queue_cycle [_param->_size_store_queue];
393	double load_queue_cycle [_param->_size_load_queue ];
394	double current_cycle = sc_simulation_time();
395
396	for (uint32_t i=0; i<_param->_size_store_queue; i++)
397	store_queue_cycle [i] = current_cycle;
398	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
399	load_queue_cycle [i] = current_cycle;
400
401	// Init fifo_request
402	for (uint32_t i=0; i<nb_request; i++)
403	{
404	double cycle = current_cycle+(rand()%(cst_max_cycle*nb_request));
405	Tcontext_t context_id = rand () % _param->_nb_context;
406	Tpacket_t packet_id = i;
407	Tlsq_ptr_t store_queue_ptr_write_old = store_queue_ptr_write;
408	Tlsq_ptr_t load_queue_ptr_write_old = load_queue_ptr_write ;
409	Toperation_t operation;
410
411	int32_t percent = rand()%100;
412
413	if (percent < seuil_type_load)
414	{
415	operation = OPERATION_MEMORY_LOAD_16_S;
416	load_queue_ptr_write = (load_queue_ptr_write+1) % (_param->_size_load_queue);
417	}
418	else
419	if (percent < seuil_type_store)
420	{
421	operation = OPERATION_MEMORY_STORE_16;
422	store_queue_ptr_write = (store_queue_ptr_write+1) % (_param->_size_store_queue);
423	}
424	else
425	{
426	operation = OPERATION_MEMORY_PREFETCH;
427	load_queue_ptr_write = (load_queue_ptr_write+1) % (_param->_size_load_queue);
428	}
429
430	// Valid nb cycle ?
431	if (is_operation_memory_store(operation))
432	{
433	if (cycle <= store_queue_cycle[packet_id])
434	cycle = store_queue_cycle[packet_id]+1;
435	}
436	else
437	{
438	if (cycle <= load_queue_cycle[packet_id])
439	cycle = load_queue_cycle[packet_id]+1;
440	}
441
442	Ttype_t type = TYPE_MEMORY;
443
444	Tgeneral_data_t address = rand()%(1<<_param->_size_general_data);
445	Tgeneral_data_t offset = rand()%(1<<_param->_size_general_data);
446
447	percent = rand()%100;
448	if (percent > percent_exception)
449	address = address & (not mask_memory_access(operation));
450
451	if (offset > address) // max
452	offset = address;
453
454	Tgeneral_data_t immediat = offset;
455	Tgeneral_data_t data_ra = address - offset;
456	Tgeneral_data_t data_rb = rand()%(1<<_param->_size_general_data);
457	Tcontrol_t write_rd = 0;
458	Tgeneral_address_t num_reg_rd = 0;
459	bool write_spec_ko = ((rand()%100)<percent_miss_spec);
460
461	tab_request [i].modif(cycle ,
462	context_id ,
463	packet_id ,
464	operation ,
465	type ,
466	store_queue_ptr_write_old,
467	load_queue_ptr_write_old ,
468	immediat ,
469	data_ra ,
470	data_rb ,
471	write_rd ,
472	num_reg_rd ,
473	write_spec_ko
474	);
475
476	fifo_request.push(tab_request [i]);
477
478	if (is_operation_memory_store(operation))
479	{
480	cycle = cycle+((rand()%(10))-4);
481
482	if (cycle <= store_queue_cycle[packet_id])
483	cycle = store_queue_cycle[packet_id]+1;
484
485	fifo_request.push(MemoryRequest_t(cycle,
486	context_id,
487	packet_id,
488	(write_spec_ko==true)?OPERATION_MEMORY_STORE_HEAD_KO:OPERATION_MEMORY_STORE_HEAD_OK,
489	type,
490	store_queue_ptr_write_old,
491	0,
492	0,
493	0,
494	0,
495	0,
496	0,
497	write_spec_ko));
498	}
499
500	// update nb cycle ?
501	if (is_operation_memory_store(operation))
502	{
503	store_queue_cycle[packet_id] = cycle;
504	}
505	else
506	{
507	load_queue_cycle [packet_id] = cycle;
508	}
509	}
510
511	while (nb_request_memory_out < nb_request)
512	{
513	bool can_execute = false;
514
515	if (is_operation_memory_store(fifo_request.top()._operation))
516	can_execute = (not store_queue_use [fifo_request.top()._store_queue_ptr_write]) or is_operation_memory_store_head(fifo_request.top()._operation);
517	else
518	can_execute = not load_queue_use [fifo_request.top()._load_queue_ptr_write];
519
520	in_MEMORY_IN_VAL ->write((not fifo_request.empty()) and
521	can_execute and
522	(sc_simulation_time() >= fifo_request.top()._cycle));
523
524	in_MEMORY_IN_CONTEXT_ID ->write (fifo_request.top()._context_id );
525	in_MEMORY_IN_PACKET_ID ->write (fifo_request.top()._packet_id );
526	in_MEMORY_IN_OPERATION ->write (fifo_request.top()._operation );
527	in_MEMORY_IN_TYPE ->write (fifo_request.top()._type );
528	in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);
529	in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );
530	in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat );
531	in_MEMORY_IN_DATA_RA ->write (fifo_request.top()._data_ra );
532	in_MEMORY_IN_DATA_RB ->write (fifo_request.top()._data_rb );
533	in_MEMORY_IN_WRITE_RD ->write (fifo_request.top()._write_rd );
534	in_MEMORY_IN_NUM_REG_RD ->write (fifo_request.top()._num_reg_rd );
535
536	in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
537
538	SC_START(0);
539
540	SC_START(1);
541
542	LABEL("MEMORY_IN : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));
543	if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
544	{
545	LABEL(" * Accepted MEMORY_IN : " + toString(nb_request_memory_in));
546	cout << fifo_request.top();
547
548	if (is_operation_memory_store(fifo_request.top()._operation))
549	{
550	if (not is_operation_memory_store_head(fifo_request.top()._operation))
551	store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;
552	}
553	else
554	load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;
555
556	fifo_request.pop();
557
558	nb_request_memory_in ++;
559	}
560
561	LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read()));
562	if (out_MEMORY_OUT_VAL->read() and in_MEMORY_OUT_ACK->read())
563	{
564	LABEL(" * Accepted MEMORY_OUT : " + toString(out_MEMORY_OUT_PACKET_ID->read()));
565
566	if (is_operation_memory_store(tab_request[out_MEMORY_OUT_PACKET_ID->read()]._operation))
567	store_queue_use [tab_request[out_MEMORY_OUT_PACKET_ID->read()]._store_queue_ptr_write] = false;
568	else
569	load_queue_use [tab_request[out_MEMORY_OUT_PACKET_ID->read()]._load_queue_ptr_write] = false;
570
571	nb_request_memory_out ++;
572	}
573	}
574	}
575
576	/********************************************************
577	* Simulation - End
578	********************************************************/
579
580	TEST_OK ("End of Simulation");
581	delete _time;
582	cout << "<" << name << "> ............ Stop Simulation" << endl;
583
584	delete in_CLOCK;
585	delete in_NRESET;
586
587	delete in_MEMORY_IN_VAL ;
588	delete out_MEMORY_IN_ACK ;
589	delete in_MEMORY_IN_CONTEXT_ID ;
590	delete in_MEMORY_IN_PACKET_ID ;
591	delete in_MEMORY_IN_OPERATION ;
592	delete in_MEMORY_IN_TYPE ;
593	delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
594	delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
595	//delete in_MEMORY_IN_HAS_IMMEDIAT ;
596	delete in_MEMORY_IN_IMMEDIAT ;
597	delete in_MEMORY_IN_DATA_RA ;
598	delete in_MEMORY_IN_DATA_RB ;
599	//delete in_MEMORY_IN_DATA_RC ;
600	delete in_MEMORY_IN_WRITE_RD ;
601	delete in_MEMORY_IN_NUM_REG_RD ;
602	//delete in_MEMORY_IN_WRITE_RE ;
603	//delete in_MEMORY_IN_NUM_REG_RE ;
604
605	delete out_MEMORY_OUT_VAL ;
606	delete in_MEMORY_OUT_ACK ;
607	delete out_MEMORY_OUT_CONTEXT_ID;
608	delete out_MEMORY_OUT_PACKET_ID ;
609	delete out_MEMORY_OUT_OPERATION ;
610	delete out_MEMORY_OUT_TYPE ;
611	delete out_MEMORY_OUT_WRITE_RD ;
612	delete out_MEMORY_OUT_NUM_REG_RD;
613	delete out_MEMORY_OUT_DATA_RD ;
614	//delete out_MEMORY_OUT_WRITE_RE ;
615	//delete out_MEMORY_OUT_NUM_REG_RE;
616	//delete out_MEMORY_OUT_DATA_RE ;
617	delete out_MEMORY_OUT_EXCEPTION ;
618
619	delete out_DCACHE_REQ_VAL ;
620	delete in_DCACHE_REQ_ACK ;
621	delete out_DCACHE_REQ_CONTEXT_ID;
622	delete out_DCACHE_REQ_PACKET_ID ;
623	delete out_DCACHE_REQ_ADDRESS ;
624	delete out_DCACHE_REQ_TYPE ;
625	delete out_DCACHE_REQ_UNCACHED ;
626	delete out_DCACHE_REQ_WDATA ;
627
628	delete in_DCACHE_RSP_VAL ;
629	delete out_DCACHE_RSP_ACK ;
630	delete in_DCACHE_RSP_CONTEXT_ID;
631	delete in_DCACHE_RSP_PACKET_ID ;
632	delete in_DCACHE_RSP_RDATA ;
633	delete in_DCACHE_RSP_ERROR ;
634
635	delete [] out_BYPASS_MEMORY_VAL ;
636	delete [] out_BYPASS_MEMORY_CONTEXT_ID;
637	delete [] out_BYPASS_MEMORY_NUM_REG ;
638	delete [] out_BYPASS_MEMORY_DATA ;
639
640	#endif
641
642	delete _Load_store_unit;
643	#ifdef STATISTICS
644	delete _parameters_statistics;
645	#endif
646	}

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