Context Navigation

source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test1.cpp @ 71

Last change on this file since 71 was 71, checked in by rosiere, 16 years ago
Modification of Statisctics Add a new systemC component : Load_Store_Queue (tested with one benchmark and one configuration). Store don't supported the Data Buss Error (Load is supported)
File size: 33.2 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include <queue>
10	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
11
12	#define NB_ITERATION 1
13	#define CYCLE_MAX (1024*NB_ITERATION)
14
15	#define LABEL(str) \
16	{ \
17	cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \
18	} while(0)
19
20	#define SC_START(cycle_offset) \
21	do \
22	{ \
23	/cout << "SC_START (begin)" << endl;/ \
24	\
25	uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
26	if (cycle_offset != 0) \
27	{ \
28	cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \
29	} \
30	\
31	if (cycle_current > CYCLE_MAX) \
32	{ \
33	TEST_KO("Maximal cycles Reached"); \
34	} \
35	sc_start(cycle_offset); \
36	/cout << "SC_START (end )" << endl;/ \
37	} while(0)
38
39
40	//===================================================================={test}
41	void test1 (string name,
42	morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param)
43	{
44	cout << "<" << name << "> : Simulation SystemC" << endl;
45
46	#ifdef STATISTICS
47	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
48	#endif
49
50	Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(),
51	#ifdef STATISTICS
52	_parameters_statistics,
53	#endif
54	_param);
55
56	#ifdef SYSTEMC
57	/*********************************************************************
58	* Déclarations des signaux
59	*********************************************************************/
60	string rename = "";
61
62	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
63	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
64
65	sc_signal<Tcontrol_t > * in_MEMORY_IN_VAL = new sc_signal<Tcontrol_t > (rename.c_str());
66	sc_signal<Tcontrol_t > * out_MEMORY_IN_ACK = new sc_signal<Tcontrol_t > (rename.c_str());
67	sc_signal<Tcontext_t > * in_MEMORY_IN_CONTEXT_ID = new sc_signal<Tcontext_t > (rename.c_str());
68	sc_signal<Tcontext_t > * in_MEMORY_IN_FRONT_END_ID = new sc_signal<Tcontext_t > (rename.c_str());
69	sc_signal<Tcontext_t > * in_MEMORY_IN_OOO_ENGINE_ID = new sc_signal<Tcontext_t > (rename.c_str());
70	sc_signal<Tpacket_t > * in_MEMORY_IN_PACKET_ID = new sc_signal<Tpacket_t > (rename.c_str());
71	sc_signal<Toperation_t > * in_MEMORY_IN_OPERATION = new sc_signal<Toperation_t > (rename.c_str());
72	sc_signal<Ttype_t > * in_MEMORY_IN_TYPE = new sc_signal<Ttype_t > (rename.c_str());
73	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
74	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
75	//sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str());
76	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_IMMEDIAT = new sc_signal<Tgeneral_data_t > (rename.c_str());
77	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RA = new sc_signal<Tgeneral_data_t > (rename.c_str());
78	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RB = new sc_signal<Tgeneral_data_t > (rename.c_str());
79	//sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str());
80	// sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str());
81	sc_signal<Tgeneral_address_t> * in_MEMORY_IN_NUM_REG_RD = new sc_signal<Tgeneral_address_t> (rename.c_str());
82	//sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str());
83	//sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str());
84
85	sc_signal<Tcontrol_t > * out_MEMORY_OUT_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
86	sc_signal<Tcontrol_t > * in_MEMORY_OUT_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
87	sc_signal<Tcontext_t > * out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
88	sc_signal<Tcontext_t > * out_MEMORY_OUT_FRONT_END_ID = new sc_signal<Tcontext_t >(rename.c_str());
89	sc_signal<Tcontext_t > * out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >(rename.c_str());
90	sc_signal<Tpacket_t > * out_MEMORY_OUT_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
91	sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RD = new sc_signal<Tcontrol_t >(rename.c_str());
92	sc_signal<Tgeneral_address_t> * out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str());
93	sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_DATA_RD = new sc_signal<Tgeneral_data_t >(rename.c_str());
94	//sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str());
95	//sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str());
96	//sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str());
97	sc_signal<Texception_t > * out_MEMORY_OUT_EXCEPTION = new sc_signal<Texception_t >(rename.c_str());
98
99	sc_signal<Tcontrol_t > * out_DCACHE_REQ_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
100	sc_signal<Tcontrol_t > * in_DCACHE_REQ_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
101	sc_signal<Tcontext_t > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
102	sc_signal<Tpacket_t > * out_DCACHE_REQ_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
103	sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS = new sc_signal<Tdcache_address_t >(rename.c_str());
104	sc_signal<Tdcache_type_t > * out_DCACHE_REQ_TYPE = new sc_signal<Tdcache_type_t >(rename.c_str());
105	sc_signal<Tdcache_data_t > * out_DCACHE_REQ_WDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
106
107	sc_signal<Tcontrol_t > * in_DCACHE_RSP_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
108	sc_signal<Tcontrol_t > * out_DCACHE_RSP_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
109	sc_signal<Tcontext_t > * in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
110	sc_signal<Tpacket_t > * in_DCACHE_RSP_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
111	sc_signal<Tdcache_data_t > * in_DCACHE_RSP_RDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
112	sc_signal<Tdcache_error_t > * in_DCACHE_RSP_ERROR = new sc_signal<Tdcache_error_t >(rename.c_str());
113
114	sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_size_load_queue];
115	sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_size_load_queue];
116	sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_size_load_queue];
117	sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_size_load_queue];
118
119	for (uint32_t i=0; i<_param->_size_load_queue; i++)
120	{
121	out_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t >(rename.c_str());
122	out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t >(rename.c_str());
123	out_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t>(rename.c_str());
124	out_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t >(rename.c_str());
125	}
126
127	/********************************************************
128	* Instanciation
129	********************************************************/
130
131	cout << "<" << name << "> Instanciation of _Load_store_unit" << endl;
132
133	((_Load_store_unit->in_CLOCK)) ((in_CLOCK));
134	((_Load_store_unit->in_NRESET)) ((in_NRESET));
135
136	((_Load_store_unit-> in_MEMORY_IN_VAL ))(( in_MEMORY_IN_VAL ));
137	((_Load_store_unit->out_MEMORY_IN_ACK ))((out_MEMORY_IN_ACK ));
138	if (_param->_have_port_context_id)
139	((_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID ))(( in_MEMORY_IN_CONTEXT_ID ));
140	if (_param->_have_port_front_end_id)
141	((_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID ))(( in_MEMORY_IN_FRONT_END_ID ));
142	if (_param->_have_port_ooo_engine_id)
143	((_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID ))(( in_MEMORY_IN_OOO_ENGINE_ID ));
144	if (_param->_have_port_packet_id)
145	((_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(( in_MEMORY_IN_PACKET_ID ));
146	((_Load_store_unit-> in_MEMORY_IN_OPERATION ))(( in_MEMORY_IN_OPERATION ));
147	((_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
148	((_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
149	//((_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(( in_MEMORY_IN_HAS_IMMEDIAT ));
150	((_Load_store_unit-> in_MEMORY_IN_IMMEDIAT ))(( in_MEMORY_IN_IMMEDIAT ));
151	((_Load_store_unit-> in_MEMORY_IN_DATA_RA ))(( in_MEMORY_IN_DATA_RA ));
152	((_Load_store_unit-> in_MEMORY_IN_DATA_RB ))(( in_MEMORY_IN_DATA_RB ));
153	//((_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(( in_MEMORY_IN_DATA_RC ));
154	// ((_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(( in_MEMORY_IN_WRITE_RD ));
155	((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD ))(( in_MEMORY_IN_NUM_REG_RD ));
156	//((_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(( in_MEMORY_IN_WRITE_RE ));
157	//((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(( in_MEMORY_IN_NUM_REG_RE ));
158
159	((_Load_store_unit->out_MEMORY_OUT_VAL ))((out_MEMORY_OUT_VAL ));
160	((_Load_store_unit-> in_MEMORY_OUT_ACK ))(( in_MEMORY_OUT_ACK ));
161	if (_param->_have_port_context_id)
162	((_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))((out_MEMORY_OUT_CONTEXT_ID ));
163	if (_param->_have_port_front_end_id)
164	((_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID ))((out_MEMORY_OUT_FRONT_END_ID ));
165	if (_param->_have_port_ooo_engine_id)
166	((_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))((out_MEMORY_OUT_OOO_ENGINE_ID ));
167	if (_param->_have_port_packet_id)
168	((_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))((out_MEMORY_OUT_PACKET_ID ));
169	((_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))((out_MEMORY_OUT_WRITE_RD ));
170	((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))((out_MEMORY_OUT_NUM_REG_RD ));
171	((_Load_store_unit->out_MEMORY_OUT_DATA_RD ))((out_MEMORY_OUT_DATA_RD ));
172	//((_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))((out_MEMORY_OUT_WRITE_RE ));
173	//((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))((out_MEMORY_OUT_NUM_REG_RE ));
174	//((_Load_store_unit->out_MEMORY_OUT_DATA_RE ))((out_MEMORY_OUT_DATA_RE ));
175	((_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))((out_MEMORY_OUT_EXCEPTION ));
176
177	((_Load_store_unit->out_DCACHE_REQ_VAL ))((out_DCACHE_REQ_VAL ));
178	((_Load_store_unit-> in_DCACHE_REQ_ACK ))(( in_DCACHE_REQ_ACK ));
179	if (_param->_have_port_dcache_context_id)
180	((_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))((out_DCACHE_REQ_CONTEXT_ID));
181	((_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))((out_DCACHE_REQ_PACKET_ID ));
182	((_Load_store_unit->out_DCACHE_REQ_ADDRESS ))((out_DCACHE_REQ_ADDRESS ));
183	((_Load_store_unit->out_DCACHE_REQ_TYPE ))((out_DCACHE_REQ_TYPE ));
184	((_Load_store_unit->out_DCACHE_REQ_WDATA ))((out_DCACHE_REQ_WDATA ));
185
186	((_Load_store_unit-> in_DCACHE_RSP_VAL ))(( in_DCACHE_RSP_VAL ));
187	((_Load_store_unit->out_DCACHE_RSP_ACK ))((out_DCACHE_RSP_ACK ));
188	if (_param->_have_port_dcache_context_id)
189	((_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(( in_DCACHE_RSP_CONTEXT_ID));
190	((_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(( in_DCACHE_RSP_PACKET_ID ));
191	((_Load_store_unit-> in_DCACHE_RSP_RDATA ))(( in_DCACHE_RSP_RDATA ));
192	((_Load_store_unit-> in_DCACHE_RSP_ERROR ))(( in_DCACHE_RSP_ERROR ));
193
194	if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
195	{
196	for (uint32_t i=0; i<_param->_size_load_queue; i++)
197	{
198	((_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))((out_BYPASS_MEMORY_VAL [i]));
199	if (_param->_have_port_ooo_engine_id)
200	((_Load_store_unit->out_BYPASS_MEMORY_OOO_ENGINE_ID [i]))((out_BYPASS_MEMORY_OOO_ENGINE_ID [i]));
201	((_Load_store_unit->out_BYPASS_MEMORY_NUM_REG [i]))((out_BYPASS_MEMORY_NUM_REG [i]));
202	((_Load_store_unit->out_BYPASS_MEMORY_DATA [i]))((out_BYPASS_MEMORY_DATA [i]));
203	}
204	}
205	cout << "<" << name << "> Start Simulation ............" << endl;
206	Time * _time = new Time();
207
208	/********************************************************
209	* Simulation - Begin
210	********************************************************/
211
212	// Initialisation
213
214	const uint32_t seed = 0;
215	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
216
217	srand(seed);
218
219	const uint32_t nb_request = _param->_nb_packet;
220	const uint32_t nb_word = nb_request;
221
222	//const int32_t percent_transaction_memory_in = 100;
223	const int32_t percent_transaction_memory_out = 75;
224	const int32_t percent_transaction_dcache = 75;
225
226	const int32_t percent_exception = 0;
227	const int32_t percent_type_load = 0;
228	const int32_t percent_type_store = 50;
229	const int32_t percent_miss_spec = 20;
230
231	const uint32_t miss_rate = 10;
232	const uint32_t miss_penality = 5;
233
234	if ((percent_type_load +
235	percent_type_store ) > 100)
236	TEST_KO("sum of percent_type > 100");
237
238	const int32_t seuil_type_load = percent_type_load;
239	const int32_t seuil_type_store = percent_type_store+percent_type_load;
240
241	uint32_t nb_request_memory_in ;
242	uint32_t nb_request_memory_out;
243	uint32_t nb_request_dcache ;
244
245	MemoryRequest_t tab_request [nb_request];
246	priority_queue<MemoryRequest_t> fifo_request;
247
248	// emulation of memory
249	Memory_t * _memory = new Memory_t (1<<_param->_size_dcache_context_id, nb_word, _param->_size_general_data);
250	Cache_t * _cache = new Cache_t (miss_rate, miss_penality);
251
252
253	SC_START(0);
254
255	LABEL("Initialisation");
256
257	in_MEMORY_IN_VAL ->write(0);
258	in_MEMORY_OUT_ACK->write(0);
259	in_DCACHE_REQ_ACK->write(0);
260	in_DCACHE_RSP_VAL->write(0);
261
262	in_NRESET ->write(0);
263	SC_START(5);
264	in_NRESET ->write(5);
265
266	LABEL("Loop of Test");
267
268	try
269	{
270	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
271	{
272	LABEL("Iteration "+toString(iteration));
273
274	LABEL("Structure's initialisation");
275
276	nb_request_memory_in = 0;
277	nb_request_memory_out = 0;
278	nb_request_dcache = 0;
279
280	// Fill the request_queue
281
282	Tlsq_ptr_t store_queue_ptr_write = 0;
283	Tlsq_ptr_t load_queue_ptr_write = 0;
284
285	bool store_queue_use [_param->_size_store_queue];
286	uint32_t nb_store_slot_use = 0;
287	bool load_queue_use [_param->_size_load_queue ];
288
289	for (uint32_t i=0; i<_param->_size_store_queue; i++)
290	store_queue_use [i] = false;
291	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
292	load_queue_use [i] = false;
293
294	double current_cycle = sc_simulation_time();
295	double cycle_min = current_cycle;
296
297	Toperation_t operation_store [4] = {OPERATION_MEMORY_STORE_8,
298	OPERATION_MEMORY_STORE_16,
299	OPERATION_MEMORY_STORE_32,
300	OPERATION_MEMORY_STORE_64};
301
302	Toperation_t operation_load [8] = {OPERATION_MEMORY_LOAD_8_Z,
303	OPERATION_MEMORY_LOAD_8_S,
304	OPERATION_MEMORY_LOAD_16_Z,
305	OPERATION_MEMORY_LOAD_16_S,
306	OPERATION_MEMORY_LOAD_32_Z,
307	OPERATION_MEMORY_LOAD_32_S,
308	OPERATION_MEMORY_LOAD_64_Z,
309	OPERATION_MEMORY_LOAD_64_S};
310
311	Toperation_t operation_other [5] = {OPERATION_MEMORY_LOCK ,
312	OPERATION_MEMORY_INVALIDATE ,
313	OPERATION_MEMORY_PREFETCH ,
314	OPERATION_MEMORY_FLUSH ,
315	OPERATION_MEMORY_SYNCHRONIZATION};
316
317
318	const uint32_t nb_operation_store = (log2(_param->_size_general_data/8)+1);
319	const uint32_t nb_operation_load = 2*(log2(_param->_size_general_data/8)+1);
320	const uint32_t nb_operation_other = 5;
321
322	LABEL("Fifo request initialisation");
323	// Init fifo_request
324	for (uint32_t i=0; i<nb_request; i++)
325	{
326	double cycle;
327	Tcontext_t context_id = 0;
328	Tcontext_t front_end_id = 0;
329	Tcontext_t ooo_engine_id = rand () % _param->_nb_ooo_engine;
330	Tpacket_t packet_id = i;
331	Tlsq_ptr_t store_queue_ptr_write_old = store_queue_ptr_write;
332	Tlsq_ptr_t load_queue_ptr_write_old = load_queue_ptr_write ;
333	Toperation_t operation;
334
335	int32_t percent = rand()%100;
336
337	uint32_t size_queue;
338
339	if (percent < seuil_type_load)
340	{
341	LABEL(" * LOAD");
342	operation = operation_load[(rand()%nb_operation_load)];
343	size_queue = _param->_size_load_queue;
344	load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
345	}
346	else
347	{
348	if (percent < seuil_type_store)
349	{
350	LABEL(" * STORE");
351
352
353	operation = operation_store[(rand()%nb_operation_store)];
354	size_queue = _param->_size_store_queue;
355	store_queue_ptr_write = (store_queue_ptr_write+1) % (size_queue);
356	}
357	else
358	{
359	LABEL(" * OTHERS");
360	operation = operation_other[(rand()%nb_operation_other)];
361	// operation = operation_other[4];
362	size_queue = _param->_size_load_queue;
363	load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
364	}
365	}
366
367	cycle = cycle_min;
368	cycle_min ++;
369
370	Ttype_t type = TYPE_MEMORY;
371	Tgeneral_data_t address = rand()%(nb_word);
372	Tgeneral_data_t offset = rand()%(nb_word);
373
374	// LABEL ("Address step 1 : "+toString(address)+" - "+toString(offset));
375
376	percent = rand()%100;
377	if (percent > percent_exception)
378	address = address & (~ mask_memory_access(operation));
379
380	// LABEL ("Address step 2 : "+toString(address)+" - mask : "+toString((~ mask_memory_access(operation))));
381
382	if (offset > address) // max
383	offset = address;
384
385	Tgeneral_data_t immediat = offset;
386	Tgeneral_data_t data_ra = address - offset;
387
388	// LABEL ("Address step 3 : "+toString(address)+", "+toString(data_ra)+" - "+toString(immediat));
389
390	Tgeneral_data_t data_rb = static_cast<Tgeneral_data_t>(rand());
391	Tcontrol_t write_rd = 0;
392	Tgeneral_address_t num_reg_rd = 0;
393	bool write_spec_ko = is_operation_memory_store(operation) and ((rand()%100)<percent_miss_spec);
394
395	tab_request [i].modif(cycle ,
396	context_id ,
397	front_end_id ,
398	ooo_engine_id ,
399	packet_id ,
400	operation ,
401	type ,
402	store_queue_ptr_write_old,
403	load_queue_ptr_write_old ,
404	immediat ,
405	data_ra ,
406	data_rb ,
407	write_rd ,
408	num_reg_rd ,
409	write_spec_ko);
410
411	cout << tab_request [i] << endl;
412
413	fifo_request.push(tab_request [i]);
414
415	double cycle_head = 0;
416
417	if (is_operation_memory_store(operation))
418	{
419	cycle_head = cycle_min;
420	cycle_min ++;
421
422	cout << " * Write head : " << toString(cycle_head)
423	<< endl
424	<< endl;
425
426	fifo_request.push(MemoryRequest_t(cycle_head,
427	context_id,
428	front_end_id,
429	ooo_engine_id,
430	packet_id,
431	(write_spec_ko==true)?OPERATION_MEMORY_STORE_HEAD_KO:OPERATION_MEMORY_STORE_HEAD_OK,
432	type,
433	store_queue_ptr_write_old,
434	0,
435	0,
436	0,
437	0,
438	0,
439	0,
440	write_spec_ko));
441	}
442	}
443
444	LABEL("Simulation of this iteration ...");
445
446	while (nb_request_memory_out < nb_request)
447	{
448	cout << "*********************************************" << endl;
449	cout << "Dump STORE_QUEUE_USE : " << endl;
450	cout << " use " << nb_store_slot_use << endl;
451	for (uint32_t i=0; i<_param->_size_store_queue; i++)
452	cout << " [" << i << "] " << store_queue_use [i] << endl;
453	cout << "Dump LOAD_QUEUE_USE : " << endl;
454	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
455	cout << " [" << i << "] " << load_queue_use [i] << endl;
456	cout << "*********************************************" << endl;
457
458
459	// *** MEMORY_IN ***
460
461	// memory_in_val depends of three factors :
462	// 1) request's fifo is not empty ?
463	// 2) the slot destination is free ?
464	// 3) The head of request's fifo can be issue : the number of cycle is more than current cycle
465
466	bool can_execute = false;
467
468	if (is_operation_memory_store(fifo_request.top()._operation))
469	can_execute = (not store_queue_use [fifo_request.top()._store_queue_ptr_write] and (nb_store_slot_use < _param->_size_store_queue-1)) or is_operation_memory_store_head(fifo_request.top()._operation);
470	else
471	can_execute = not load_queue_use [fifo_request.top()._load_queue_ptr_write];
472
473	in_MEMORY_IN_VAL ->write((not fifo_request.empty()) and
474	can_execute and
475	(sc_simulation_time() >= fifo_request.top()._cycle));
476
477	if (_param->_have_port_context_id)
478	in_MEMORY_IN_CONTEXT_ID ->write (fifo_request.top()._context_id );
479	if (_param->_have_port_front_end_id)
480	in_MEMORY_IN_FRONT_END_ID ->write (fifo_request.top()._front_end_id );
481	if (_param->_have_port_ooo_engine_id)
482	in_MEMORY_IN_OOO_ENGINE_ID ->write (fifo_request.top()._ooo_engine_id );
483	if (_param->_have_port_packet_id)
484	in_MEMORY_IN_PACKET_ID ->write (fifo_request.top()._packet_id );
485	in_MEMORY_IN_OPERATION ->write (fifo_request.top()._operation );
486	in_MEMORY_IN_TYPE ->write (fifo_request.top()._type );
487	in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);
488	in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );
489	in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat );
490	in_MEMORY_IN_DATA_RA ->write (fifo_request.top()._data_ra );
491	in_MEMORY_IN_DATA_RB ->write (fifo_request.top()._data_rb );
492	// in_MEMORY_IN_WRITE_RD ->write (fifo_request.top()._write_rd );
493	in_MEMORY_IN_NUM_REG_RD ->write (fifo_request.top()._num_reg_rd );
494
495	in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
496
497	// *** DCACHE_REQ ***
498	in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);
499
500	// *** DCACHE_RSP ***
501	bool have_rsp = _cache->have_rsp ();
502	in_DCACHE_RSP_VAL->write(have_rsp);
503
504	if (have_rsp)
505	{
506	in_DCACHE_RSP_CONTEXT_ID->write(_cache->front()._context_id);
507	in_DCACHE_RSP_PACKET_ID ->write(_cache->front()._packet_id );
508	in_DCACHE_RSP_RDATA ->write(_cache->front()._rdata );
509	in_DCACHE_RSP_ERROR ->write(_cache->front()._error );
510	}
511
512	SC_START(0);
513
514	LABEL("MEMORY_IN : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));
515	LABEL(" * fifo_request.empty : "+toString(fifo_request.empty()));
516	LABEL(" * fifo_request.top.cycle : "+toString(fifo_request.top()._cycle));
517	LABEL(" * fifo_request.top.store_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._store_queue_ptr_write)));
518	LABEL(" * fifo_request.top.load_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._load_queue_ptr_write)));
519	LABEL(" * fifo_request.top.operation : "+toString(static_cast<uint32_t>(fifo_request.top()._operation )));
520	LABEL(" * can_execute : "+toString(can_execute));
521
522	if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
523	{
524	LABEL(" * Accepted MEMORY_IN : " + toString(nb_request_memory_in));
525	cout << fifo_request.top();
526
527	if (is_operation_memory_store(fifo_request.top()._operation))
528	{
529	if (not is_operation_memory_store_head(fifo_request.top()._operation))
530	{
531	store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;
532	nb_store_slot_use ++;
533	}
534	}
535	else
536	load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;
537
538	fifo_request.pop();
539
540	nb_request_memory_in ++;
541	}
542
543	LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read()));
544	if (out_MEMORY_OUT_VAL->read() and in_MEMORY_OUT_ACK->read())
545	{
546	Tpacket_t packet_id = out_MEMORY_OUT_PACKET_ID->read();
547
548	LABEL(" * Accepted MEMORY_OUT : " + toString(packet_id));
549
550	if (is_operation_memory_store(tab_request[packet_id]._operation))
551	{
552	store_queue_use [tab_request[packet_id]._store_queue_ptr_write] = false;
553	nb_store_slot_use --;
554	}
555	else
556	load_queue_use [tab_request[packet_id]._load_queue_ptr_write] = false;
557
558	nb_request_memory_out ++;
559
560	// a lot of test
561	TEST(Tcontext_t , out_MEMORY_OUT_CONTEXT_ID ->read(), tab_request[packet_id]._context_id );
562	TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id );
563	TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id);
564	TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID ->read(), tab_request[packet_id]._packet_id );
565	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), tab_request[packet_id]._write_rd );
566	TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD ->read(), tab_request[packet_id]._num_reg_rd );
567
568	Tgeneral_data_t address = tab_request[packet_id]._data_ra + tab_request[packet_id]._immediat;
569	if (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation))))
570	TEST(Texception_t , out_MEMORY_OUT_EXCEPTION ->read(), EXCEPTION_MEMORY_ALIGNMENT);
571	else
572	{
573	if (tab_request[packet_id]._write_spec_ko)
574	TEST(Texception_t, out_MEMORY_OUT_EXCEPTION ->read(), EXCEPTION_MEMORY_MISS_SPECULATION);
575	else
576	{
577	TEST(Texception_t, out_MEMORY_OUT_EXCEPTION ->read(), EXCEPTION_MEMORY_NONE);
578
579	if (is_operation_memory_load(tab_request[packet_id]._operation))
580	{
581	Tgeneral_data_t read_lsq = _memory->read_lsq (((tab_request[packet_id]._ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) \|
582	(tab_request[packet_id]._front_end_id <<(_param->_size_context_id)) \|
583	(tab_request[packet_id]._context_id)),
584	(tab_request[packet_id]._immediat +
585	tab_request[packet_id]._data_ra),
586	tab_request[packet_id]._operation);
587	cout << "MEMORY_OUT is a LOAD" << endl
588	<< " * operation : " << tab_request[packet_id]._operation << endl
589	<< std::hex
590	<< " * address : " << (tab_request[packet_id]._immediat +
591	tab_request[packet_id]._data_ra) << endl
592	<< " * read_lsq : " << read_lsq << endl
593	<< " * memory_out_data : " << out_MEMORY_OUT_DATA_RD->read() << endl
594	<< std::dec;
595
596	// TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), read_lsq);
597	}
598	}
599	}
600	}
601
602	LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read()));
603	if (out_DCACHE_REQ_VAL->read() and in_DCACHE_REQ_ACK->read())
604	{
605	Tcontext_t context_id;
606	Tpacket_t packet_id ;
607	if (_param->_have_port_dcache_context_id)
608	context_id = out_DCACHE_REQ_CONTEXT_ID->read();
609	else
610	context_id = 0;
611
612	packet_id = (out_DCACHE_REQ_PACKET_ID ->read())>>1;
613
614	LABEL(" * Accepted DCACHE_REQ : " + toString(packet_id));
615
616	// TEST(Tcontext_t ,out_DCACHE_REQ_CONTEXT_ID->read(),((tab_request[packet_id]._ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) \|
617	// (tab_request[packet_id]._front_end_id <<(_param->_size_context_id)) \|
618	// (tab_request[packet_id]._context_id)));
619	// TEST(Tdcache_address_t,out_DCACHE_REQ_ADDRESS ->read(),(tab_request[packet_id]._immediat +
620	// tab_request[packet_id]._data_ra) );
621	// TEST(Tdcache_type_t ,out_DCACHE_REQ_TYPE ->read(), operation_to_dcache_type(operation));
622
623	// if (is_operation_memory_store(operation))
624	// TEST(Tdcache_data_t ,out_DCACHE_REQ_WDATA ->read(),tab_request[packet_id]._data_rb);
625
626	Tdcache_data_t rdata = _memory->access (context_id, out_DCACHE_REQ_ADDRESS->read(), out_DCACHE_REQ_TYPE->read(), out_DCACHE_REQ_WDATA->read());
627
628	// test type : send or not a respons !
629	LABEL(" * rdata : " + toString(rdata));
630
631	if ((out_DCACHE_REQ_TYPE->read() == DCACHE_SYNCHRONIZATION) or
632	(out_DCACHE_REQ_TYPE->read() == DCACHE_LOAD))
633	{
634	LABEL(" * have_dcache_rsp");
635
636	_cache->push (context_id,
637	out_DCACHE_REQ_PACKET_ID ->read(),
638	rdata ,
639	0);
640	}
641	}
642
643	LABEL("DCACHE_RSP : "+toString(in_DCACHE_RSP_VAL->read())+" - "+toString(out_DCACHE_RSP_ACK ->read()));
644	if (in_DCACHE_RSP_VAL->read() and out_DCACHE_RSP_ACK->read())
645	{
646	_cache->pop();
647	}
648
649	_cache->end_cycle();
650
651	SC_START(1);
652	}
653	}
654	}
655	catch (morpheo::ErrorMorpheo & error)
656	{
657	_memory->trace();
658	throw (error);
659	}
660
661	_memory->trace();
662
663
664	/********************************************************
665	* Simulation - End
666	********************************************************/
667
668	TEST_OK ("End of Simulation");
669	delete _time;
670	cout << "<" << name << "> ............ Stop Simulation" << endl;
671
672	delete in_CLOCK;
673	delete in_NRESET;
674
675	delete in_MEMORY_IN_VAL ;
676	delete out_MEMORY_IN_ACK ;
677	delete in_MEMORY_IN_CONTEXT_ID ;
678	delete in_MEMORY_IN_FRONT_END_ID ;
679	delete in_MEMORY_IN_OOO_ENGINE_ID ;
680	delete in_MEMORY_IN_PACKET_ID ;
681	delete in_MEMORY_IN_OPERATION ;
682	delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
683	delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
684	//delete in_MEMORY_IN_HAS_IMMEDIAT;
685	delete in_MEMORY_IN_IMMEDIAT ;
686	delete in_MEMORY_IN_DATA_RA ;
687	delete in_MEMORY_IN_DATA_RB ;
688	//delete in_MEMORY_IN_DATA_RC ;
689	// delete in_MEMORY_IN_WRITE_RD ;
690	delete in_MEMORY_IN_NUM_REG_RD ;
691	//delete in_MEMORY_IN_WRITE_RE ;
692	//delete in_MEMORY_IN_NUM_REG_RE ;
693
694	delete out_MEMORY_OUT_VAL ;
695	delete in_MEMORY_OUT_ACK ;
696	delete out_MEMORY_OUT_CONTEXT_ID;
697	delete out_MEMORY_OUT_FRONT_END_ID;
698	delete out_MEMORY_OUT_OOO_ENGINE_ID;
699	delete out_MEMORY_OUT_PACKET_ID ;
700	delete out_MEMORY_OUT_WRITE_RD ;
701	delete out_MEMORY_OUT_NUM_REG_RD;
702	delete out_MEMORY_OUT_DATA_RD ;
703	//delete out_MEMORY_OUT_WRITE_RE ;
704	//delete out_MEMORY_OUT_NUM_REG_RE;
705	//delete out_MEMORY_OUT_DATA_RE ;
706	delete out_MEMORY_OUT_EXCEPTION ;
707
708	delete out_DCACHE_REQ_VAL ;
709	delete in_DCACHE_REQ_ACK ;
710	delete out_DCACHE_REQ_CONTEXT_ID;
711	delete out_DCACHE_REQ_PACKET_ID ;
712	delete out_DCACHE_REQ_ADDRESS ;
713	delete out_DCACHE_REQ_TYPE ;
714	delete out_DCACHE_REQ_WDATA ;
715
716	delete in_DCACHE_RSP_VAL ;
717	delete out_DCACHE_RSP_ACK ;
718	delete in_DCACHE_RSP_CONTEXT_ID;
719	delete in_DCACHE_RSP_PACKET_ID ;
720	delete in_DCACHE_RSP_RDATA ;
721	delete in_DCACHE_RSP_ERROR ;
722
723	if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
724	{
725	delete [] out_BYPASS_MEMORY_VAL ;
726	delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
727	delete [] out_BYPASS_MEMORY_NUM_REG ;
728	delete [] out_BYPASS_MEMORY_DATA ;
729	}
730	#endif
731
732	delete _Load_store_unit;
733	delete _memory;
734	delete _cache;
735	#ifdef STATISTICS
736	delete _parameters_statistics;
737	#endif
738	}

Note: See TracBrowser for help on using the repository browser.

Download in other formats: