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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp @ 71

Last change on this file since 71 was 71, checked in by rosiere, 16 years ago
Modification of Statisctics Add a new systemC component : Load_Store_Queue (tested with one benchmark and one configuration). Store don't supported the Data Buss Error (Load is supported)
File size: 39.6 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include <queue>
10	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
11
12	#define CYCLE_MAX 1024
13
14	#define LABEL(str) \
15	{ \
16	cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \
17	} while(0)
18
19	#define SC_START(cycle_offset) \
20	do \
21	{ \
22	/cout << "SC_START (begin)" << endl;/ \
23	\
24	uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
25	if (cycle_offset != 0) \
26	{ \
27	cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \
28	} \
29	\
30	if (cycle_current > CYCLE_MAX) \
31	{ \
32	TEST_KO("Maximal cycles Reached"); \
33	} \
34	sc_start(cycle_offset); \
35	/cout << "SC_START (end )" << endl;/ \
36	} while(0)
37
38
39	//===================================================================={test}
40	void test2 (void)
41	{
42	std::string name = "Test_Load_store_queue_manual";
43
44	cout << "<" << name << "> : Simulation SystemC" << endl;
45
46
47	morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters
48	(
49	4, //_size_store_queue
50	4, //_size_load_queue
51	2, //_size_speculative_access_queue
52	2, //_nb_port_check
53	SPECULATIVE_LOAD_COMMIT, //_speculative_load
54	1, //_nb_context
55	1, //_nb_front_end
56	2, //_nb_ooo_engine
57	128,//_nb_packet
58	32, //_size_general_data
59	64, //_nb_general_register
60	4, //_nb_operation
61	4 //_nb_type
62	);
63
64	#ifdef STATISTICS
65	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
66	#endif
67
68	Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(),
69	#ifdef STATISTICS
70	_parameters_statistics,
71	#endif
72	_param);
73
74	#ifdef SYSTEMC
75	/*********************************************************************
76	* Déclarations des signaux
77	*********************************************************************/
78	string rename = "";
79
80	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
81	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
82
83	sc_signal<Tcontrol_t > * in_MEMORY_IN_VAL = new sc_signal<Tcontrol_t > (rename.c_str());
84	sc_signal<Tcontrol_t > * out_MEMORY_IN_ACK = new sc_signal<Tcontrol_t > (rename.c_str());
85	sc_signal<Tcontext_t > * in_MEMORY_IN_CONTEXT_ID = new sc_signal<Tcontext_t > (rename.c_str());
86	sc_signal<Tcontext_t > * in_MEMORY_IN_FRONT_END_ID = new sc_signal<Tcontext_t > (rename.c_str());
87	sc_signal<Tcontext_t > * in_MEMORY_IN_OOO_ENGINE_ID = new sc_signal<Tcontext_t > (rename.c_str());
88	sc_signal<Tpacket_t > * in_MEMORY_IN_PACKET_ID = new sc_signal<Tpacket_t > (rename.c_str());
89	sc_signal<Toperation_t > * in_MEMORY_IN_OPERATION = new sc_signal<Toperation_t > (rename.c_str());
90	sc_signal<Ttype_t > * in_MEMORY_IN_TYPE = new sc_signal<Ttype_t > (rename.c_str());
91	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
92	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
93	//sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str());
94	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_IMMEDIAT = new sc_signal<Tgeneral_data_t > (rename.c_str());
95	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RA = new sc_signal<Tgeneral_data_t > (rename.c_str());
96	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RB = new sc_signal<Tgeneral_data_t > (rename.c_str());
97	//sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str());
98	// sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str());
99	sc_signal<Tgeneral_address_t> * in_MEMORY_IN_NUM_REG_RD = new sc_signal<Tgeneral_address_t> (rename.c_str());
100	//sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str());
101	//sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str());
102
103	sc_signal<Tcontrol_t > * out_MEMORY_OUT_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
104	sc_signal<Tcontrol_t > * in_MEMORY_OUT_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
105	sc_signal<Tcontext_t > * out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
106	sc_signal<Tcontext_t > * out_MEMORY_OUT_FRONT_END_ID = new sc_signal<Tcontext_t >(rename.c_str());
107	sc_signal<Tcontext_t > * out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >(rename.c_str());
108	sc_signal<Tpacket_t > * out_MEMORY_OUT_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
109	sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RD = new sc_signal<Tcontrol_t >(rename.c_str());
110	sc_signal<Tgeneral_address_t> * out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str());
111	sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_DATA_RD = new sc_signal<Tgeneral_data_t >(rename.c_str());
112	//sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str());
113	//sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str());
114	//sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str());
115	sc_signal<Texception_t > * out_MEMORY_OUT_EXCEPTION = new sc_signal<Texception_t >(rename.c_str());
116
117	sc_signal<Tcontrol_t > * out_DCACHE_REQ_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
118	sc_signal<Tcontrol_t > * in_DCACHE_REQ_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
119	sc_signal<Tcontext_t > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
120	sc_signal<Tpacket_t > * out_DCACHE_REQ_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
121	sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS = new sc_signal<Tdcache_address_t >(rename.c_str());
122	sc_signal<Tdcache_type_t > * out_DCACHE_REQ_TYPE = new sc_signal<Tdcache_type_t >(rename.c_str());
123	sc_signal<Tdcache_data_t > * out_DCACHE_REQ_WDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
124
125	sc_signal<Tcontrol_t > * in_DCACHE_RSP_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
126	sc_signal<Tcontrol_t > * out_DCACHE_RSP_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
127	sc_signal<Tcontext_t > * in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
128	sc_signal<Tpacket_t > * in_DCACHE_RSP_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
129	sc_signal<Tdcache_data_t > * in_DCACHE_RSP_RDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
130	sc_signal<Tdcache_error_t > * in_DCACHE_RSP_ERROR = new sc_signal<Tdcache_error_t >(rename.c_str());
131
132	sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_size_load_queue];
133	sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_size_load_queue];
134	sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_size_load_queue];
135	sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_size_load_queue];
136
137	for (uint32_t i=0; i<_param->_size_load_queue; i++)
138	{
139	out_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t >(rename.c_str());
140	out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t >(rename.c_str());
141	out_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t>(rename.c_str());
142	out_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t >(rename.c_str());
143	}
144
145	/********************************************************
146	* Instanciation
147	********************************************************/
148
149	cout << "<" << name << "> Instanciation of _Load_store_unit" << endl;
150
151	((_Load_store_unit->in_CLOCK)) ((in_CLOCK));
152	((_Load_store_unit->in_NRESET)) ((in_NRESET));
153
154	((_Load_store_unit-> in_MEMORY_IN_VAL ))(( in_MEMORY_IN_VAL ));
155	((_Load_store_unit->out_MEMORY_IN_ACK ))((out_MEMORY_IN_ACK ));
156	if (_param->_have_port_context_id)
157	((_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID ))(( in_MEMORY_IN_CONTEXT_ID ));
158	if (_param->_have_port_front_end_id)
159	((_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID ))(( in_MEMORY_IN_FRONT_END_ID ));
160	if (_param->_have_port_ooo_engine_id)
161	((_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID ))(( in_MEMORY_IN_OOO_ENGINE_ID ));
162	if (_param->_have_port_packet_id)
163	((_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(( in_MEMORY_IN_PACKET_ID ));
164	((_Load_store_unit-> in_MEMORY_IN_OPERATION ))(( in_MEMORY_IN_OPERATION ));
165	((_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
166	((_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
167	//((_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(( in_MEMORY_IN_HAS_IMMEDIAT ));
168	((_Load_store_unit-> in_MEMORY_IN_IMMEDIAT ))(( in_MEMORY_IN_IMMEDIAT ));
169	((_Load_store_unit-> in_MEMORY_IN_DATA_RA ))(( in_MEMORY_IN_DATA_RA ));
170	((_Load_store_unit-> in_MEMORY_IN_DATA_RB ))(( in_MEMORY_IN_DATA_RB ));
171	//((_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(( in_MEMORY_IN_DATA_RC ));
172	// ((_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(( in_MEMORY_IN_WRITE_RD ));
173	((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD ))(( in_MEMORY_IN_NUM_REG_RD ));
174	//((_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(( in_MEMORY_IN_WRITE_RE ));
175	//((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(( in_MEMORY_IN_NUM_REG_RE ));
176
177	((_Load_store_unit->out_MEMORY_OUT_VAL ))((out_MEMORY_OUT_VAL ));
178	((_Load_store_unit-> in_MEMORY_OUT_ACK ))(( in_MEMORY_OUT_ACK ));
179	if (_param->_have_port_context_id)
180	((_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))((out_MEMORY_OUT_CONTEXT_ID ));
181	if (_param->_have_port_front_end_id)
182	((_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID ))((out_MEMORY_OUT_FRONT_END_ID ));
183	if (_param->_have_port_ooo_engine_id)
184	((_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))((out_MEMORY_OUT_OOO_ENGINE_ID ));
185	if (_param->_have_port_packet_id)
186	((_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))((out_MEMORY_OUT_PACKET_ID ));
187	((_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))((out_MEMORY_OUT_WRITE_RD ));
188	((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))((out_MEMORY_OUT_NUM_REG_RD ));
189	((_Load_store_unit->out_MEMORY_OUT_DATA_RD ))((out_MEMORY_OUT_DATA_RD ));
190	//((_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))((out_MEMORY_OUT_WRITE_RE ));
191	//((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))((out_MEMORY_OUT_NUM_REG_RE ));
192	//((_Load_store_unit->out_MEMORY_OUT_DATA_RE ))((out_MEMORY_OUT_DATA_RE ));
193	((_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))((out_MEMORY_OUT_EXCEPTION ));
194
195	((_Load_store_unit->out_DCACHE_REQ_VAL ))((out_DCACHE_REQ_VAL ));
196	((_Load_store_unit-> in_DCACHE_REQ_ACK ))(( in_DCACHE_REQ_ACK ));
197	if (_param->_have_port_dcache_context_id)
198	((_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))((out_DCACHE_REQ_CONTEXT_ID));
199	((_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))((out_DCACHE_REQ_PACKET_ID ));
200	((_Load_store_unit->out_DCACHE_REQ_ADDRESS ))((out_DCACHE_REQ_ADDRESS ));
201	((_Load_store_unit->out_DCACHE_REQ_TYPE ))((out_DCACHE_REQ_TYPE ));
202	((_Load_store_unit->out_DCACHE_REQ_WDATA ))((out_DCACHE_REQ_WDATA ));
203
204	((_Load_store_unit-> in_DCACHE_RSP_VAL ))(( in_DCACHE_RSP_VAL ));
205	((_Load_store_unit->out_DCACHE_RSP_ACK ))((out_DCACHE_RSP_ACK ));
206	if (_param->_have_port_dcache_context_id)
207	((_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(( in_DCACHE_RSP_CONTEXT_ID));
208	((_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(( in_DCACHE_RSP_PACKET_ID ));
209	((_Load_store_unit-> in_DCACHE_RSP_RDATA ))(( in_DCACHE_RSP_RDATA ));
210	((_Load_store_unit-> in_DCACHE_RSP_ERROR ))(( in_DCACHE_RSP_ERROR ));
211
212	if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
213	{
214	for (uint32_t i=0; i<_param->_size_load_queue; i++)
215	{
216	((_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))((out_BYPASS_MEMORY_VAL [i]));
217	if (_param->_have_port_ooo_engine_id)
218	((_Load_store_unit->out_BYPASS_MEMORY_OOO_ENGINE_ID [i]))((out_BYPASS_MEMORY_OOO_ENGINE_ID [i]));
219	((_Load_store_unit->out_BYPASS_MEMORY_NUM_REG [i]))((out_BYPASS_MEMORY_NUM_REG [i]));
220	((_Load_store_unit->out_BYPASS_MEMORY_DATA [i]))((out_BYPASS_MEMORY_DATA [i]));
221	}
222	}
223	cout << "<" << name << "> Start Simulation ............" << endl;
224	Time * _time = new Time();
225
226	/********************************************************
227	* Simulation - Begin
228	********************************************************/
229
230	// Initialisation
231
232	const uint32_t seed = 0;
233	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
234
235	srand(seed);
236
237	const int32_t percent_transaction_memory_out = 100;
238	const int32_t percent_transaction_dcache = 100;
239	const uint32_t miss_rate = 0;
240	const uint32_t miss_penality = 0;
241
242	uint32_t nb_request_memory_out=0;
243
244	MemoryRequest_t tab_request [_param->_nb_packet];
245	priority_queue<MemoryRequest_t> fifo_request;
246
247	const uint32_t size_memory = 0x100;
248	// emulation of memory
249	Memory_t * _memory = new Memory_t (1<<_param->_size_dcache_context_id, size_memory, _param->_size_general_data);
250	Cache_t * _cache = new Cache_t (miss_rate, miss_penality);
251
252	SC_START(0);
253
254	LABEL("Initialisation");
255
256	in_MEMORY_IN_VAL ->write(0);
257	in_MEMORY_OUT_ACK->write(0);
258	in_DCACHE_REQ_ACK->write(0);
259	in_DCACHE_RSP_VAL->write(0);
260
261	in_NRESET ->write(0);
262	SC_START(5);
263	in_NRESET ->write(5);
264
265	LABEL("Loop of Test");
266
267	try
268	{
269	LABEL("Structure's initialisation");
270
271	bool store_queue_use [_param->_size_store_queue];
272	uint32_t nb_store_slot_use = 0;
273	bool load_queue_use [_param->_size_load_queue ];
274
275	for (uint32_t i=0; i<_param->_size_store_queue; i++)
276	store_queue_use [i] = false;
277	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
278	load_queue_use [i] = false;
279
280
281	//--------------------------------------------------------------------------------------------------------------
282	// c c f o p o t s l i d d w n w
283	// y o r o a p y t o m a a r u r
284	// c n o o c e p o a m t t i m i
285	// l t n _ k r e r d e a a t _ t
286	// e e t e e a e _ d _ _ e r e
287	// x _ n t t _ p i r r _ _ _
288	// t e g _ i p t a a b r g s
289	// _ n i i o t r t d _ p
290	// i d n d n r _ r e
291	// d _ e _ w d c
292	// i _ w r _
293	// d i r i k
294	// d i t o
295	// t e
296	// e
297	//
298	tab_request[ 0].modif( 5,0,0,0, 0,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x10 ,0xdead1234,0,0,0);
299
300	tab_request[ 1].modif(10,0,0,0, 0,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
301
302	// READ 32b
303	tab_request[ 2].modif(12,0,0,0, 2,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,1,0,0xdead1234);
304	tab_request[ 3].modif(13,0,0,0, 3,OPERATION_MEMORY_LOAD_32_S ,TYPE_MEMORY,1,1,0x10 ,0x0 ,0x0 ,1,2,0,0xdead1234);
305
306	// READ 16b
307	tab_request[ 4].modif(14,0,0,0, 4,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,1,2,0x10 ,0x0 ,0x0 ,1,3,0,0x00001234);
308	tab_request[ 5].modif(15,0,0,0, 5,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,1,3,0x12 ,0x0 ,0x0 ,1,4,0,0x0000dead);
309	tab_request[ 6].modif(16,0,0,0, 6,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,5,0,0x00001234);
310	tab_request[ 7].modif(17,0,0,0, 7,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,1,1,0x12 ,0x0 ,0x0 ,1,6,0,0xffffdead);
311
312	// READ 8b
313	tab_request[ 8].modif(18,0,0,0, 8,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,7,0,0x00000034);
314	tab_request[ 9].modif(19,0,0,0, 9,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,1,0x11 ,0x0 ,0x0 ,1,8,0,0x00000012);
315	tab_request[10].modif(20,0,0,0,10,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,2,0x12 ,0x0 ,0x0 ,1,9,0,0x000000ad);
316	tab_request[11].modif(21,0,0,0,11,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,3,0x13 ,0x0 ,0x0 ,1,1,0,0x000000de);
317	tab_request[12].modif(22,0,0,0,12,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,2,0,0x00000034);
318	tab_request[13].modif(23,0,0,0,13,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,1,0x11 ,0x0 ,0x0 ,1,3,0,0x00000012);
319	tab_request[14].modif(24,0,0,0,14,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,2,0x12 ,0x0 ,0x0 ,1,4,0,0xffffffad);
320	tab_request[15].modif(25,0,0,0,15,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,3,0x13 ,0x0 ,0x0 ,1,5,0,0xffffffde);
321
322	// STORE 16b
323	tab_request[16].modif(30,0,0,0,16,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,1,0,0x20 ,0x0 ,0xffffabcd,0,0,0);
324	tab_request[17].modif(31,0,0,0,17,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,2,0,0x22 ,0x0 ,0xffffdcba,0,0,0);
325	tab_request[18].modif(35,0,0,0,18,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
326	tab_request[19].modif(36,0,0,0,19,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
327	tab_request[20].modif(40,0,0,0,20,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,0,0x20 ,0x0 ,0x0 ,1,0,0,0xdcbaabcd);
328
329	// STORE 8b and head / valid out order
330	tab_request[21].modif(50,0,0,0,21,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,3,0,0x1 ,0x4 ,0xffffff56,0,0,0);
331	tab_request[22].modif(55,0,0,0,22,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x1 ,0x0 ,0x0 ,0,0,0);
332	tab_request[23].modif(48,0,0,0,23,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,0,0,0x0 ,0x4 ,0xffffff78,0,0,0);
333	tab_request[24].modif(43,0,0,0,24,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
334	tab_request[25].modif(47,0,0,0,25,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,1,0,0x3 ,0x4 ,0xffffff12,0,0,0);
335	tab_request[26].modif(49,0,0,0,26,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
336	tab_request[27].modif(57,0,0,0,27,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,2,0,0x2 ,0x4 ,0xffffff34,0,0,0);
337	tab_request[28].modif(44,0,0,0,28,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
338	tab_request[29].modif(70,0,0,0,29,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,1,0x2 ,0x2 ,0x0 ,1,0,0,0x12345678);
339
340	// CHECK - with a store not present, store format is >=
341	tab_request[30].modif(180,0,0,0,30,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,3,0,0x0 ,0x30 ,0x21071981,0,0,0);
342	tab_request[31].modif(179,0,0,0,31,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0);
343	tab_request[32].modif(173,0,0,0,32,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x30 ,0x0 ,1,0,0,0x21071981);
344	tab_request[33].modif(174,0,0,0,33,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,0,3,0x0 ,0x30 ,0x0 ,1,0,0,0x00001981);
345	tab_request[34].modif(175,0,0,0,34,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,0,0,0x0 ,0x32 ,0x0 ,1,0,0,0x00002107);
346	tab_request[35].modif(176,0,0,0,35,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,0,1,0x0 ,0x31 ,0x0 ,1,0,0,0x00000019);
347
348	// CHECK - with a store not present, multiple store and format is different
349	tab_request[36].modif(200,0,0,0,36,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x40 ,0xffffffff,0,0,0);
350	tab_request[37].modif(200,0,0,0,37,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
351	tab_request[38].modif(220,0,0,0,38,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,1,0,0x0 ,0x42 ,0xbaba ,0,0,0);
352	tab_request[39].modif(245,0,0,0,39,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
353	tab_request[40].modif(224,0,0,0,40,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,2,0,0x0 ,0x42 ,0xbe ,0,0,0);
354	tab_request[41].modif(240,0,0,0,41,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
355	tab_request[42].modif(228,0,0,0,42,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,3,0,0x0 ,0x40 ,0xf00d ,0,0,0);
356	tab_request[43].modif(235,0,0,0,43,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0);
357	tab_request[44].modif(210,0,0,0,44,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x40 ,0x0 ,1,0,0,0xbabef00d);
358	tab_request[45].modif(211,0,0,0,45,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,2,3,0x0 ,0x40 ,0x0 ,1,0,0,0xbabaffff);
359	tab_request[46].modif(212,0,0,0,46,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,0,0x0 ,0x40 ,0x0 ,1,0,0,0xbabeffff);
360	tab_request[47].modif(213,0,0,0,47,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,3,1,0x0 ,0x42 ,0x0 ,1,0,0,0xffffffbe);
361
362
363	// CHECK - with different ooo_engine_id
364	tab_request[48].modif(300,0,0,0,48,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x0 ,0xdad1900d,0,0,0);
365	tab_request[49].modif(300,0,0,0,49,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
366	tab_request[50].modif(300,0,0,1,50,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x55508570,0,0,0);
367	tab_request[51].modif(300,0,0,1,51,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
368
369
370	tab_request[52].modif(320,0,0,0,52,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,2,2,0x0 ,0x2 ,0x0 ,1,0,0,0xffffdad1);
371	tab_request[53].modif(321,0,0,1,53,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,2,3,0x0 ,0x0 ,0x0 ,1,0,0,0xffff8570);
372
373
374	// with a little exception
375	tab_request[54].modif(330,0,0,1,54,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,2,0,0x0 ,0x0 ,0xffff6996,0,0,1);
376	tab_request[55].modif(340,0,0,1,55,OPERATION_MEMORY_STORE_HEAD_KO,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
377	tab_request[56].modif(322,0,0,1,56,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,3,0,0x0 ,0x1 ,0x0 ,1,0,0,0x00000069); // they are a bypass (because, the cpu go in exception handler ... load is not use)
378	tab_request[57].modif(350,0,0,1,57,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,1,0x0 ,0x0 ,0x0 ,1,0,0,0x55508570); // the memory have not change
379
380
381	// multiple event
382	// * store : miss_spec and aligment, priority : miss_spec > aligment
383	// * load : miss_spec and aligment, priority : miss_spec > aligment
384	tab_request[58].modif(410,0,0,0,58,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,3,0,0x0 ,0x1 ,0x0 ,0,0,1);
385	tab_request[59].modif(415,0,0,0,59,OPERATION_MEMORY_STORE_HEAD_KO,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0);
386
387	tab_request[60].modif(430,0,0,0,60,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x0 ,0x0 ,1,0,0,0xdad1900d);
388	tab_request[61].modif(400,0,0,0,61,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,3,0x0 ,0x3 ,0x0 ,1,0,0); // miss_spec and alignment
389	tab_request[62].modif(450,0,0,0,62,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,0,0x0 ,size_memory ,0x0 ,1,0,0); // bus error and alignement
390	tab_request[63].modif(460,0,0,0,63,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,1,0x0 ,size_memory+1,0x0 ,1,0,0); // bus error and alignement
391
392
393
394	tab_request[64].modif(500,0,0,0,64,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,size_memory ,0x0 ,0,0,0); // bus error
395	tab_request[65].modif(505,0,0,0,65,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
396	tab_request[66].modif(550,0,0,0,65,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,1,0,0,0x55508570); // just to wait the dcache_rsp
397
398	const uint32_t nb_request = 64;//_param->_nb_packet;
399
400	for (uint32_t i=0; i<nb_request; i++)
401	{
402	std::cout << tab_request [i] << std::endl;
403	fifo_request.push(tab_request [i]);
404	}
405	LABEL("Simulation ...");
406
407	while (nb_request_memory_out < nb_request)
408	{
409	cout << "*********************************************" << endl;
410	cout << "Dump STORE_QUEUE_USE : " << endl;
411	cout << " use " << nb_store_slot_use << endl;
412	for (uint32_t i=0; i<_param->_size_store_queue; i++)
413	cout << " [" << i << "] " << store_queue_use [i] << endl;
414	cout << "Dump LOAD_QUEUE_USE : " << endl;
415	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
416	cout << " [" << i << "] " << load_queue_use [i] << endl;
417	cout << "*********************************************" << endl;
418
419
420	// *** MEMORY_IN ***
421
422	// memory_in_val depends of three factors :
423	// 1) request's fifo is not empty ?
424	// 2) the slot destination is free ?
425	// 3) The head of request's fifo can be issue : the number of cycle is more than current cycle
426
427	bool can_execute = false;
428
429	if (not fifo_request.empty())
430	{
431	can_execute = sc_simulation_time() >= fifo_request.top()._cycle;
432	if (is_operation_memory_store(fifo_request.top()._operation))
433	can_execute &= (not store_queue_use [fifo_request.top()._store_queue_ptr_write] and (nb_store_slot_use < _param->_size_store_queue-1)) or is_operation_memory_store_head(fifo_request.top()._operation);
434	else
435	can_execute &= not load_queue_use [fifo_request.top()._load_queue_ptr_write];
436	}
437	in_MEMORY_IN_VAL ->write(can_execute);
438
439	if (not fifo_request.empty())
440	{
441	if (_param->_have_port_context_id)
442	in_MEMORY_IN_CONTEXT_ID ->write (fifo_request.top()._context_id );
443	if (_param->_have_port_front_end_id)
444	in_MEMORY_IN_FRONT_END_ID ->write (fifo_request.top()._front_end_id );
445	if (_param->_have_port_ooo_engine_id)
446	in_MEMORY_IN_OOO_ENGINE_ID ->write (fifo_request.top()._ooo_engine_id );
447	if (_param->_have_port_packet_id)
448	in_MEMORY_IN_PACKET_ID ->write (fifo_request.top()._packet_id );
449	in_MEMORY_IN_OPERATION ->write (fifo_request.top()._operation );
450	in_MEMORY_IN_TYPE ->write (fifo_request.top()._type );
451	in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);
452	in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );
453	in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat );
454	in_MEMORY_IN_DATA_RA ->write (fifo_request.top()._data_ra );
455	in_MEMORY_IN_DATA_RB ->write (fifo_request.top()._data_rb );
456	// in_MEMORY_IN_WRITE_RD ->write (fifo_request.top()._write_rd );
457	in_MEMORY_IN_NUM_REG_RD ->write (fifo_request.top()._num_reg_rd );
458	}
459	in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
460
461	// *** DCACHE_REQ ***
462	in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);
463
464	// *** DCACHE_RSP ***
465	bool have_rsp = _cache->have_rsp ();
466	in_DCACHE_RSP_VAL->write(have_rsp);
467
468	if (have_rsp)
469	{
470	in_DCACHE_RSP_CONTEXT_ID->write(_cache->front()._context_id);
471	in_DCACHE_RSP_PACKET_ID ->write(_cache->front()._packet_id );
472	in_DCACHE_RSP_RDATA ->write(_cache->front()._rdata );
473	in_DCACHE_RSP_ERROR ->write(_cache->front()._error );
474	}
475
476	SC_START(0);
477
478	LABEL("MEMORY_IN : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));
479	if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
480	{
481	Tpacket_t packet_id = in_MEMORY_IN_PACKET_ID->read();
482
483	LABEL(" * Accepted MEMORY_IN : " + toString(packet_id));
484	cout << fifo_request.top();
485
486	if (is_operation_memory_store(fifo_request.top()._operation))
487	{
488	if (not is_operation_memory_store_head(fifo_request.top()._operation))
489	{
490	store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;
491	nb_store_slot_use ++;
492	}
493	}
494	else
495	load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;
496
497	fifo_request.pop();
498	}
499
500	LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read()));
501	if (out_MEMORY_OUT_VAL->read() and in_MEMORY_OUT_ACK->read())
502	{
503	Tpacket_t packet_id = out_MEMORY_OUT_PACKET_ID->read();
504
505	LABEL(" * Accepted MEMORY_OUT : " + toString(packet_id));
506
507	if (is_operation_memory_store(tab_request[packet_id]._operation))
508	{
509	store_queue_use [tab_request[packet_id]._store_queue_ptr_write] = false;
510	nb_store_slot_use --;
511	nb_request_memory_out +=2;
512
513	}
514	else
515	{
516	if (not (out_MEMORY_OUT_EXCEPTION->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
517	{
518	nb_request_memory_out ++;
519
520	load_queue_use [tab_request[packet_id]._load_queue_ptr_write] = false;
521	}
522	else
523	{
524	std::cout << "seth - have a load_speculative." << std::endl;
525	tab_request[packet_id]._write_spec_ko = (out_MEMORY_OUT_DATA_RD->read() != tab_request[packet_id]._data_wait);
526	tab_request[packet_id]._previous_load_speculative = 1;
527	}
528	}
529
530	std::cout << "kane - nb_request_memory_out : " << nb_request_memory_out << std::endl;
531
532	// a lot of test
533	TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID ->read(), tab_request[packet_id]._packet_id );
534	TEST(Tcontext_t , out_MEMORY_OUT_CONTEXT_ID ->read(), tab_request[packet_id]._context_id );
535	TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id );
536	TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id);
537
538	if (is_operation_memory_load (tab_request[packet_id]._operation))
539	{
540	TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD ->read(), tab_request[packet_id]._num_reg_rd );
541	}
542
543	Tgeneral_data_t address = tab_request[packet_id]._data_ra + tab_request[packet_id]._immediat;
544
545	bool error_alignment = (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation))));
546	bool berr = (address >= size_memory);
547	Texception_t exception = out_MEMORY_OUT_EXCEPTION->read();
548
549	if (is_operation_memory_store(tab_request[packet_id]._operation))
550	{
551	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), 0);
552
553	// store.
554	// prioritary : miss_speculation > aligmnent > DBERR
555
556	bool test_result_ko = false;
557
558	if (tab_request[packet_id]._write_spec_ko)
559	{
560	TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION);
561	}
562	else
563	if (error_alignment)
564	{
565	TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT);
566	test_result_ko = true;
567	}
568	else
569	if (berr)
570	{
571	// TODO NOT SUPPORTED
572	// TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR);
573
574	//test_result_ko = true;
575	}
576	else
577	{
578	TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE);
579	}
580	// In all case : test data
581	if (test_result_ko)
582	{
583	TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), address);
584	}
585	}
586	else
587	{
588	// load
589	// prioritary : miss_speculation > aligmnent > DBERR
590
591	bool is_load = is_operation_memory_load(tab_request[packet_id]._operation);
592
593	if (not (out_MEMORY_OUT_EXCEPTION->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
594	{
595	bool test_result_ko = false;
596
597	if (tab_request[packet_id]._write_spec_ko)
598	{
599	// IS A LOAD :D
600	TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION);
601	TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD->read(), 1);
602	}
603	else
604	if (error_alignment)
605	{
606	TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT);
607	TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD->read(), is_load);
608	test_result_ko = true;
609	}
610	else
611	if (berr)
612	{
613	TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR);
614	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD->read(), is_load);
615	test_result_ko = true;
616	}
617	else
618	{
619	TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE);
620	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD->read(), is_load and not tab_request[packet_id]._previous_load_speculative);
621	}
622	// In all case : test data
623	if (test_result_ko)
624	{
625	TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), address);
626	}
627	else
628	{
629	TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), tab_request[packet_id]._data_wait);
630	}
631	}
632	else
633	{
634	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), 1);
635	}
636	}
637	}
638
639	LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read()));
640	if (out_DCACHE_REQ_VAL->read() and in_DCACHE_REQ_ACK->read())
641	{
642	Tcontext_t context_id;
643	Tpacket_t packet_id ;
644	Tdcache_address_t address = out_DCACHE_REQ_ADDRESS->read();
645	Tdcache_data_t rdata;
646	Tdcache_error_t error = 0;
647	if (_param->_have_port_dcache_context_id)
648	context_id = out_DCACHE_REQ_CONTEXT_ID->read();
649	else
650	context_id = 0;
651
652	packet_id = (out_DCACHE_REQ_PACKET_ID ->read())>>1;
653
654	LABEL(" * Accepted DCACHE_REQ : " + toString(packet_id));
655
656	if (address >= size_memory)
657	{
658	// Bus error
659	error = 1;
660	rdata = address; // convention : cache return the address fautive !
661	}
662	else
663	{
664	rdata = _memory->access (context_id, address, out_DCACHE_REQ_TYPE->read(), out_DCACHE_REQ_WDATA->read());
665	LABEL(" * rdata : " + toString(rdata));
666	}
667
668	// test type : send or not a respons !
669	if ((out_DCACHE_REQ_TYPE->read() == DCACHE_SYNCHRONIZATION) or
670	(out_DCACHE_REQ_TYPE->read() == DCACHE_LOAD) or
671	((error == 1) and ((out_DCACHE_REQ_TYPE->read() == DCACHE_STORE_8 ) or
672	(out_DCACHE_REQ_TYPE->read() == DCACHE_STORE_16) or
673	(out_DCACHE_REQ_TYPE->read() == DCACHE_STORE_32) or
674	(out_DCACHE_REQ_TYPE->read() == DCACHE_STORE_64) )))
675	{
676	LABEL(" * have_dcache_rsp");
677
678	_cache->push (context_id,
679	out_DCACHE_REQ_PACKET_ID ->read(),
680	rdata,
681	error);
682	}
683	}
684
685	LABEL("DCACHE_RSP : "+toString(in_DCACHE_RSP_VAL->read())+" - "+toString(out_DCACHE_RSP_ACK ->read()));
686	if (in_DCACHE_RSP_VAL->read() and out_DCACHE_RSP_ACK->read())
687	{
688	_cache->pop();
689	}
690
691	_cache->end_cycle();
692
693	SC_START(1);
694	}
695	}
696	catch (morpheo::ErrorMorpheo & error)
697	{
698	_memory->trace();
699	throw (error);
700	}
701
702	_memory->trace();
703
704
705	/********************************************************
706	* Simulation - End
707	********************************************************/
708
709	TEST_OK ("End of Simulation");
710	delete _time;
711	cout << "<" << name << "> ............ Stop Simulation" << endl;
712
713	delete in_CLOCK;
714	delete in_NRESET;
715
716	delete in_MEMORY_IN_VAL ;
717	delete out_MEMORY_IN_ACK ;
718	delete in_MEMORY_IN_CONTEXT_ID ;
719	delete in_MEMORY_IN_FRONT_END_ID ;
720	delete in_MEMORY_IN_OOO_ENGINE_ID ;
721	delete in_MEMORY_IN_PACKET_ID ;
722	delete in_MEMORY_IN_OPERATION ;
723	delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
724	delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
725	//delete in_MEMORY_IN_HAS_IMMEDIAT;
726	delete in_MEMORY_IN_IMMEDIAT ;
727	delete in_MEMORY_IN_DATA_RA ;
728	delete in_MEMORY_IN_DATA_RB ;
729	//delete in_MEMORY_IN_DATA_RC ;
730	// delete in_MEMORY_IN_WRITE_RD ;
731	delete in_MEMORY_IN_NUM_REG_RD ;
732	//delete in_MEMORY_IN_WRITE_RE ;
733	//delete in_MEMORY_IN_NUM_REG_RE ;
734
735	delete out_MEMORY_OUT_VAL ;
736	delete in_MEMORY_OUT_ACK ;
737	delete out_MEMORY_OUT_CONTEXT_ID;
738	delete out_MEMORY_OUT_FRONT_END_ID;
739	delete out_MEMORY_OUT_OOO_ENGINE_ID;
740	delete out_MEMORY_OUT_PACKET_ID ;
741	delete out_MEMORY_OUT_WRITE_RD ;
742	delete out_MEMORY_OUT_NUM_REG_RD;
743	delete out_MEMORY_OUT_DATA_RD ;
744	//delete out_MEMORY_OUT_WRITE_RE ;
745	//delete out_MEMORY_OUT_NUM_REG_RE;
746	//delete out_MEMORY_OUT_DATA_RE ;
747	delete out_MEMORY_OUT_EXCEPTION ;
748
749	delete out_DCACHE_REQ_VAL ;
750	delete in_DCACHE_REQ_ACK ;
751	delete out_DCACHE_REQ_CONTEXT_ID;
752	delete out_DCACHE_REQ_PACKET_ID ;
753	delete out_DCACHE_REQ_ADDRESS ;
754	delete out_DCACHE_REQ_TYPE ;
755	delete out_DCACHE_REQ_WDATA ;
756
757	delete in_DCACHE_RSP_VAL ;
758	delete out_DCACHE_RSP_ACK ;
759	delete in_DCACHE_RSP_CONTEXT_ID;
760	delete in_DCACHE_RSP_PACKET_ID ;
761	delete in_DCACHE_RSP_RDATA ;
762	delete in_DCACHE_RSP_ERROR ;
763
764	if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
765	{
766	delete [] out_BYPASS_MEMORY_VAL ;
767	delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
768	delete [] out_BYPASS_MEMORY_NUM_REG ;
769	delete [] out_BYPASS_MEMORY_DATA ;
770	}
771	#endif
772
773	delete _Load_store_unit;
774	delete _memory;
775	delete _cache;
776	#ifdef STATISTICS
777	delete _parameters_statistics;
778	#endif
779	delete _param;
780	}

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