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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp @ 77

Last change on this file since 77 was 77, checked in by rosiere, 16 years ago
Add two component : network between read unit and execute unit network between execute unit and write unit remove parameters "nb_operation" and "nb_type" in write_queue add the special case : load_speculative
File size: 39.6 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include <queue>
10	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
11
12	#define CYCLE_MAX 1024
13
14	#define LABEL(str) \
15	{ \
16	cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \
17	} while(0)
18
19	#define SC_START(cycle_offset) \
20	do \
21	{ \
22	/cout << "SC_START (begin)" << endl;/ \
23	\
24	uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
25	if (cycle_offset != 0) \
26	{ \
27	cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \
28	} \
29	\
30	if (cycle_current > CYCLE_MAX) \
31	{ \
32	TEST_KO("Maximal cycles Reached"); \
33	} \
34	sc_start(cycle_offset); \
35	/cout << "SC_START (end )" << endl;/ \
36	} while(0)
37
38
39	//===================================================================={test}
40	void test2 (void)
41	{
42	std::string name = "Test_Load_store_queue_manual";
43
44	cout << "<" << name << "> : Simulation SystemC" << endl;
45
46
47	morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters
48	(
49	4, //_size_store_queue
50	4, //_size_load_queue
51	2, //_size_speculative_access_queue
52	2, //_nb_port_check
53	SPECULATIVE_LOAD_COMMIT, //_speculative_load
54	1, //_nb_context
55	1, //_nb_front_end
56	2, //_nb_ooo_engine
57	128,//_nb_packet
58	32, //_size_general_data
59	64 //_nb_general_register
60	);
61
62	#ifdef STATISTICS
63	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
64	#endif
65
66	Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(),
67	#ifdef STATISTICS
68	_parameters_statistics,
69	#endif
70	_param);
71
72	#ifdef SYSTEMC
73	/*********************************************************************
74	* Déclarations des signaux
75	*********************************************************************/
76	string rename = "";
77
78	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
79	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
80
81	sc_signal<Tcontrol_t > * in_MEMORY_IN_VAL = new sc_signal<Tcontrol_t > (rename.c_str());
82	sc_signal<Tcontrol_t > * out_MEMORY_IN_ACK = new sc_signal<Tcontrol_t > (rename.c_str());
83	sc_signal<Tcontext_t > * in_MEMORY_IN_CONTEXT_ID = new sc_signal<Tcontext_t > (rename.c_str());
84	sc_signal<Tcontext_t > * in_MEMORY_IN_FRONT_END_ID = new sc_signal<Tcontext_t > (rename.c_str());
85	sc_signal<Tcontext_t > * in_MEMORY_IN_OOO_ENGINE_ID = new sc_signal<Tcontext_t > (rename.c_str());
86	sc_signal<Tpacket_t > * in_MEMORY_IN_PACKET_ID = new sc_signal<Tpacket_t > (rename.c_str());
87	sc_signal<Toperation_t > * in_MEMORY_IN_OPERATION = new sc_signal<Toperation_t > (rename.c_str());
88	sc_signal<Ttype_t > * in_MEMORY_IN_TYPE = new sc_signal<Ttype_t > (rename.c_str());
89	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
90	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
91	//sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str());
92	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_IMMEDIAT = new sc_signal<Tgeneral_data_t > (rename.c_str());
93	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RA = new sc_signal<Tgeneral_data_t > (rename.c_str());
94	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RB = new sc_signal<Tgeneral_data_t > (rename.c_str());
95	//sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str());
96	// sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str());
97	sc_signal<Tgeneral_address_t> * in_MEMORY_IN_NUM_REG_RD = new sc_signal<Tgeneral_address_t> (rename.c_str());
98	//sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str());
99	//sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str());
100
101	sc_signal<Tcontrol_t > * out_MEMORY_OUT_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
102	sc_signal<Tcontrol_t > * in_MEMORY_OUT_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
103	sc_signal<Tcontext_t > * out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
104	sc_signal<Tcontext_t > * out_MEMORY_OUT_FRONT_END_ID = new sc_signal<Tcontext_t >(rename.c_str());
105	sc_signal<Tcontext_t > * out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >(rename.c_str());
106	sc_signal<Tpacket_t > * out_MEMORY_OUT_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
107	sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RD = new sc_signal<Tcontrol_t >(rename.c_str());
108	sc_signal<Tgeneral_address_t> * out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str());
109	sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_DATA_RD = new sc_signal<Tgeneral_data_t >(rename.c_str());
110	//sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str());
111	//sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str());
112	//sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str());
113	sc_signal<Texception_t > * out_MEMORY_OUT_EXCEPTION = new sc_signal<Texception_t >(rename.c_str());
114
115	sc_signal<Tcontrol_t > * out_DCACHE_REQ_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
116	sc_signal<Tcontrol_t > * in_DCACHE_REQ_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
117	sc_signal<Tcontext_t > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
118	sc_signal<Tpacket_t > * out_DCACHE_REQ_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
119	sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS = new sc_signal<Tdcache_address_t >(rename.c_str());
120	sc_signal<Tdcache_type_t > * out_DCACHE_REQ_TYPE = new sc_signal<Tdcache_type_t >(rename.c_str());
121	sc_signal<Tdcache_data_t > * out_DCACHE_REQ_WDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
122
123	sc_signal<Tcontrol_t > * in_DCACHE_RSP_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
124	sc_signal<Tcontrol_t > * out_DCACHE_RSP_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
125	sc_signal<Tcontext_t > * in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
126	sc_signal<Tpacket_t > * in_DCACHE_RSP_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
127	sc_signal<Tdcache_data_t > * in_DCACHE_RSP_RDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
128	sc_signal<Tdcache_error_t > * in_DCACHE_RSP_ERROR = new sc_signal<Tdcache_error_t >(rename.c_str());
129
130	sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_size_load_queue];
131	sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_size_load_queue];
132	sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_size_load_queue];
133	sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_size_load_queue];
134
135	for (uint32_t i=0; i<_param->_size_load_queue; i++)
136	{
137	out_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t >(rename.c_str());
138	out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t >(rename.c_str());
139	out_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t>(rename.c_str());
140	out_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t >(rename.c_str());
141	}
142
143	/********************************************************
144	* Instanciation
145	********************************************************/
146
147	cout << "<" << name << "> Instanciation of _Load_store_unit" << endl;
148
149	((_Load_store_unit->in_CLOCK)) ((in_CLOCK));
150	((_Load_store_unit->in_NRESET)) ((in_NRESET));
151
152	((_Load_store_unit-> in_MEMORY_IN_VAL ))(( in_MEMORY_IN_VAL ));
153	((_Load_store_unit->out_MEMORY_IN_ACK ))((out_MEMORY_IN_ACK ));
154	if (_param->_have_port_context_id)
155	((_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID ))(( in_MEMORY_IN_CONTEXT_ID ));
156	if (_param->_have_port_front_end_id)
157	((_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID ))(( in_MEMORY_IN_FRONT_END_ID ));
158	if (_param->_have_port_ooo_engine_id)
159	((_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID ))(( in_MEMORY_IN_OOO_ENGINE_ID ));
160	if (_param->_have_port_packet_id)
161	((_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(( in_MEMORY_IN_PACKET_ID ));
162	((_Load_store_unit-> in_MEMORY_IN_OPERATION ))(( in_MEMORY_IN_OPERATION ));
163	((_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
164	((_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
165	//((_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(( in_MEMORY_IN_HAS_IMMEDIAT ));
166	((_Load_store_unit-> in_MEMORY_IN_IMMEDIAT ))(( in_MEMORY_IN_IMMEDIAT ));
167	((_Load_store_unit-> in_MEMORY_IN_DATA_RA ))(( in_MEMORY_IN_DATA_RA ));
168	((_Load_store_unit-> in_MEMORY_IN_DATA_RB ))(( in_MEMORY_IN_DATA_RB ));
169	//((_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(( in_MEMORY_IN_DATA_RC ));
170	// ((_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(( in_MEMORY_IN_WRITE_RD ));
171	((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD ))(( in_MEMORY_IN_NUM_REG_RD ));
172	//((_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(( in_MEMORY_IN_WRITE_RE ));
173	//((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(( in_MEMORY_IN_NUM_REG_RE ));
174
175	((_Load_store_unit->out_MEMORY_OUT_VAL ))((out_MEMORY_OUT_VAL ));
176	((_Load_store_unit-> in_MEMORY_OUT_ACK ))(( in_MEMORY_OUT_ACK ));
177	if (_param->_have_port_context_id)
178	((_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))((out_MEMORY_OUT_CONTEXT_ID ));
179	if (_param->_have_port_front_end_id)
180	((_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID ))((out_MEMORY_OUT_FRONT_END_ID ));
181	if (_param->_have_port_ooo_engine_id)
182	((_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))((out_MEMORY_OUT_OOO_ENGINE_ID ));
183	if (_param->_have_port_packet_id)
184	((_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))((out_MEMORY_OUT_PACKET_ID ));
185	((_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))((out_MEMORY_OUT_WRITE_RD ));
186	((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))((out_MEMORY_OUT_NUM_REG_RD ));
187	((_Load_store_unit->out_MEMORY_OUT_DATA_RD ))((out_MEMORY_OUT_DATA_RD ));
188	//((_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))((out_MEMORY_OUT_WRITE_RE ));
189	//((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))((out_MEMORY_OUT_NUM_REG_RE ));
190	//((_Load_store_unit->out_MEMORY_OUT_DATA_RE ))((out_MEMORY_OUT_DATA_RE ));
191	((_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))((out_MEMORY_OUT_EXCEPTION ));
192
193	((_Load_store_unit->out_DCACHE_REQ_VAL ))((out_DCACHE_REQ_VAL ));
194	((_Load_store_unit-> in_DCACHE_REQ_ACK ))(( in_DCACHE_REQ_ACK ));
195	if (_param->_have_port_dcache_context_id)
196	((_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))((out_DCACHE_REQ_CONTEXT_ID));
197	((_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))((out_DCACHE_REQ_PACKET_ID ));
198	((_Load_store_unit->out_DCACHE_REQ_ADDRESS ))((out_DCACHE_REQ_ADDRESS ));
199	((_Load_store_unit->out_DCACHE_REQ_TYPE ))((out_DCACHE_REQ_TYPE ));
200	((_Load_store_unit->out_DCACHE_REQ_WDATA ))((out_DCACHE_REQ_WDATA ));
201
202	((_Load_store_unit-> in_DCACHE_RSP_VAL ))(( in_DCACHE_RSP_VAL ));
203	((_Load_store_unit->out_DCACHE_RSP_ACK ))((out_DCACHE_RSP_ACK ));
204	if (_param->_have_port_dcache_context_id)
205	((_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(( in_DCACHE_RSP_CONTEXT_ID));
206	((_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(( in_DCACHE_RSP_PACKET_ID ));
207	((_Load_store_unit-> in_DCACHE_RSP_RDATA ))(( in_DCACHE_RSP_RDATA ));
208	((_Load_store_unit-> in_DCACHE_RSP_ERROR ))(( in_DCACHE_RSP_ERROR ));
209
210	if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
211	{
212	for (uint32_t i=0; i<_param->_size_load_queue; i++)
213	{
214	((_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))((out_BYPASS_MEMORY_VAL [i]));
215	if (_param->_have_port_ooo_engine_id)
216	((_Load_store_unit->out_BYPASS_MEMORY_OOO_ENGINE_ID [i]))((out_BYPASS_MEMORY_OOO_ENGINE_ID [i]));
217	((_Load_store_unit->out_BYPASS_MEMORY_NUM_REG [i]))((out_BYPASS_MEMORY_NUM_REG [i]));
218	((_Load_store_unit->out_BYPASS_MEMORY_DATA [i]))((out_BYPASS_MEMORY_DATA [i]));
219	}
220	}
221	cout << "<" << name << "> Start Simulation ............" << endl;
222	Time * _time = new Time();
223
224	/********************************************************
225	* Simulation - Begin
226	********************************************************/
227
228	// Initialisation
229
230	const uint32_t seed = 0;
231	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
232
233	srand(seed);
234
235	const int32_t percent_transaction_memory_out = 100;
236	const int32_t percent_transaction_dcache = 100;
237	const uint32_t miss_rate = 0;
238	const uint32_t miss_penality = 0;
239
240	uint32_t nb_request_memory_out=0;
241
242	MemoryRequest_t tab_request [_param->_nb_packet];
243	priority_queue<MemoryRequest_t> fifo_request;
244
245	const uint32_t size_memory = 0x100;
246	// emulation of memory
247	Memory_t * _memory = new Memory_t (1<<_param->_size_dcache_context_id, size_memory, _param->_size_general_data);
248	Cache_t * _cache = new Cache_t (miss_rate, miss_penality);
249
250	SC_START(0);
251
252	LABEL("Initialisation");
253
254	in_MEMORY_IN_VAL ->write(0);
255	in_MEMORY_OUT_ACK->write(0);
256	in_DCACHE_REQ_ACK->write(0);
257	in_DCACHE_RSP_VAL->write(0);
258
259	in_NRESET ->write(0);
260	SC_START(5);
261	in_NRESET ->write(5);
262
263	LABEL("Loop of Test");
264
265	try
266	{
267	LABEL("Structure's initialisation");
268
269	bool store_queue_use [_param->_size_store_queue];
270	uint32_t nb_store_slot_use = 0;
271	bool load_queue_use [_param->_size_load_queue ];
272
273	for (uint32_t i=0; i<_param->_size_store_queue; i++)
274	store_queue_use [i] = false;
275	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
276	load_queue_use [i] = false;
277
278
279	//--------------------------------------------------------------------------------------------------------------
280	// c c f o p o t s l i d d w n w
281	// y o r o a p y t o m a a r u r
282	// c n o o c e p o a m t t i m i
283	// l t n _ k r e r d e a a t _ t
284	// e e t e e a e _ d _ _ e r e
285	// x _ n t t _ p i r r _ _ _
286	// t e g _ i p t a a b r g s
287	// _ n i i o t r t d _ p
288	// i d n d n r _ r e
289	// d _ e _ w d c
290	// i _ w r _
291	// d i r i k
292	// d i t o
293	// t e
294	// e
295	//
296	tab_request[ 0].modif( 5,0,0,0, 0,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x10 ,0xdead1234,0,0,0);
297
298	tab_request[ 1].modif(10,0,0,0, 0,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
299
300	// READ 32b
301	tab_request[ 2].modif(12,0,0,0, 2,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,1,0,0xdead1234);
302	tab_request[ 3].modif(13,0,0,0, 3,OPERATION_MEMORY_LOAD_32_S ,TYPE_MEMORY,1,1,0x10 ,0x0 ,0x0 ,1,2,0,0xdead1234);
303
304	// READ 16b
305	tab_request[ 4].modif(14,0,0,0, 4,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,1,2,0x10 ,0x0 ,0x0 ,1,3,0,0x00001234);
306	tab_request[ 5].modif(15,0,0,0, 5,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,1,3,0x12 ,0x0 ,0x0 ,1,4,0,0x0000dead);
307	tab_request[ 6].modif(16,0,0,0, 6,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,5,0,0x00001234);
308	tab_request[ 7].modif(17,0,0,0, 7,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,1,1,0x12 ,0x0 ,0x0 ,1,6,0,0xffffdead);
309
310	// READ 8b
311	tab_request[ 8].modif(18,0,0,0, 8,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,7,0,0x00000034);
312	tab_request[ 9].modif(19,0,0,0, 9,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,1,0x11 ,0x0 ,0x0 ,1,8,0,0x00000012);
313	tab_request[10].modif(20,0,0,0,10,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,2,0x12 ,0x0 ,0x0 ,1,9,0,0x000000ad);
314	tab_request[11].modif(21,0,0,0,11,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,3,0x13 ,0x0 ,0x0 ,1,1,0,0x000000de);
315	tab_request[12].modif(22,0,0,0,12,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,2,0,0x00000034);
316	tab_request[13].modif(23,0,0,0,13,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,1,0x11 ,0x0 ,0x0 ,1,3,0,0x00000012);
317	tab_request[14].modif(24,0,0,0,14,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,2,0x12 ,0x0 ,0x0 ,1,4,0,0xffffffad);
318	tab_request[15].modif(25,0,0,0,15,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,3,0x13 ,0x0 ,0x0 ,1,5,0,0xffffffde);
319
320	// STORE 16b
321	tab_request[16].modif(30,0,0,0,16,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,1,0,0x20 ,0x0 ,0xffffabcd,0,0,0);
322	tab_request[17].modif(31,0,0,0,17,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,2,0,0x22 ,0x0 ,0xffffdcba,0,0,0);
323	tab_request[18].modif(35,0,0,0,18,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
324	tab_request[19].modif(36,0,0,0,19,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
325	tab_request[20].modif(40,0,0,0,20,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,0,0x20 ,0x0 ,0x0 ,1,0,0,0xdcbaabcd);
326
327	// STORE 8b and head / valid out order
328	tab_request[21].modif(50,0,0,0,21,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,3,0,0x1 ,0x4 ,0xffffff56,0,0,0);
329	tab_request[22].modif(55,0,0,0,22,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x1 ,0x0 ,0x0 ,0,0,0);
330	tab_request[23].modif(48,0,0,0,23,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,0,0,0x0 ,0x4 ,0xffffff78,0,0,0);
331	tab_request[24].modif(43,0,0,0,24,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
332	tab_request[25].modif(47,0,0,0,25,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,1,0,0x3 ,0x4 ,0xffffff12,0,0,0);
333	tab_request[26].modif(49,0,0,0,26,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
334	tab_request[27].modif(57,0,0,0,27,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,2,0,0x2 ,0x4 ,0xffffff34,0,0,0);
335	tab_request[28].modif(44,0,0,0,28,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
336	tab_request[29].modif(70,0,0,0,29,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,1,0x2 ,0x2 ,0x0 ,1,0,0,0x12345678);
337
338	// CHECK - with a store not present, store format is >=
339	tab_request[30].modif(180,0,0,0,30,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,3,0,0x0 ,0x30 ,0x21071981,0,0,0);
340	tab_request[31].modif(179,0,0,0,31,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0);
341	tab_request[32].modif(173,0,0,0,32,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x30 ,0x0 ,1,0,0,0x21071981);
342	tab_request[33].modif(174,0,0,0,33,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,0,3,0x0 ,0x30 ,0x0 ,1,0,0,0x00001981);
343	tab_request[34].modif(175,0,0,0,34,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,0,0,0x0 ,0x32 ,0x0 ,1,0,0,0x00002107);
344	tab_request[35].modif(176,0,0,0,35,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,0,1,0x0 ,0x31 ,0x0 ,1,0,0,0x00000019);
345
346	// CHECK - with a store not present, multiple store and format is different
347	tab_request[36].modif(200,0,0,0,36,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x40 ,0xffffffff,0,0,0);
348	tab_request[37].modif(200,0,0,0,37,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
349	tab_request[38].modif(220,0,0,0,38,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,1,0,0x0 ,0x42 ,0xbaba ,0,0,0);
350	tab_request[39].modif(245,0,0,0,39,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
351	tab_request[40].modif(224,0,0,0,40,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,2,0,0x0 ,0x42 ,0xbe ,0,0,0);
352	tab_request[41].modif(240,0,0,0,41,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
353	tab_request[42].modif(228,0,0,0,42,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,3,0,0x0 ,0x40 ,0xf00d ,0,0,0);
354	tab_request[43].modif(235,0,0,0,43,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0);
355	tab_request[44].modif(210,0,0,0,44,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x40 ,0x0 ,1,0,0,0xbabef00d);
356	tab_request[45].modif(211,0,0,0,45,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,2,3,0x0 ,0x40 ,0x0 ,1,0,0,0xbabaffff);
357	tab_request[46].modif(212,0,0,0,46,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,0,0x0 ,0x40 ,0x0 ,1,0,0,0xbabeffff);
358	tab_request[47].modif(213,0,0,0,47,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,3,1,0x0 ,0x42 ,0x0 ,1,0,0,0xffffffbe);
359
360
361	// CHECK - with different ooo_engine_id
362	tab_request[48].modif(300,0,0,0,48,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x0 ,0xdad1900d,0,0,0);
363	tab_request[49].modif(300,0,0,0,49,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
364	tab_request[50].modif(300,0,0,1,50,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x55508570,0,0,0);
365	tab_request[51].modif(300,0,0,1,51,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
366
367
368	tab_request[52].modif(320,0,0,0,52,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,2,2,0x0 ,0x2 ,0x0 ,1,0,0,0xffffdad1);
369	tab_request[53].modif(321,0,0,1,53,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,2,3,0x0 ,0x0 ,0x0 ,1,0,0,0xffff8570);
370
371
372	// with a little exception
373	tab_request[54].modif(330,0,0,1,54,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,2,0,0x0 ,0x0 ,0xffff6996,0,0,1);
374	tab_request[55].modif(340,0,0,1,55,OPERATION_MEMORY_STORE_HEAD_KO,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
375	tab_request[56].modif(322,0,0,1,56,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,3,0,0x0 ,0x1 ,0x0 ,1,0,0,0x00000069); // they are a bypass (because, the cpu go in exception handler ... load is not use)
376	tab_request[57].modif(350,0,0,1,57,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,1,0x0 ,0x0 ,0x0 ,1,0,0,0x55508570); // the memory have not change
377
378
379	// multiple event
380	// * store : miss_spec and aligment, priority : miss_spec > aligment
381	// * load : miss_spec and aligment, priority : miss_spec > aligment
382	tab_request[58].modif(410,0,0,0,58,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,3,0,0x0 ,0x1 ,0x0 ,0,0,1);
383	tab_request[59].modif(415,0,0,0,59,OPERATION_MEMORY_STORE_HEAD_KO,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0);
384
385	tab_request[60].modif(430,0,0,0,60,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x0 ,0x0 ,1,0,0,0xdad1900d);
386	tab_request[61].modif(400,0,0,0,61,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,3,0x0 ,0x3 ,0x0 ,1,0,0); // miss_spec and alignment
387	tab_request[62].modif(450,0,0,0,62,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,0,0x0 ,size_memory ,0x0 ,1,0,0); // bus error and alignement
388	tab_request[63].modif(460,0,0,0,63,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,1,0x0 ,size_memory+1,0x0 ,1,0,0); // bus error and alignement
389
390
391
392	tab_request[64].modif(500,0,0,0,64,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,size_memory ,0x0 ,0,0,0); // bus error
393	tab_request[65].modif(505,0,0,0,65,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
394	tab_request[66].modif(550,0,0,0,65,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,1,0,0,0x55508570); // just to wait the dcache_rsp
395
396	const uint32_t nb_request = 64;//_param->_nb_packet;
397
398	for (uint32_t i=0; i<nb_request; i++)
399	{
400	std::cout << tab_request [i] << std::endl;
401	fifo_request.push(tab_request [i]);
402	}
403	LABEL("Simulation ...");
404
405	while (nb_request_memory_out < nb_request)
406	{
407	cout << "*********************************************" << endl;
408	cout << "Dump STORE_QUEUE_USE : " << endl;
409	cout << " use " << nb_store_slot_use << endl;
410	for (uint32_t i=0; i<_param->_size_store_queue; i++)
411	cout << " [" << i << "] " << store_queue_use [i] << endl;
412	cout << "Dump LOAD_QUEUE_USE : " << endl;
413	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
414	cout << " [" << i << "] " << load_queue_use [i] << endl;
415	cout << "*********************************************" << endl;
416
417
418	// *** MEMORY_IN ***
419
420	// memory_in_val depends of three factors :
421	// 1) request's fifo is not empty ?
422	// 2) the slot destination is free ?
423	// 3) The head of request's fifo can be issue : the number of cycle is more than current cycle
424
425	bool can_execute = false;
426
427	if (not fifo_request.empty())
428	{
429	can_execute = sc_simulation_time() >= fifo_request.top()._cycle;
430	if (is_operation_memory_store(fifo_request.top()._operation))
431	can_execute &= (not store_queue_use [fifo_request.top()._store_queue_ptr_write] and (nb_store_slot_use < _param->_size_store_queue-1)) or is_operation_memory_store_head(fifo_request.top()._operation);
432	else
433	can_execute &= not load_queue_use [fifo_request.top()._load_queue_ptr_write];
434	}
435	in_MEMORY_IN_VAL ->write(can_execute);
436
437	if (not fifo_request.empty())
438	{
439	if (_param->_have_port_context_id)
440	in_MEMORY_IN_CONTEXT_ID ->write (fifo_request.top()._context_id );
441	if (_param->_have_port_front_end_id)
442	in_MEMORY_IN_FRONT_END_ID ->write (fifo_request.top()._front_end_id );
443	if (_param->_have_port_ooo_engine_id)
444	in_MEMORY_IN_OOO_ENGINE_ID ->write (fifo_request.top()._ooo_engine_id );
445	if (_param->_have_port_packet_id)
446	in_MEMORY_IN_PACKET_ID ->write (fifo_request.top()._packet_id );
447	in_MEMORY_IN_OPERATION ->write (fifo_request.top()._operation );
448	in_MEMORY_IN_TYPE ->write (fifo_request.top()._type );
449	in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);
450	in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );
451	in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat );
452	in_MEMORY_IN_DATA_RA ->write (fifo_request.top()._data_ra );
453	in_MEMORY_IN_DATA_RB ->write (fifo_request.top()._data_rb );
454	// in_MEMORY_IN_WRITE_RD ->write (fifo_request.top()._write_rd );
455	in_MEMORY_IN_NUM_REG_RD ->write (fifo_request.top()._num_reg_rd );
456	}
457	in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
458
459	// *** DCACHE_REQ ***
460	in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);
461
462	// *** DCACHE_RSP ***
463	bool have_rsp = _cache->have_rsp ();
464	in_DCACHE_RSP_VAL->write(have_rsp);
465
466	if (have_rsp)
467	{
468	in_DCACHE_RSP_CONTEXT_ID->write(_cache->front()._context_id);
469	in_DCACHE_RSP_PACKET_ID ->write(_cache->front()._packet_id );
470	in_DCACHE_RSP_RDATA ->write(_cache->front()._rdata );
471	in_DCACHE_RSP_ERROR ->write(_cache->front()._error );
472	}
473
474	SC_START(0);
475
476	LABEL("MEMORY_IN : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));
477	if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
478	{
479	Tpacket_t packet_id = in_MEMORY_IN_PACKET_ID->read();
480
481	LABEL(" * Accepted MEMORY_IN : " + toString(packet_id));
482	cout << fifo_request.top();
483
484	if (is_operation_memory_store(fifo_request.top()._operation))
485	{
486	if (not is_operation_memory_store_head(fifo_request.top()._operation))
487	{
488	store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;
489	nb_store_slot_use ++;
490	}
491	}
492	else
493	load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;
494
495	fifo_request.pop();
496	}
497
498	LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read()));
499	if (out_MEMORY_OUT_VAL->read() and in_MEMORY_OUT_ACK->read())
500	{
501	Tpacket_t packet_id = out_MEMORY_OUT_PACKET_ID->read();
502
503	LABEL(" * Accepted MEMORY_OUT : " + toString(packet_id));
504
505	if (is_operation_memory_store(tab_request[packet_id]._operation))
506	{
507	store_queue_use [tab_request[packet_id]._store_queue_ptr_write] = false;
508	nb_store_slot_use --;
509	nb_request_memory_out +=2;
510
511	}
512	else
513	{
514	if (not (out_MEMORY_OUT_EXCEPTION->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
515	{
516	nb_request_memory_out ++;
517
518	load_queue_use [tab_request[packet_id]._load_queue_ptr_write] = false;
519	}
520	else
521	{
522	std::cout << "seth - have a load_speculative." << std::endl;
523	tab_request[packet_id]._write_spec_ko = (out_MEMORY_OUT_DATA_RD->read() != tab_request[packet_id]._data_wait);
524	tab_request[packet_id]._previous_load_speculative = 1;
525	}
526	}
527
528	std::cout << "kane - nb_request_memory_out : " << nb_request_memory_out << std::endl;
529
530	// a lot of test
531	TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID ->read(), tab_request[packet_id]._packet_id );
532	TEST(Tcontext_t , out_MEMORY_OUT_CONTEXT_ID ->read(), tab_request[packet_id]._context_id );
533	TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id );
534	TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id);
535
536	if (is_operation_memory_load (tab_request[packet_id]._operation))
537	{
538	TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD ->read(), tab_request[packet_id]._num_reg_rd );
539	}
540
541	Tgeneral_data_t address = tab_request[packet_id]._data_ra + tab_request[packet_id]._immediat;
542
543	bool error_alignment = (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation))));
544	bool berr = (address >= size_memory);
545	Texception_t exception = out_MEMORY_OUT_EXCEPTION->read();
546
547	if (is_operation_memory_store(tab_request[packet_id]._operation))
548	{
549	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), 0);
550
551	// store.
552	// prioritary : miss_speculation > aligmnent > DBERR
553
554	bool test_result_ko = false;
555
556	if (tab_request[packet_id]._write_spec_ko)
557	{
558	TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION);
559	}
560	else
561	if (error_alignment)
562	{
563	TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT);
564	test_result_ko = true;
565	}
566	else
567	if (berr)
568	{
569	// TODO NOT SUPPORTED
570	// TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR);
571
572	//test_result_ko = true;
573	}
574	else
575	{
576	TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE);
577	}
578	// In all case : test data
579	if (test_result_ko)
580	{
581	TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), address);
582	}
583	}
584	else
585	{
586	// load
587	// prioritary : miss_speculation > aligmnent > DBERR
588
589	bool is_load = is_operation_memory_load(tab_request[packet_id]._operation);
590
591	if (not (out_MEMORY_OUT_EXCEPTION->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
592	{
593	bool test_result_ko = false;
594
595	if (tab_request[packet_id]._write_spec_ko)
596	{
597	// IS A LOAD :D
598	TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION);
599	TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD->read(), 1);
600	}
601	else
602	if (error_alignment)
603	{
604	TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT);
605	TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD->read(), is_load);
606	test_result_ko = true;
607	}
608	else
609	if (berr)
610	{
611	TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR);
612	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD->read(), is_load);
613	test_result_ko = true;
614	}
615	else
616	{
617	TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE);
618	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD->read(), is_load and not tab_request[packet_id]._previous_load_speculative);
619	}
620	// In all case : test data
621	if (test_result_ko)
622	{
623	TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), address);
624	}
625	else
626	{
627	TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), tab_request[packet_id]._data_wait);
628	}
629	}
630	else
631	{
632	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), 1);
633	}
634	}
635	}
636
637	LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read()));
638	if (out_DCACHE_REQ_VAL->read() and in_DCACHE_REQ_ACK->read())
639	{
640	Tcontext_t context_id;
641	Tpacket_t packet_id ;
642	Tdcache_address_t address = out_DCACHE_REQ_ADDRESS->read();
643	Tdcache_data_t rdata;
644	Tdcache_error_t error = 0;
645	if (_param->_have_port_dcache_context_id)
646	context_id = out_DCACHE_REQ_CONTEXT_ID->read();
647	else
648	context_id = 0;
649
650	packet_id = (out_DCACHE_REQ_PACKET_ID ->read())>>1;
651
652	LABEL(" * Accepted DCACHE_REQ : " + toString(packet_id));
653
654	if (address >= size_memory)
655	{
656	// Bus error
657	error = DCACHE_ERROR_BUS_ERROR;
658	rdata = address; // convention : cache return the address fautive !
659	}
660	else
661	{
662	rdata = _memory->access (context_id, address, out_DCACHE_REQ_TYPE->read(), out_DCACHE_REQ_WDATA->read());
663	LABEL(" * rdata : " + toString(rdata));
664	}
665
666	// test type : send or not a respons !
667	if ((out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_SYNCHRONIZATION) or
668	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD) or
669	((error != DCACHE_ERROR_NONE) and ((out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_8 ) or
670	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_16) or
671	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_32) or
672	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_64) )))
673	{
674	LABEL(" * have_dcache_rsp");
675
676	_cache->push (context_id,
677	out_DCACHE_REQ_PACKET_ID ->read(),
678	rdata,
679	error);
680	}
681	}
682
683	LABEL("DCACHE_RSP : "+toString(in_DCACHE_RSP_VAL->read())+" - "+toString(out_DCACHE_RSP_ACK ->read()));
684	if (in_DCACHE_RSP_VAL->read() and out_DCACHE_RSP_ACK->read())
685	{
686	_cache->pop();
687	}
688
689	_cache->end_cycle();
690
691	SC_START(1);
692	}
693	}
694	catch (morpheo::ErrorMorpheo & error)
695	{
696	_memory->trace();
697	throw (error);
698	}
699
700	_memory->trace();
701
702
703	/********************************************************
704	* Simulation - End
705	********************************************************/
706
707	TEST_OK ("End of Simulation");
708	delete _time;
709	cout << "<" << name << "> ............ Stop Simulation" << endl;
710
711	delete in_CLOCK;
712	delete in_NRESET;
713
714	delete in_MEMORY_IN_VAL ;
715	delete out_MEMORY_IN_ACK ;
716	delete in_MEMORY_IN_CONTEXT_ID ;
717	delete in_MEMORY_IN_FRONT_END_ID ;
718	delete in_MEMORY_IN_OOO_ENGINE_ID ;
719	delete in_MEMORY_IN_PACKET_ID ;
720	delete in_MEMORY_IN_OPERATION ;
721	delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
722	delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
723	//delete in_MEMORY_IN_HAS_IMMEDIAT;
724	delete in_MEMORY_IN_IMMEDIAT ;
725	delete in_MEMORY_IN_DATA_RA ;
726	delete in_MEMORY_IN_DATA_RB ;
727	//delete in_MEMORY_IN_DATA_RC ;
728	// delete in_MEMORY_IN_WRITE_RD ;
729	delete in_MEMORY_IN_NUM_REG_RD ;
730	//delete in_MEMORY_IN_WRITE_RE ;
731	//delete in_MEMORY_IN_NUM_REG_RE ;
732
733	delete out_MEMORY_OUT_VAL ;
734	delete in_MEMORY_OUT_ACK ;
735	delete out_MEMORY_OUT_CONTEXT_ID;
736	delete out_MEMORY_OUT_FRONT_END_ID;
737	delete out_MEMORY_OUT_OOO_ENGINE_ID;
738	delete out_MEMORY_OUT_PACKET_ID ;
739	delete out_MEMORY_OUT_WRITE_RD ;
740	delete out_MEMORY_OUT_NUM_REG_RD;
741	delete out_MEMORY_OUT_DATA_RD ;
742	//delete out_MEMORY_OUT_WRITE_RE ;
743	//delete out_MEMORY_OUT_NUM_REG_RE;
744	//delete out_MEMORY_OUT_DATA_RE ;
745	delete out_MEMORY_OUT_EXCEPTION ;
746
747	delete out_DCACHE_REQ_VAL ;
748	delete in_DCACHE_REQ_ACK ;
749	delete out_DCACHE_REQ_CONTEXT_ID;
750	delete out_DCACHE_REQ_PACKET_ID ;
751	delete out_DCACHE_REQ_ADDRESS ;
752	delete out_DCACHE_REQ_TYPE ;
753	delete out_DCACHE_REQ_WDATA ;
754
755	delete in_DCACHE_RSP_VAL ;
756	delete out_DCACHE_RSP_ACK ;
757	delete in_DCACHE_RSP_CONTEXT_ID;
758	delete in_DCACHE_RSP_PACKET_ID ;
759	delete in_DCACHE_RSP_RDATA ;
760	delete in_DCACHE_RSP_ERROR ;
761
762	if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
763	{
764	delete [] out_BYPASS_MEMORY_VAL ;
765	delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
766	delete [] out_BYPASS_MEMORY_NUM_REG ;
767	delete [] out_BYPASS_MEMORY_DATA ;
768	}
769	#endif
770
771	delete _Load_store_unit;
772	delete _memory;
773	delete _cache;
774	#ifdef STATISTICS
775	delete _parameters_statistics;
776	#endif
777	delete _param;
778	}

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