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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp @ 97

Last change on this file since 97 was 97, checked in by rosiere, 15 years ago
1) Update Prediction Table : statistics 2) Size instruction address on 30 bits 3) Change Log File 4) Add debug_level in simulation configuration file
Property svn:keywords set to `Id`
File size: 43.7 KB

Line
1	/*
2	* $Id: test2.cpp 97 2008-12-19 15:34:00Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include <queue>
10	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
11	#include "Behavioural/include/Allocation.h"
12
13	//===================================================================={test}
14	void test2 (void)
15	{
16	std::string name = "Test_Load_store_queue_manual";
17
18	cout << "<" << name << "> : Simulation SystemC" << endl;
19
20
21	morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters
22	(
23	4, //_size_store_queue
24	4, //_size_load_queue
25	2, //_size_speculative_access_queue
26	2, //_nb_port_check
27	SPECULATIVE_LOAD_COMMIT, //_speculative_load
28	0, //_nb_bypass_memory
29	1, //_nb_cache_port
30	1, //_nb_inst_memory
31	1, //_nb_context
32	1, //_nb_front_end
33	2, //_nb_ooo_engine
34	128,//_nb_packet
35	32, //_size_general_data
36	2 , //_size_special_data
37	64, //_nb_general_register
38	16, //_nb_special_register
39	true //is_toplevel
40	);
41
42	#ifdef STATISTICS
43	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
44	#endif
45
46	Tusage_t _usage = USE_ALL;
47
48	// _usage = usage_unset(_usage,USE_SYSTEMC );
49	// _usage = usage_unset(_usage,USE_VHDL );
50	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
51	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
52	// _usage = usage_unset(_usage,USE_POSITION );
53	// _usage = usage_unset(_usage,USE_STATISTICS );
54	// _usage = usage_unset(_usage,USE_INFORMATION );
55
56	Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(),
57	#ifdef STATISTICS
58	_parameters_statistics,
59	#endif
60	_param,
61	_usage);
62
63	#ifdef SYSTEMC
64	/*********************************************************************
65	* Déclarations des signaux
66	*********************************************************************/
67	string rename = "";
68
69	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
70	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
71
72	// ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
73	ALLOC1_SC_SIGNAL( in_MEMORY_IN_VAL ," in_MEMORY_IN_VAL ",Tcontrol_t ,_param->_nb_inst_memory);
74	ALLOC1_SC_SIGNAL(out_MEMORY_IN_ACK ,"out_MEMORY_IN_ACK ",Tcontrol_t ,_param->_nb_inst_memory);
75	ALLOC1_SC_SIGNAL( in_MEMORY_IN_CONTEXT_ID ," in_MEMORY_IN_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_memory);
76	ALLOC1_SC_SIGNAL( in_MEMORY_IN_FRONT_END_ID ," in_MEMORY_IN_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_memory);
77	ALLOC1_SC_SIGNAL( in_MEMORY_IN_OOO_ENGINE_ID ," in_MEMORY_IN_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_inst_memory);
78	ALLOC1_SC_SIGNAL( in_MEMORY_IN_PACKET_ID ," in_MEMORY_IN_PACKET_ID ",Tpacket_t ,_param->_nb_inst_memory);
79	ALLOC1_SC_SIGNAL( in_MEMORY_IN_OPERATION ," in_MEMORY_IN_OPERATION ",Toperation_t ,_param->_nb_inst_memory);
80	ALLOC1_SC_SIGNAL( in_MEMORY_IN_TYPE ," in_MEMORY_IN_TYPE ",Ttype_t ,_param->_nb_inst_memory);
81	ALLOC1_SC_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE," in_MEMORY_IN_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_inst_memory);
82	ALLOC1_SC_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ," in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_inst_memory);
83	ALLOC1_SC_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT ," in_MEMORY_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_memory);
84	ALLOC1_SC_SIGNAL( in_MEMORY_IN_IMMEDIAT ," in_MEMORY_IN_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_memory); // memory address
85	ALLOC1_SC_SIGNAL( in_MEMORY_IN_DATA_RA ," in_MEMORY_IN_DATA_RA ",Tgeneral_data_t ,_param->_nb_inst_memory); // memory address
86	ALLOC1_SC_SIGNAL( in_MEMORY_IN_DATA_RB ," in_MEMORY_IN_DATA_RB ",Tgeneral_data_t ,_param->_nb_inst_memory); // data (store)
87	ALLOC1_SC_SIGNAL( in_MEMORY_IN_DATA_RC ," in_MEMORY_IN_DATA_RC ",Tspecial_data_t ,_param->_nb_inst_memory);
88	ALLOC1_SC_SIGNAL( in_MEMORY_IN_WRITE_RD ," in_MEMORY_IN_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_memory); // = (operation==load)
89	ALLOC1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RD ," in_MEMORY_IN_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_memory); // destination (load)
90	ALLOC1_SC_SIGNAL( in_MEMORY_IN_WRITE_RE ," in_MEMORY_IN_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_memory);
91	ALLOC1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RE ," in_MEMORY_IN_NUM_REG_RE ",Tspecial_address_t,_param->_nb_inst_memory);
92	ALLOC1_SC_SIGNAL(out_MEMORY_OUT_VAL ,"out_MEMORY_OUT_VAL ",Tcontrol_t ,_param->_nb_inst_memory);
93	ALLOC1_SC_SIGNAL( in_MEMORY_OUT_ACK ," in_MEMORY_OUT_ACK ",Tcontrol_t ,_param->_nb_inst_memory);
94	ALLOC1_SC_SIGNAL(out_MEMORY_OUT_CONTEXT_ID ,"out_MEMORY_OUT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_memory);
95	ALLOC1_SC_SIGNAL(out_MEMORY_OUT_FRONT_END_ID ,"out_MEMORY_OUT_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_memory);
96	ALLOC1_SC_SIGNAL(out_MEMORY_OUT_OOO_ENGINE_ID ,"out_MEMORY_OUT_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_inst_memory);
97	ALLOC1_SC_SIGNAL(out_MEMORY_OUT_PACKET_ID ,"out_MEMORY_OUT_PACKET_ID ",Tpacket_t ,_param->_nb_inst_memory);
98	//ALLOC1_SC_SIGNAL(out_MEMORY_OUT_OPERATION ,"out_MEMORY_OUT_OPERATION ",Toperation_t ,_param->_nb_inst_memory);
99	//ALLOC1_SC_SIGNAL(out_MEMORY_OUT_TYPE ,"out_MEMORY_OUT_TYPE ",Ttype_t ,_param->_nb_inst_memory);
100	ALLOC1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RD ,"out_MEMORY_OUT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_memory); // = (operation==load)
101	ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,"out_MEMORY_OUT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_memory); // destination (load)
102	ALLOC1_SC_SIGNAL(out_MEMORY_OUT_DATA_RD ,"out_MEMORY_OUT_DATA_RD ",Tgeneral_data_t ,_param->_nb_inst_memory); // data (load)
103	ALLOC1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RE ,"out_MEMORY_OUT_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_memory);
104	ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RE ,"out_MEMORY_OUT_NUM_REG_RE ",Tspecial_address_t,_param->_nb_inst_memory);
105	ALLOC1_SC_SIGNAL(out_MEMORY_OUT_DATA_RE ,"out_MEMORY_OUT_DATA_RE ",Tspecial_data_t ,_param->_nb_inst_memory);
106	ALLOC1_SC_SIGNAL(out_MEMORY_OUT_EXCEPTION ,"out_MEMORY_OUT_EXCEPTION ",Texception_t ,_param->_nb_inst_memory);
107	ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE ,"out_MEMORY_OUT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_memory);
108	ALLOC1_SC_SIGNAL(out_MEMORY_OUT_ADDRESS ,"out_MEMORY_OUT_ADDRESS ",Taddress_t ,_param->_nb_inst_memory);
109	ALLOC1_SC_SIGNAL(out_DCACHE_REQ_VAL ,"out_DCACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_cache_port);
110	ALLOC1_SC_SIGNAL( in_DCACHE_REQ_ACK ," in_DCACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_cache_port);
111	ALLOC1_SC_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,"out_DCACHE_REQ_CONTEXT_ID ",Tcontext_t ,_param->_nb_cache_port);
112	ALLOC1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,"out_DCACHE_REQ_PACKET_ID ",Tpacket_t ,_param->_nb_cache_port);
113	ALLOC1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,"out_DCACHE_REQ_ADDRESS ",Tdcache_address_t ,_param->_nb_cache_port);
114	ALLOC1_SC_SIGNAL(out_DCACHE_REQ_TYPE ,"out_DCACHE_REQ_TYPE ",Tdcache_type_t ,_param->_nb_cache_port);
115	ALLOC1_SC_SIGNAL(out_DCACHE_REQ_WDATA ,"out_DCACHE_REQ_WDATA ",Tdcache_data_t ,_param->_nb_cache_port);
116	ALLOC1_SC_SIGNAL( in_DCACHE_RSP_VAL ," in_DCACHE_RSP_VAL ",Tcontrol_t ,_param->_nb_cache_port);
117	ALLOC1_SC_SIGNAL(out_DCACHE_RSP_ACK ,"out_DCACHE_RSP_ACK ",Tcontrol_t ,_param->_nb_cache_port);
118	ALLOC1_SC_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ," in_DCACHE_RSP_CONTEXT_ID ",Tcontext_t ,_param->_nb_cache_port);
119	ALLOC1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ," in_DCACHE_RSP_PACKET_ID ",Tpacket_t ,_param->_nb_cache_port);
120	ALLOC1_SC_SIGNAL( in_DCACHE_RSP_RDATA ," in_DCACHE_RSP_RDATA ",Tdcache_data_t ,_param->_nb_cache_port);
121	ALLOC1_SC_SIGNAL( in_DCACHE_RSP_ERROR ," in_DCACHE_RSP_ERROR ",Tdcache_error_t ,_param->_nb_cache_port);
122	ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_VAL ,"out_BYPASS_MEMORY_VAL ",Tcontrol_t ,_param->_nb_bypass_memory);
123	ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_OOO_ENGINE_ID ,"out_BYPASS_MEMORY_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_bypass_memory);
124	ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_NUM_REG ,"out_BYPASS_MEMORY_NUM_REG ",Tgeneral_address_t,_param->_nb_bypass_memory);
125	ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_DATA ,"out_BYPASS_MEMORY_DATA ",Tgeneral_data_t ,_param->_nb_bypass_memory);
126
127	/********************************************************
128	* Instanciation
129	********************************************************/
130
131	cout << "<" << name << "> Instanciation of _Load_store_unit" << endl;
132
133	((_Load_store_unit->in_CLOCK)) ((in_CLOCK));
134	((_Load_store_unit->in_NRESET)) ((in_NRESET));
135
136	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_VAL ,_param->_nb_inst_memory);
137	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_IN_ACK ,_param->_nb_inst_memory);
138	if (_param->_have_port_context_id)
139	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_CONTEXT_ID ,_param->_nb_inst_memory);
140	if (_param->_have_port_front_end_id)
141	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_FRONT_END_ID ,_param->_nb_inst_memory);
142	if (_param->_have_port_ooo_engine_id)
143	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_OOO_ENGINE_ID ,_param->_nb_inst_memory);
144	if (_param->_have_port_rob_ptr)
145	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_PACKET_ID ,_param->_nb_inst_memory);
146	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_OPERATION ,_param->_nb_inst_memory);
147	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_TYPE ,_param->_nb_inst_memory);
148	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory);
149	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory);
150	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_HAS_IMMEDIAT ,_param->_nb_inst_memory);
151	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_IMMEDIAT ,_param->_nb_inst_memory);
152	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_DATA_RA ,_param->_nb_inst_memory);
153	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_DATA_RB ,_param->_nb_inst_memory);
154	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_DATA_RC ,_param->_nb_inst_memory);
155	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_WRITE_RD ,_param->_nb_inst_memory);
156	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_NUM_REG_RD ,_param->_nb_inst_memory);
157	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_WRITE_RE ,_param->_nb_inst_memory);
158	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_NUM_REG_RE ,_param->_nb_inst_memory);
159
160	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_VAL ,_param->_nb_inst_memory);
161	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_OUT_ACK ,_param->_nb_inst_memory);
162	if (_param->_have_port_context_id)
163	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_CONTEXT_ID ,_param->_nb_inst_memory);
164	if (_param->_have_port_front_end_id)
165	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_FRONT_END_ID ,_param->_nb_inst_memory);
166	if (_param->_have_port_ooo_engine_id)
167	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_OOO_ENGINE_ID,_param->_nb_inst_memory);
168	if (_param->_have_port_rob_ptr)
169	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory);
170	//INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory);
171	//INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory);
172	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory);
173	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory);
174	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_DATA_RD ,_param->_nb_inst_memory);
175	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_WRITE_RE ,_param->_nb_inst_memory);
176	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NUM_REG_RE ,_param->_nb_inst_memory);
177	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_DATA_RE ,_param->_nb_inst_memory);
178	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_EXCEPTION ,_param->_nb_inst_memory);
179	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NO_SEQUENCE ,_param->_nb_inst_memory);
180	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_ADDRESS ,_param->_nb_inst_memory);
181
182	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_VAL ,_param->_nb_cache_port);
183	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_REQ_ACK ,_param->_nb_cache_port);
184	if (_param->_have_port_dcache_context_id)
185	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_cache_port);
186	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_PACKET_ID ,_param->_nb_cache_port);
187	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_ADDRESS ,_param->_nb_cache_port);
188	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_TYPE ,_param->_nb_cache_port);
189	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_WDATA ,_param->_nb_cache_port);
190
191	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_VAL ,_param->_nb_cache_port);
192	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_RSP_ACK ,_param->_nb_cache_port);
193	if (_param->_have_port_dcache_context_id)
194	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_cache_port);
195	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_PACKET_ID ,_param->_nb_cache_port);
196	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_RDATA ,_param->_nb_cache_port);
197	INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_ERROR ,_param->_nb_cache_port);
198
199	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_VAL ,_param->_nb_bypass_memory);
200	if (_param->_have_port_ooo_engine_id)
201	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory);
202	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_NUM_REG ,_param->_nb_bypass_memory);
203	INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_DATA ,_param->_nb_bypass_memory);
204
205
206	cout << "<" << name << "> Start Simulation ............" << endl;
207	Time * _time = new Time();
208
209	/********************************************************
210	* Simulation - Begin
211	********************************************************/
212
213	// Initialisation
214
215	const uint32_t seed = 0;
216	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
217
218	srand(seed);
219
220	const int32_t percent_transaction_memory_out = 100;
221	const int32_t percent_transaction_dcache = 100;
222	const uint32_t miss_rate = 0;
223	const uint32_t miss_penality = 0;
224
225	uint32_t nb_request_memory_out=0;
226
227	MemoryRequest_t tab_request [_param->_nb_packet];
228	priority_queue<MemoryRequest_t> fifo_request;
229
230	const uint32_t size_memory = 0x100;
231	// emulation of memory
232	Memory_t * _memory = new Memory_t (1<<_param->_size_dcache_context_id, size_memory, _param->_size_general_data);
233	Cache_t * _cache = new Cache_t (miss_rate, miss_penality);
234
235	SC_START(0);
236
237	LABEL("Initialisation");
238
239	in_MEMORY_IN_VAL [0]->write(0);
240	in_MEMORY_OUT_ACK[0]->write(0);
241	in_DCACHE_REQ_ACK[0]->write(0);
242	in_DCACHE_RSP_VAL[0]->write(0);
243
244	in_NRESET ->write(0);
245	SC_START(5);
246	in_NRESET ->write(5);
247
248	LABEL("Loop of Test");
249
250	try
251	{
252	LABEL("Structure's initialisation");
253
254	bool store_queue_use [_param->_size_store_queue];
255	uint32_t nb_store_slot_use = 0;
256	bool load_queue_use [_param->_size_load_queue ];
257
258	for (uint32_t i=0; i<_param->_size_store_queue; i++)
259	store_queue_use [i] = false;
260	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
261	load_queue_use [i] = false;
262
263
264	//--------------------------------------------------------------------------------------------------------------
265	// c c f o p o t s l i d d w n w
266	// y o r o a p y t o m a a r u r
267	// c n o o c e p o a m t t i m i
268	// l t n _ k r e r d e a a t _ t
269	// e e t e e a e _ d _ _ e r e
270	// x _ n t t _ p i r r _ _ _
271	// t e g _ i p t a a b r g s
272	// _ n i i o t r t d _ p
273	// i d n d n r _ r e
274	// d _ e _ w d c
275	// i _ w r _
276	// d i r i k
277	// d i t o
278	// t e
279	// e
280	//
281	tab_request[ 0].modif( 5,0,0,0, 0,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x10 ,0xdead1234,0,0,0);
282
283	tab_request[ 1].modif(10,0,0,0, 0,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
284
285	// READ 32b
286	tab_request[ 2].modif(12,0,0,0, 2,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,1,0,0xdead1234);
287	tab_request[ 3].modif(13,0,0,0, 3,OPERATION_MEMORY_LOAD_32_S ,TYPE_MEMORY,1,1,0x10 ,0x0 ,0x0 ,1,2,0,0xdead1234);
288
289	// READ 16b
290	tab_request[ 4].modif(14,0,0,0, 4,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,1,2,0x10 ,0x0 ,0x0 ,1,3,0,0x00001234);
291	tab_request[ 5].modif(15,0,0,0, 5,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,1,3,0x12 ,0x0 ,0x0 ,1,4,0,0x0000dead);
292	tab_request[ 6].modif(16,0,0,0, 6,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,5,0,0x00001234);
293	tab_request[ 7].modif(17,0,0,0, 7,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,1,1,0x12 ,0x0 ,0x0 ,1,6,0,0xffffdead);
294
295	// READ 8b
296	tab_request[ 8].modif(18,0,0,0, 8,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,7,0,0x00000034);
297	tab_request[ 9].modif(19,0,0,0, 9,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,1,0x11 ,0x0 ,0x0 ,1,8,0,0x00000012);
298	tab_request[10].modif(20,0,0,0,10,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,2,0x12 ,0x0 ,0x0 ,1,9,0,0x000000ad);
299	tab_request[11].modif(21,0,0,0,11,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,3,0x13 ,0x0 ,0x0 ,1,1,0,0x000000de);
300	tab_request[12].modif(22,0,0,0,12,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,2,0,0x00000034);
301	tab_request[13].modif(23,0,0,0,13,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,1,0x11 ,0x0 ,0x0 ,1,3,0,0x00000012);
302	tab_request[14].modif(24,0,0,0,14,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,2,0x12 ,0x0 ,0x0 ,1,4,0,0xffffffad);
303	tab_request[15].modif(25,0,0,0,15,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,3,0x13 ,0x0 ,0x0 ,1,5,0,0xffffffde);
304
305	// STORE 16b
306	tab_request[16].modif(30,0,0,0,16,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,1,0,0x20 ,0x0 ,0xffffabcd,0,0,0);
307	tab_request[17].modif(31,0,0,0,17,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,2,0,0x22 ,0x0 ,0xffffdcba,0,0,0);
308	tab_request[18].modif(35,0,0,0,18,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
309	tab_request[19].modif(36,0,0,0,19,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
310	tab_request[20].modif(40,0,0,0,20,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,0,0x20 ,0x0 ,0x0 ,1,0,0,0xdcbaabcd);
311
312	// STORE 8b and head / valid out order
313	tab_request[21].modif(50,0,0,0,21,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,3,0,0x1 ,0x4 ,0xffffff56,0,0,0);
314	tab_request[22].modif(55,0,0,0,22,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x1 ,0x0 ,0x0 ,0,0,0);
315	tab_request[23].modif(48,0,0,0,23,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,0,0,0x0 ,0x4 ,0xffffff78,0,0,0);
316	tab_request[24].modif(43,0,0,0,24,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
317	tab_request[25].modif(47,0,0,0,25,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,1,0,0x3 ,0x4 ,0xffffff12,0,0,0);
318	tab_request[26].modif(49,0,0,0,26,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
319	tab_request[27].modif(57,0,0,0,27,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,2,0,0x2 ,0x4 ,0xffffff34,0,0,0);
320	tab_request[28].modif(44,0,0,0,28,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
321	tab_request[29].modif(70,0,0,0,29,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,1,0x2 ,0x2 ,0x0 ,1,0,0,0x12345678);
322
323	// CHECK - with a store not present, store format is >=
324	tab_request[30].modif(180,0,0,0,30,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,3,0,0x0 ,0x30 ,0x21071981,0,0,0);
325	tab_request[31].modif(179,0,0,0,31,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0);
326	tab_request[32].modif(173,0,0,0,32,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x30 ,0x0 ,1,0,0,0x21071981);
327	tab_request[33].modif(174,0,0,0,33,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,0,3,0x0 ,0x30 ,0x0 ,1,0,0,0x00001981);
328	tab_request[34].modif(175,0,0,0,34,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,0,0,0x0 ,0x32 ,0x0 ,1,0,0,0x00002107);
329	tab_request[35].modif(176,0,0,0,35,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,0,1,0x0 ,0x31 ,0x0 ,1,0,0,0x00000019);
330
331	// CHECK - with a store not present, multiple store and format is different
332	tab_request[36].modif(200,0,0,0,36,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x40 ,0xffffffff,0,0,0);
333	tab_request[37].modif(200,0,0,0,37,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
334	tab_request[38].modif(220,0,0,0,38,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,1,0,0x0 ,0x42 ,0xbaba ,0,0,0);
335	tab_request[39].modif(245,0,0,0,39,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
336	tab_request[40].modif(224,0,0,0,40,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,2,0,0x0 ,0x42 ,0xbe ,0,0,0);
337	tab_request[41].modif(240,0,0,0,41,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
338	tab_request[42].modif(228,0,0,0,42,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,3,0,0x0 ,0x40 ,0xf00d ,0,0,0);
339	tab_request[43].modif(235,0,0,0,43,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0);
340	tab_request[44].modif(210,0,0,0,44,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x40 ,0x0 ,1,0,0,0xbabef00d);
341	tab_request[45].modif(211,0,0,0,45,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,2,3,0x0 ,0x40 ,0x0 ,1,0,0,0xbabaffff);
342	tab_request[46].modif(212,0,0,0,46,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,0,0x0 ,0x40 ,0x0 ,1,0,0,0xbabeffff);
343	tab_request[47].modif(213,0,0,0,47,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,3,1,0x0 ,0x42 ,0x0 ,1,0,0,0xffffffbe);
344
345
346	// CHECK - with different ooo_engine_id
347	tab_request[48].modif(300,0,0,0,48,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x0 ,0xdad1900d,0,0,0);
348	tab_request[49].modif(300,0,0,0,49,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
349	tab_request[50].modif(300,0,0,1,50,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x55508570,0,0,0);
350	tab_request[51].modif(300,0,0,1,51,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
351
352
353	tab_request[52].modif(320,0,0,0,52,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,2,2,0x0 ,0x2 ,0x0 ,1,0,0,0xffffdad1);
354	tab_request[53].modif(321,0,0,1,53,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,2,3,0x0 ,0x0 ,0x0 ,1,0,0,0xffff8570);
355
356
357	// with a little exception
358	tab_request[54].modif(330,0,0,1,54,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,2,0,0x0 ,0x0 ,0xffff6996,0,0,1);
359	tab_request[55].modif(340,0,0,1,55,OPERATION_MEMORY_STORE_HEAD_KO,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
360	tab_request[56].modif(322,0,0,1,56,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,3,0,0x0 ,0x1 ,0x0 ,1,0,0,0x00000069); // they are a bypass (because, the cpu go in exception handler ... load is not use)
361	tab_request[57].modif(350,0,0,1,57,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,1,0x0 ,0x0 ,0x0 ,1,0,0,0x55508570); // the memory have not change
362
363
364	// multiple event
365	// * store : miss_spec and aligment, priority : miss_spec > aligment
366	// * load : miss_spec and aligment, priority : miss_spec > aligment
367	tab_request[58].modif(410,0,0,0,58,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,3,0,0x0 ,0x1 ,0x0 ,0,0,1);
368	tab_request[59].modif(415,0,0,0,59,OPERATION_MEMORY_STORE_HEAD_KO,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0);
369
370	tab_request[60].modif(430,0,0,0,60,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x0 ,0x0 ,1,0,0,0xdad1900d);
371	tab_request[61].modif(400,0,0,0,61,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,3,0x0 ,0x3 ,0x0 ,1,0,0); // miss_spec and alignment
372	tab_request[62].modif(450,0,0,0,62,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,0,0x0 ,size_memory ,0x0 ,1,0,0); // bus error and alignement
373	tab_request[63].modif(460,0,0,0,63,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,1,0x0 ,size_memory+1,0x0 ,1,0,0); // bus error and alignement
374
375
376
377	tab_request[64].modif(500,0,0,0,64,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,size_memory ,0x0 ,0,0,0); // bus error
378	tab_request[65].modif(505,0,0,0,65,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
379	tab_request[66].modif(550,0,0,0,65,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,1,0,0,0x55508570); // just to wait the dcache_rsp
380
381	const uint32_t nb_request = 64;//_param->_nb_packet;
382
383	for (uint32_t i=0; i<nb_request; i++)
384	{
385	std::cout << tab_request [i] << std::endl;
386	fifo_request.push(tab_request [i]);
387	}
388	LABEL("Simulation ...");
389
390	while (nb_request_memory_out < nb_request)
391	{
392	cout << "*********************************************" << endl;
393	cout << "Dump STORE_QUEUE_USE : " << endl;
394	cout << " use " << nb_store_slot_use << endl;
395	for (uint32_t i=0; i<_param->_size_store_queue; i++)
396	cout << " [" << i << "] " << store_queue_use [i] << endl;
397	cout << "Dump LOAD_QUEUE_USE : " << endl;
398	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
399	cout << " [" << i << "] " << load_queue_use [i] << endl;
400	cout << "*********************************************" << endl;
401
402
403	// *** MEMORY_IN ***
404
405	// memory_in_val depends of three factors :
406	// 1) request's fifo is not empty ?
407	// 2) the slot destination is free ?
408	// 3) The head of request's fifo can be issue : the number of cycle is more than current cycle
409
410	bool can_execute = false;
411
412	if (not fifo_request.empty())
413	{
414	can_execute = sc_simulation_time() >= fifo_request.top()._cycle;
415	if (is_operation_memory_store(fifo_request.top()._operation))
416	can_execute &= (not store_queue_use [fifo_request.top()._store_queue_ptr_write] and (nb_store_slot_use < _param->_size_store_queue-1)) or is_operation_memory_store_head(fifo_request.top()._operation);
417	else
418	can_execute &= not load_queue_use [fifo_request.top()._load_queue_ptr_write];
419	}
420	in_MEMORY_IN_VAL [0]->write(can_execute);
421
422	if (not fifo_request.empty())
423	{
424	if (_param->_have_port_context_id)
425	in_MEMORY_IN_CONTEXT_ID [0]->write (fifo_request.top()._context_id );
426	if (_param->_have_port_front_end_id)
427	in_MEMORY_IN_FRONT_END_ID [0]->write (fifo_request.top()._front_end_id );
428	if (_param->_have_port_ooo_engine_id)
429	in_MEMORY_IN_OOO_ENGINE_ID [0]->write (fifo_request.top()._ooo_engine_id );
430	if (_param->_have_port_rob_ptr)
431	in_MEMORY_IN_PACKET_ID [0]->write (fifo_request.top()._packet_id );
432	in_MEMORY_IN_OPERATION [0]->write (fifo_request.top()._operation );
433	in_MEMORY_IN_TYPE [0]->write (fifo_request.top()._type );
434	in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[0]->write (fifo_request.top()._store_queue_ptr_write);
435	if (_param->_have_port_load_queue_ptr)
436	in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE [0]->write (fifo_request.top()._load_queue_ptr_write );
437	in_MEMORY_IN_IMMEDIAT [0]->write (fifo_request.top()._immediat );
438	in_MEMORY_IN_DATA_RA [0]->write (fifo_request.top()._data_ra );
439	in_MEMORY_IN_DATA_RB [0]->write (fifo_request.top()._data_rb );
440	// in_MEMORY_IN_WRITE_RD [0]->write (fifo_request.top()._write_rd );
441	in_MEMORY_IN_NUM_REG_RD [0]->write (fifo_request.top()._num_reg_rd );
442	}
443	in_MEMORY_OUT_ACK[0]->write((rand()%100)<percent_transaction_memory_out);
444
445	// *** DCACHE_REQ ***
446	in_DCACHE_REQ_ACK[0]->write((rand()%100)<percent_transaction_dcache);
447
448	// *** DCACHE_RSP ***
449	bool have_rsp = _cache->have_rsp ();
450	in_DCACHE_RSP_VAL[0]->write(have_rsp);
451
452	if (have_rsp)
453	{
454	in_DCACHE_RSP_CONTEXT_ID[0]->write(_cache->front()._context_id);
455	in_DCACHE_RSP_PACKET_ID [0]->write(_cache->front()._packet_id );
456	in_DCACHE_RSP_RDATA [0]->write(_cache->front()._rdata );
457	in_DCACHE_RSP_ERROR [0]->write(_cache->front()._error );
458	}
459
460	SC_START(0);
461
462	LABEL("MEMORY_IN : %d - %d",in_MEMORY_IN_VAL [0]->read(),out_MEMORY_IN_ACK [0]->read());
463	if ( in_MEMORY_IN_VAL [0]->read() and out_MEMORY_IN_ACK [0]->read())
464	{
465	Tpacket_t packet_id = in_MEMORY_IN_PACKET_ID[0]->read();
466
467	LABEL(" * Accepted MEMORY_IN : %d",packet_id);
468	cout << fifo_request.top();
469
470	if (is_operation_memory_store(fifo_request.top()._operation))
471	{
472	if (not is_operation_memory_store_head(fifo_request.top()._operation))
473	{
474	store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;
475	nb_store_slot_use ++;
476	}
477	}
478	else
479	load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;
480
481	fifo_request.pop();
482	}
483
484	LABEL("MEMORY_OUT : %d - %d",out_MEMORY_OUT_VAL[0]->read(),in_MEMORY_OUT_ACK [0]->read());
485	if (out_MEMORY_OUT_VAL[0]->read() and in_MEMORY_OUT_ACK[0]->read())
486	{
487	Tpacket_t packet_id = out_MEMORY_OUT_PACKET_ID[0]->read();
488
489	LABEL(" * Accepted MEMORY_OUT : %d",packet_id);
490
491	if (is_operation_memory_store(tab_request[packet_id]._operation))
492	{
493	store_queue_use [tab_request[packet_id]._store_queue_ptr_write] = false;
494	nb_store_slot_use --;
495	nb_request_memory_out +=2;
496
497	}
498	else
499	{
500	if (not (out_MEMORY_OUT_EXCEPTION[0]->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
501	{
502	nb_request_memory_out ++;
503
504	load_queue_use [tab_request[packet_id]._load_queue_ptr_write] = false;
505	}
506	else
507	{
508	std::cout << "seth - have a load_speculative." << std::endl;
509	tab_request[packet_id]._write_spec_ko = (out_MEMORY_OUT_DATA_RD[0]->read() != tab_request[packet_id]._data_wait);
510	tab_request[packet_id]._previous_load_speculative = 1;
511	}
512	}
513
514	std::cout << "kane - nb_request_memory_out : " << nb_request_memory_out << std::endl;
515
516	// a lot of test
517	TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID [0]->read(), tab_request[packet_id]._packet_id );
518	TEST(Tcontext_t , out_MEMORY_OUT_CONTEXT_ID [0]->read(), tab_request[packet_id]._context_id );
519	TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID [0]->read(), tab_request[packet_id]._front_end_id );
520	TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID[0]->read(), tab_request[packet_id]._ooo_engine_id);
521	// TEST(Toperation_t , out_MEMORY_OUT_OPERATION [0]->read(), tab_request[packet_id]._operation );
522	// TEST(Ttype_t , out_MEMORY_OUT_TYPE [0]->read(), TYPE_MEMORY );
523
524	if (is_operation_memory_load (tab_request[packet_id]._operation))
525	{
526	TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD [0]->read(), tab_request[packet_id]._num_reg_rd );
527	}
528
529	Tgeneral_data_t address = tab_request[packet_id]._data_ra + tab_request[packet_id]._immediat;
530
531	bool error_alignment = (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation))));
532	bool berr = (address >= size_memory);
533	Texception_t exception = out_MEMORY_OUT_EXCEPTION[0]->read();
534
535	if (is_operation_memory_store(tab_request[packet_id]._operation))
536	{
537	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD [0]->read(), 0);
538
539	// store.
540	// prioritary : miss_speculation > aligmnent > DBERR
541
542	bool test_result_ko = false;
543
544	if (tab_request[packet_id]._write_spec_ko)
545	{
546	TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION);
547	}
548	else
549	if (error_alignment)
550	{
551	TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT);
552	test_result_ko = true;
553	}
554	else
555	if (berr)
556	{
557	// TODO NOT SUPPORTED
558	// TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR);
559
560	//test_result_ko = true;
561	}
562	else
563	{
564	TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE);
565	}
566	// In all case : test data
567	if (test_result_ko)
568	{
569	TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD[0]->read(), address);
570	}
571	}
572	else
573	{
574	// load
575	// prioritary : miss_speculation > aligmnent > DBERR
576
577	bool is_load = is_operation_memory_load(tab_request[packet_id]._operation);
578
579	if (not (out_MEMORY_OUT_EXCEPTION[0]->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
580	{
581	bool test_result_ko = false;
582
583	if (tab_request[packet_id]._write_spec_ko)
584	{
585	// IS A LOAD :D
586	TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION);
587	TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD[0]->read(), 1);
588	}
589	else
590	if (error_alignment)
591	{
592	TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT);
593	TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD[0]->read(), is_load);
594	test_result_ko = true;
595	}
596	else
597	if (berr)
598	{
599	TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR);
600	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD[0]->read(), is_load);
601	test_result_ko = true;
602	}
603	else
604	{
605	TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE);
606	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD[0]->read(), is_load and not tab_request[packet_id]._previous_load_speculative);
607	}
608	// In all case : test data
609	if (test_result_ko)
610	{
611	TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD[0]->read(), address);
612	}
613	else
614	{
615	TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD[0]->read(), tab_request[packet_id]._data_wait);
616	}
617	}
618	else
619	{
620	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD [0]->read(), 1);
621	}
622	}
623	}
624
625	LABEL("DCACHE_REQ : %d - %d",out_DCACHE_REQ_VAL[0]->read(),in_DCACHE_REQ_ACK [0]->read());
626	if (out_DCACHE_REQ_VAL[0]->read() and in_DCACHE_REQ_ACK[0]->read())
627	{
628	Tcontext_t context_id;
629	Tpacket_t packet_id ;
630	Tdcache_address_t address = out_DCACHE_REQ_ADDRESS[0]->read();
631	Tdcache_data_t rdata;
632	Tdcache_error_t error = 0;
633	if (_param->_have_port_dcache_context_id)
634	context_id = out_DCACHE_REQ_CONTEXT_ID[0]->read();
635	else
636	context_id = 0;
637
638	packet_id = (out_DCACHE_REQ_PACKET_ID [0]->read())>>1;
639
640	LABEL(" * Accepted DCACHE_REQ : %d",packet_id);
641
642	if (address >= size_memory)
643	{
644	// Bus error
645	error = DCACHE_ERROR_BUS_ERROR;
646	rdata = address; // convention : cache return the address fautive !
647	}
648	else
649	{
650	rdata = _memory->access (context_id, address, out_DCACHE_REQ_TYPE[0]->read(), out_DCACHE_REQ_WDATA[0]->read());
651	LABEL(" * rdata : 0x%x",rdata);
652	}
653
654	// test type : send or not a respons !
655	if ((out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_SYNCHRONIZATION) or
656	(out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_8 ) or
657	(out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_16) or
658	(out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_32) or
659	(out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_64) or
660	((error != DCACHE_ERROR_NONE) and ((out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_8 ) or
661	(out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_16) or
662	(out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_32) or
663	(out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_64) )))
664	{
665	LABEL(" * have_dcache_rsp");
666
667	_cache->push (context_id,
668	out_DCACHE_REQ_PACKET_ID [0]->read(),
669	rdata,
670	error);
671	}
672	}
673
674	LABEL("DCACHE_RSP : %d - %d",in_DCACHE_RSP_VAL[0]->read(),out_DCACHE_RSP_ACK [0]->read());
675	if (in_DCACHE_RSP_VAL[0]->read() and out_DCACHE_RSP_ACK[0]->read())
676	{
677	_cache->pop();
678	}
679
680	_cache->end_cycle();
681
682	SC_START(1);
683	}
684	}
685	catch (morpheo::ErrorMorpheo & error)
686	{
687	_memory->trace();
688	throw (error);
689	}
690
691	_memory->trace();
692
693
694	/********************************************************
695	* Simulation - End
696	********************************************************/
697
698	TEST_OK ("End of Simulation");
699	delete _time;
700	cout << "<" << name << "> ............ Stop Simulation" << endl;
701
702	delete in_CLOCK;
703	delete in_NRESET;
704
705	DELETE1_SC_SIGNAL( in_MEMORY_IN_VAL ,_param->_nb_inst_memory);
706	DELETE1_SC_SIGNAL(out_MEMORY_IN_ACK ,_param->_nb_inst_memory);
707	DELETE1_SC_SIGNAL( in_MEMORY_IN_CONTEXT_ID ,_param->_nb_inst_memory);
708	DELETE1_SC_SIGNAL( in_MEMORY_IN_FRONT_END_ID ,_param->_nb_inst_memory);
709	DELETE1_SC_SIGNAL( in_MEMORY_IN_OOO_ENGINE_ID ,_param->_nb_inst_memory);
710	DELETE1_SC_SIGNAL( in_MEMORY_IN_PACKET_ID ,_param->_nb_inst_memory);
711	DELETE1_SC_SIGNAL( in_MEMORY_IN_OPERATION ,_param->_nb_inst_memory);
712	DELETE1_SC_SIGNAL( in_MEMORY_IN_TYPE ,_param->_nb_inst_memory);
713	DELETE1_SC_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory);
714	DELETE1_SC_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory);
715	DELETE1_SC_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT ,_param->_nb_inst_memory);
716	DELETE1_SC_SIGNAL( in_MEMORY_IN_IMMEDIAT ,_param->_nb_inst_memory);
717	DELETE1_SC_SIGNAL( in_MEMORY_IN_DATA_RA ,_param->_nb_inst_memory);
718	DELETE1_SC_SIGNAL( in_MEMORY_IN_DATA_RB ,_param->_nb_inst_memory);
719	DELETE1_SC_SIGNAL( in_MEMORY_IN_DATA_RC ,_param->_nb_inst_memory);
720	DELETE1_SC_SIGNAL( in_MEMORY_IN_WRITE_RD ,_param->_nb_inst_memory);
721	DELETE1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RD ,_param->_nb_inst_memory);
722	DELETE1_SC_SIGNAL( in_MEMORY_IN_WRITE_RE ,_param->_nb_inst_memory);
723	DELETE1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RE ,_param->_nb_inst_memory);
724
725	DELETE1_SC_SIGNAL(out_MEMORY_OUT_VAL ,_param->_nb_inst_memory);
726	DELETE1_SC_SIGNAL( in_MEMORY_OUT_ACK ,_param->_nb_inst_memory);
727	DELETE1_SC_SIGNAL(out_MEMORY_OUT_CONTEXT_ID ,_param->_nb_inst_memory);
728	DELETE1_SC_SIGNAL(out_MEMORY_OUT_FRONT_END_ID ,_param->_nb_inst_memory);
729	DELETE1_SC_SIGNAL(out_MEMORY_OUT_OOO_ENGINE_ID,_param->_nb_inst_memory);
730	DELETE1_SC_SIGNAL(out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory);
731	//DELETE1_SC_SIGNAL(out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory);
732	//DELETE1_SC_SIGNAL(out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory);
733	DELETE1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory);
734	DELETE1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory);
735	DELETE1_SC_SIGNAL(out_MEMORY_OUT_DATA_RD ,_param->_nb_inst_memory);
736	DELETE1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RE ,_param->_nb_inst_memory);
737	DELETE1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RE ,_param->_nb_inst_memory);
738	DELETE1_SC_SIGNAL(out_MEMORY_OUT_DATA_RE ,_param->_nb_inst_memory);
739	DELETE1_SC_SIGNAL(out_MEMORY_OUT_EXCEPTION ,_param->_nb_inst_memory);
740	DELETE1_SC_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE ,_param->_nb_inst_memory);
741	DELETE1_SC_SIGNAL(out_MEMORY_OUT_ADDRESS ,_param->_nb_inst_memory);
742
743	DELETE1_SC_SIGNAL(out_DCACHE_REQ_VAL ,_param->_nb_cache_port);
744	DELETE1_SC_SIGNAL( in_DCACHE_REQ_ACK ,_param->_nb_cache_port);
745	DELETE1_SC_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_cache_port);
746	DELETE1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,_param->_nb_cache_port);
747	DELETE1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,_param->_nb_cache_port);
748	DELETE1_SC_SIGNAL(out_DCACHE_REQ_TYPE ,_param->_nb_cache_port);
749	DELETE1_SC_SIGNAL(out_DCACHE_REQ_WDATA ,_param->_nb_cache_port);
750
751	DELETE1_SC_SIGNAL( in_DCACHE_RSP_VAL ,_param->_nb_cache_port);
752	DELETE1_SC_SIGNAL(out_DCACHE_RSP_ACK ,_param->_nb_cache_port);
753	DELETE1_SC_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_cache_port);
754	DELETE1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ,_param->_nb_cache_port);
755	DELETE1_SC_SIGNAL( in_DCACHE_RSP_RDATA ,_param->_nb_cache_port);
756	DELETE1_SC_SIGNAL( in_DCACHE_RSP_ERROR ,_param->_nb_cache_port);
757
758	DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_VAL ,_param->_nb_bypass_memory);
759	DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory);
760	DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_NUM_REG ,_param->_nb_bypass_memory);
761	DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_DATA ,_param->_nb_bypass_memory);
762	#endif
763
764	delete _Load_store_unit;
765	delete _memory;
766	delete _cache;
767	#ifdef STATISTICS
768	delete _parameters_statistics;
769	#endif
770	delete _param;
771	}

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