source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp @ 97

Last change on this file since 97 was 97, checked in by rosiere, 15 years ago

1) Update Prediction Table : statistics
2) Size instruction address on 30 bits
3) Change Log File
4) Add debug_level in simulation configuration file
  • Property svn:keywords set to Id
File size: 10.7 KB
Line 
1#ifdef SYSTEMC
2//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
3/*
4 * $Id: Load_store_unit_function_speculative_load_commit_genMoore.cpp 97 2008-12-19 15:34:00Z rosiere $
5 *
6 * [ Description ]
7 *
8 */
9
10#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
11
12namespace morpheo                    {
13namespace behavioural {
14namespace core {
15namespace multi_execute_loop {
16namespace execute_loop {
17namespace multi_execute_unit {
18namespace execute_unit {
19namespace load_store_unit {
20
21
22#undef  FUNCTION
23#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMoore"
24  void Load_store_unit::function_speculative_load_commit_genMoore (void)
25  {
26    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
27
28    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
29
30    Tcontext_t         memory_out_context_id    = 0;
31    Tcontext_t         memory_out_front_end_id  = 0;
32    Tcontext_t         memory_out_ooo_engine_id = 0;
33    Tpacket_t          memory_out_packet_id     = 0;
34    Tcontrol_t         memory_out_write_rd      = 0;
35    Tgeneral_address_t memory_out_num_reg_rd    = 0;
36    Tgeneral_data_t    memory_out_data_rd       = 0;
37//  Tcontrol_t         memory_out_write_re      = 0;
38//  Tspecial_address_t memory_out_num_reg_re    = 0;
39//  Tspecial_data_t    memory_out_data_re       = 0;
40    Texception_t       memory_out_exception     = 0;
41
42    internal_MEMORY_OUT_VAL = 0;
43
44    // Test store and load queue
45
46    log_printf(TRACE,Load_store_unit,FUNCTION,"genMoore : Test MEMORY_OUT");
47
48    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Load  queue");
49    for (internal_MEMORY_OUT_PTR=0; internal_MEMORY_OUT_PTR<_param->_size_load_queue; internal_MEMORY_OUT_PTR++)
50//     for (uin32_t i=0; (i<_param->_size_load_queue) and not (find_load); i++)
51      {
52//      internal_MEMORY_OUT_PTR = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;
53        internal_MEMORY_OUT_VAL = ((_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK) or
54                                   (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT));
55       
56        if (internal_MEMORY_OUT_VAL)
57          {
58            log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",internal_MEMORY_OUT_PTR);
59            internal_MEMORY_OUT_SELECT_QUEUE = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?SELECT_LOAD_QUEUE_SPECULATIVE:SELECT_LOAD_QUEUE;
60           
61            memory_out_context_id    = _load_queue [internal_MEMORY_OUT_PTR]._context_id;
62            memory_out_front_end_id  = _load_queue [internal_MEMORY_OUT_PTR]._front_end_id;
63            memory_out_ooo_engine_id = _load_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id;
64            memory_out_packet_id     = _load_queue [internal_MEMORY_OUT_PTR]._packet_id ;
65            memory_out_write_rd      = _load_queue [internal_MEMORY_OUT_PTR]._write_rd  ;
66            memory_out_num_reg_rd    = _load_queue [internal_MEMORY_OUT_PTR]._num_reg_rd;
67
68            Tdcache_data_t data_old = _load_queue [internal_MEMORY_OUT_PTR]._rdata;
69            Tdcache_data_t data_new = extend<Tdcache_data_t>(_param->_size_general_data,
70                                                             data_old >> _load_queue [internal_MEMORY_OUT_PTR]._shift,
71                                                             _load_queue [internal_MEMORY_OUT_PTR]._is_load_signed,
72                                                             _load_queue [internal_MEMORY_OUT_PTR]._access_size);
73            log_printf(TRACE,Load_store_unit,FUNCTION,"    * data : %.8x",data_new);
74            log_printf(TRACE,Load_store_unit,FUNCTION,"      * rdata        : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata);
75            log_printf(TRACE,Load_store_unit,FUNCTION,"      * shift        : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift);
76            log_printf(TRACE,Load_store_unit,FUNCTION,"      * signed?      : %d",_load_queue [internal_MEMORY_OUT_PTR]._is_load_signed);
77            log_printf(TRACE,Load_store_unit,FUNCTION,"      * access_size  : %d",_load_queue [internal_MEMORY_OUT_PTR]._access_size);
78
79            Texception_t exception      = _load_queue [internal_MEMORY_OUT_PTR]._exception;
80            bool         have_exception = ((exception != EXCEPTION_MEMORY_NONE) and
81                                           (exception != EXCEPTION_MEMORY_MISS_SPECULATION));
82
83            // if exception, rdata content the address of load, else content read data.
84            memory_out_data_rd       = (have_exception)?data_old:data_new;
85            memory_out_exception     = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?EXCEPTION_MEMORY_LOAD_SPECULATIVE:exception;
86
87            break; // we have find a entry !!! stop the search
88          }
89      }
90
91    if (not internal_MEMORY_OUT_VAL)
92      {
93        log_printf(TRACE,Load_store_unit,FUNCTION,"  * Store queue");
94        if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT)
95          {
96            log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",reg_STORE_QUEUE_PTR_READ);
97
98            internal_MEMORY_OUT_VAL          = 1;
99            internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
100           
101            memory_out_context_id    = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id;
102            memory_out_front_end_id  = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id;
103            memory_out_ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id;
104            memory_out_packet_id     = _store_queue [reg_STORE_QUEUE_PTR_READ]._packet_id ;
105//          memory_out_write_rd         
106//          memory_out_num_reg_rd       
107            memory_out_data_rd       = _store_queue [reg_STORE_QUEUE_PTR_READ]._address; // to the exception
108            memory_out_exception     = _store_queue [reg_STORE_QUEUE_PTR_READ]._exception;
109          }
110      }
111    // write output
112    PORT_WRITE(out_MEMORY_OUT_VAL          [0], internal_MEMORY_OUT_VAL);
113
114    if (_param->_have_port_context_id)
115    PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID   [0], memory_out_context_id   );
116    if (_param->_have_port_front_end_id)
117    PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID [0], memory_out_front_end_id );
118    if (_param->_have_port_ooo_engine_id)
119    PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID[0], memory_out_ooo_engine_id);
120    if (_param->_have_port_rob_ptr)
121    PORT_WRITE(out_MEMORY_OUT_PACKET_ID    [0], memory_out_packet_id    );
122//  PORT_WRITE(out_MEMORY_OUT_OPERATION    [0], memory_out_operation    );
123//  PORT_WRITE(out_MEMORY_OUT_TYPE         [0], TYPE_MEMORY             );
124    PORT_WRITE(out_MEMORY_OUT_WRITE_RD     [0], memory_out_write_rd     );
125    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD   [0], memory_out_num_reg_rd   );
126    PORT_WRITE(out_MEMORY_OUT_DATA_RD      [0], memory_out_data_rd      );
127//  PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], memory_out_write_re     );
128//  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], memory_out_num_reg_re   );
129//  PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], memory_out_data_re      );
130    PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], 0);
131    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], 0);
132    PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], 0);
133    PORT_WRITE(out_MEMORY_OUT_EXCEPTION    [0], memory_out_exception    );
134    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  [0], 0);
135    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], 0);
136
137    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
138
139    Tcontext_t        dcache_req_context_id;
140    Tpacket_t         dcache_req_packet_id ;
141    Tdcache_address_t dcache_req_address   ;
142    Tdcache_type_t    dcache_req_type      ;
143    Tdcache_data_t    dcache_req_wdata     ;
144
145    log_printf(TRACE,Load_store_unit,FUNCTION,"genMoore : Test DCACHE_REQ");
146
147    internal_DCACHE_REQ_VAL = 0;
148
149    internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = (*_speculative_access_queue_control)[0];
150
151    // Test store and load queue
152    if (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE)
153      {
154        log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue[%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ);
155
156        internal_DCACHE_REQ_VAL          = 1;
157        internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE;
158
159        if (_param->_have_port_dcache_context_id)
160          {
161            Tcontext_t context_id    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id;
162            Tcontext_t front_end_id  = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id;
163            Tcontext_t ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id;
164           
165            dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
166                                     (front_end_id <<(_param->_size_context_id)) |
167                                     (context_id));
168          }
169
170        dcache_req_packet_id  = DCACHE_REQ_IS_LOAD(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write);
171        dcache_req_address    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address & _param->_mask_address_msb;
172        dcache_req_type       = operation_to_dcache_type(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation);
173#ifdef SYSTEMC_VHDL_COMPATIBILITY
174        dcache_req_wdata      = 0;
175#endif
176      }
177    else
178      {
179        // Test an store must be commited.
180        if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE)
181          {
182            internal_DCACHE_REQ_VAL          = 1;
183            internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE;
184           
185            if (_param->_have_port_dcache_context_id)
186              {
187                Tcontext_t context_id    = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id;
188                Tcontext_t front_end_id  = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id;
189                Tcontext_t ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id;
190               
191                dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
192                                         (front_end_id <<(_param->_size_context_id)) |
193                                         (context_id));
194              }
195
196            // FIXME : il peut avoir plusieurs store avec le même paquet_id ... pour l'instant pas très grave car pas de retour (enfin seul les bus error sont des retours)
197            dcache_req_packet_id  = DCACHE_REQ_IS_STORE(reg_STORE_QUEUE_PTR_READ);
198            dcache_req_address    = _store_queue [reg_STORE_QUEUE_PTR_READ]._address   ;
199            dcache_req_type       = operation_to_dcache_type(_store_queue [reg_STORE_QUEUE_PTR_READ]._operation);
200            dcache_req_wdata      = _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata     ;
201          }
202      }
203
204    PORT_WRITE(out_DCACHE_REQ_VAL       [0], internal_DCACHE_REQ_VAL);
205    if (_param->_have_port_dcache_context_id)
206    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id);
207    PORT_WRITE(out_DCACHE_REQ_PACKET_ID [0], dcache_req_packet_id );
208    PORT_WRITE(out_DCACHE_REQ_ADDRESS   [0], dcache_req_address   );
209    PORT_WRITE(out_DCACHE_REQ_TYPE      [0], dcache_req_type      );
210    PORT_WRITE(out_DCACHE_REQ_WDATA     [0], dcache_req_wdata     );
211   
212    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
213  };
214
215}; // end namespace load_store_unit
216}; // end namespace execute_unit
217}; // end namespace multi_execute_unit
218}; // end namespace execute_loop
219}; // end namespace multi_execute_loop
220}; // end namespace core
221
222}; // end namespace behavioural
223}; // end namespace morpheo             
224#endif
225//#endif
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