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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp @ 117

Last change on this file since 117 was 117, checked in by rosiere, 15 years ago
1) Platforms : add new organization for test 2) Load_Store_Unit : add array to count nb_check in store_queue 3) Issue_queue and Core_Glue : rewrite the issue network 4) Special_Register_Unit : add reset value to register CID 5) Softwares : add multicontext test 6) Softwares : add SPECINT 7) Softwares : add MiBench? 7) Read_queue : inhib access for r0 8) Change Core_Glue (network) - dont yet support priority and load balancing scheme
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File size: 54.9 KB

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1	#ifdef SYSTEMC
2	/*
3	* $Id: Load_store_unit_function_speculative_load_commit_transition.cpp 117 2009-05-16 14:42:39Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_execute_loop {
15	namespace execute_loop {
16	namespace multi_execute_unit {
17	namespace execute_unit {
18	namespace load_store_unit {
19
20	template <typename T>
21	T swapBytes (T data, uint32_t size_data, uint32_t size_access)
22	{
23	uint64_t x = static_cast<uint64_t>(data);
24
25	// switch (size_data)
26	// {
27	// case 2 : // 16 bits
28	// {
29	// switch (size_access)
30	// {
31	// case 2 :
32	// {
33	// x = ((((x>> 8)&0xff) << 0) \|
34	// (((x>> 0)&0xff) << 8) );
35	// break;
36	// }
37	// default :
38	// {
39	// break;
40	// }
41	// }
42	// break;
43	// }
44	// case 4 : // 32 bits
45	// {
46	// switch (size_access)
47	// {
48	// case 2 :
49	// {
50	// x = ((((x>> 8)&0xff) << 0) \|
51	// (((x>> 0)&0xff) << 8) \|
52	// (((x>>24)&0xff) << 16) \|
53	// (((x>>16)&0xff) << 24) );
54	// break;
55	// }
56	// case 4 :
57	// {
58	// x = ((((x>>24)&0xff) << 0) \|
59	// (((x>>16)&0xff) << 8) \|
60	// (((x>> 8)&0xff) << 16) \|
61	// (((x>> 0)&0xff) << 24) );
62	// break;
63	// }
64	// default :
65	// {
66	// break;
67	// }
68	// }
69	// break;
70	// }
71	// case 8 : // 64 bits
72	// {
73	// switch (size_access)
74	// {
75	// case 2 :
76	// {
77	// x = ((((x>> 8)&0xff) << 0) \|
78	// (((x>> 0)&0xff) << 8) \|
79	// (((x>>24)&0xff) << 16) \|
80	// (((x>>16)&0xff) << 24) \|
81	// (((x>>40)&0xff) << 32) \|
82	// (((x>>32)&0xff) << 40) \|
83	// (((x>>56)&0xff) << 48) \|
84	// (((x>>48)&0xff) << 56) );
85	// break;
86	// }
87	// case 4 :
88	// {
89	// x = ((((x>>24)&0xff) << 0) \|
90	// (((x>>16)&0xff) << 8) \|
91	// (((x>> 8)&0xff) << 16) \|
92	// (((x>> 0)&0xff) << 24) \|
93	// (((x>>56)&0xff) << 32) \|
94	// (((x>>48)&0xff) << 40) \|
95	// (((x>>40)&0xff) << 48) \|
96	// (((x>>32)&0xff) << 56) );
97	// break;
98	// }
99	// case 8 :
100	// {
101	// x = ((((x>>56)&0xff) << 0) \|
102	// (((x>>48)&0xff) << 8) \|
103	// (((x>>40)&0xff) << 16) \|
104	// (((x>>32)&0xff) << 24) \|
105	// (((x>>24)&0xff) << 32) \|
106	// (((x>>16)&0xff) << 40) \|
107	// (((x>> 8)&0xff) << 48) \|
108	// (((x>> 0)&0xff) << 56) );
109	// break;
110	// }
111	// default :
112	// {
113	// break;
114	// }
115	// }
116	// break;
117	// }
118	// default :
119	// {
120	// break;
121	// }
122	// }
123
124
125	uint64_t y=0;
126
127	for (uint32_t i=0; i<size_data; i+=size_access)
128	{
129	uint32_t offset = i<<3;
130
131	switch (size_access)
132	{
133	case 1 :
134	{
135	y = x;
136	break;
137	}
138	case 2 :
139	{
140	y \|= ((((x>>( 8+offset))&0xff) << ( 0+offset)) \|
141	(((x>>( 0+offset))&0xff) << ( 8+offset)) );
142	break;
143	}
144	case 4 :
145	{
146	y \|= ((((x>>(24+offset))&0xff) << ( 0+offset)) \|
147	(((x>>(16+offset))&0xff) << ( 8+offset)) \|
148	(((x>>( 8+offset))&0xff) << (16+offset)) \|
149	(((x>>( 0+offset))&0xff) << (24+offset)) );
150	break;
151	}
152	case 8 :
153	{
154	y \|= ((((x>>(56+offset))&0xff) << ( 0+offset)) \|
155	(((x>>(48+offset))&0xff) << ( 8+offset)) \|
156	(((x>>(40+offset))&0xff) << (16+offset)) \|
157	(((x>>(32+offset))&0xff) << (24+offset)) \|
158	(((x>>(24+offset))&0xff) << (32+offset)) \|
159	(((x>>(16+offset))&0xff) << (40+offset)) \|
160	(((x>>( 8+offset))&0xff) << (48+offset)) \|
161	(((x>>( 0+offset))&0xff) << (56+offset)) );
162	break;
163	}
164	default :
165	{
166	break;
167	}
168	}
169	}
170
171	return static_cast<T>(y);
172	}
173
174	template <typename T>
175	T swapBits (T data, uint32_t size_data, uint32_t size_access)
176	{
177	uint8_t x = static_cast<uint8_t>(data);
178
179	uint8_t y=0;
180
181	for (uint32_t i=0; i<size_data; i+=size_access)
182	{
183	uint32_t offset = i;
184
185	switch (size_access)
186	{
187	case 1 :
188	{
189	y = x;
190	break;
191	}
192	case 2 :
193	{
194	y \|= ((((x>>( 1+offset))&0x1) << ( 0+offset)) \|
195	(((x>>( 0+offset))&0x1) << ( 1+offset)) );
196	break;
197	}
198	case 4 :
199	{
200	y \|= ((((x>>( 3+offset))&0x1) << ( 0+offset)) \|
201	(((x>>( 2+offset))&0x1) << ( 1+offset)) \|
202	(((x>>( 1+offset))&0x1) << ( 2+offset)) \|
203	(((x>>( 0+offset))&0x1) << ( 3+offset)) );
204	break;
205	}
206	case 8 :
207	{
208	y \|= ((((x>>( 7+offset))&0x1) << ( 0+offset)) \|
209	(((x>>( 6+offset))&0x1) << ( 1+offset)) \|
210	(((x>>( 5+offset))&0x1) << ( 2+offset)) \|
211	(((x>>( 4+offset))&0x1) << ( 3+offset)) \|
212	(((x>>( 3+offset))&0x1) << ( 4+offset)) \|
213	(((x>>( 2+offset))&0x1) << ( 5+offset)) \|
214	(((x>>( 1+offset))&0x1) << ( 6+offset)) \|
215	(((x>>( 0+offset))&0x1) << ( 7+offset)) );
216	break;
217	}
218	default :
219	{
220	break;
221	}
222	}
223	}
224
225	return static_cast<T>(y);
226	}
227
228	#undef FUNCTION
229	#define FUNCTION "Load_store_unit::function_speculative_load_commit_transition"
230	void Load_store_unit::function_speculative_load_commit_transition (void)
231	{
232	log_begin(Load_store_unit,FUNCTION);
233	log_function(Load_store_unit,FUNCTION,_name.c_str());
234
235	if (PORT_READ(in_NRESET) == 0)
236	{
237	// Reset : clear all queue
238	_speculative_access_queue_control->clear();
239
240	reg_STORE_QUEUE_PTR_READ = 0;
241	reg_LOAD_QUEUE_CHECK_PRIORITY = 0;
242
243	for (uint32_t i=0; i< _param->_size_store_queue ; i++)
244	{
245	reg_STORE_QUEUE_NB_CHECK [i] = 0;
246	_store_queue [i]._state = STORE_QUEUE_EMPTY;
247	}
248
249	for (uint32_t i=0; i< _param->_size_load_queue ; i++)
250	_load_queue [i]._state = LOAD_QUEUE_EMPTY;
251
252	for (uint32_t i=0; i< _param->_size_speculative_access_queue; i++)
253	_speculative_access_queue [i]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY;
254	}
255	else
256	{
257	//================================================================
258	// Interface "MEMORY_OUT"
259	//================================================================
260
261	if (( internal_MEMORY_OUT_VAL == 1) and
262	(PORT_READ(in_MEMORY_OUT_ACK[0]) == 1))
263	{
264	log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_OUT[0] transaction");
265
266	switch (internal_MEMORY_OUT_SELECT_QUEUE)
267	{
268	case SELECT_STORE_QUEUE :
269	{
270	// =======================
271	// ===== STORE_QUEUE =====
272	// =======================
273
274	log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue [%d]",reg_STORE_QUEUE_PTR_READ);
275
276	// Entry flush and increase the read pointer
277	_store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_EMPTY;
278
279	reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue;
280
281	break;
282	}
283	case SELECT_LOAD_QUEUE :
284	{
285	// ======================
286	// ===== LOAD_QUEUE =====
287	// ======================
288
289	log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d]",internal_MEMORY_OUT_PTR);
290
291	// Entry flush and increase the read pointer
292
293	_load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_EMPTY;
294
295	// reg_LOAD_QUEUE_PTR_READ = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;
296
297	break;
298	}
299	case SELECT_LOAD_QUEUE_SPECULATIVE :
300	{
301	log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d] (speculative)",internal_MEMORY_OUT_PTR);
302
303	// !!! WARNING !!!
304	// !!! Test special case :
305	// !!! in a cycle an instruction can check the last store AND commit instruction
306	// !!! also the memory_out is before the port_check
307
308	_load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_CHECK;
309	// NOTE : a speculative load write in the register file.
310	// if the speculation is a miss, write_rd is re set at 1.
311	_load_queue [internal_MEMORY_OUT_PTR]._write_rd = 0;
312
313	#ifdef STATISTICS
314	if (usage_is_set(_usage,USE_STATISTICS))
315	(*_stat_nb_inst_load_commit_speculative) ++;
316	#endif
317
318	break;
319	}
320
321	break;
322	}
323	}
324
325	//================================================================
326	// Interface "PORT_CHECK"
327	//================================================================
328
329	// Plusieurs moyens de faire la verification de dépendance entre les loads et les stores.
330	// 1) un load ne peut vérifier qu'un store par cycle. Dans ce cas port_check <= size_load_queue
331	// 2) un load tente de vérifier le maximum de store par cycle. Dans ce cas ce n'est pas du pointeur d'écriture qu'il lui faut mais un vecteur de bit indiquant quel store à déjà été testé. De plus il faut un bit indiquant qu'il y a un match mais que ce n'est pas forcément le premier.
332
333	// solution 1)
334	log_printf(TRACE,Load_store_unit,FUNCTION," * CHECK");
335	for (uint32_t i=0, nb_check=0; (nb_check<_param->_nb_port_check) and (i<_param->_size_load_queue); i++)
336	{
337	// Get an index from load queue
338	uint32_t index_load = (i + reg_LOAD_QUEUE_CHECK_PRIORITY)%_param->_size_load_queue;
339
340	// Test if this load must ckecked store queue
341	if (((_load_queue[index_load]._state == LOAD_QUEUE_WAIT_CHECK) or
342	(_load_queue[index_load]._state == LOAD_QUEUE_COMMIT_CHECK) or
343	(_load_queue[index_load]._state == LOAD_QUEUE_CHECK)) and
344	is_operation_memory_load(_load_queue[index_load]._operation))
345	{
346	log_printf(TRACE,Load_store_unit,FUNCTION," * Find a load : %d",index_load);
347
348	nb_check++; // use one port
349
350	// find a entry that it need a check
351	Tlsq_ptr_t index_store = _load_queue[index_load]._store_queue_ptr_write;
352	Tlsq_ptr_t index_store_old = index_store;
353
354	// Init variable
355	bool end_check = false;
356	bool change_state = false;
357	bool next = false;
358
359	// At the first store queue empty, stop check.
360	// Explication :
361	// * rename logic keep a empty case in the store queue (also size_store_queue > 1)
362	// * when a store is out of store queue, also it was in head of re order buffer. Also, they are none previous load.
363
364	log_printf(TRACE,Load_store_unit,FUNCTION," * index_store : %d",index_store);
365	log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read : %d",reg_STORE_QUEUE_PTR_READ);
366
367	if (index_store == reg_STORE_QUEUE_PTR_READ)
368	{
369	log_printf(TRACE,Load_store_unit,FUNCTION," * index_store == reg_STORE_QUEUE_PTR_READ");
370	end_check = true;
371	change_state = true;
372	}
373	else
374	{
375	log_printf(TRACE,Load_store_unit,FUNCTION," * index_store != reg_STORE_QUEUE_PTR_READ");
376
377	index_store = (index_store-1)%(_param->_size_store_queue); // store_queue_ptr_write target the next slot to write, also the slot is not significatif when the load is renaming
378
379	log_printf(TRACE,Load_store_unit,FUNCTION," * index_store : %d",index_store);
380
381	// switch on store_queue state
382	switch (_store_queue[index_store]._state)
383	{
384	case STORE_QUEUE_VALID_NO_SPECULATIVE :
385	case STORE_QUEUE_COMMIT :
386	case STORE_QUEUE_VALID_SPECULATIVE :
387	{
388
389	log_printf(TRACE,Load_store_unit,FUNCTION," * store have a valid entry");
390
391	// TODO : MMU - nous considérons que les adresses sont physique
392	bool test_thread_id = true;
393
394	// Test thread id
395	if (_param->_have_port_context_id)
396	test_thread_id &= (_load_queue[index_load]._context_id == _store_queue[index_store]._context_id);
397	if (_param->_have_port_front_end_id)
398	test_thread_id &= (_load_queue[index_load]._front_end_id == _store_queue[index_store]._front_end_id);
399	if (_param->_have_port_ooo_engine_id)
400	test_thread_id &= (_load_queue[index_load]._ooo_engine_id == _store_queue[index_store]._ooo_engine_id);
401
402	if (test_thread_id)
403	{
404	// the load and store are in the same thread. Now, we must test address.
405
406	log_printf(TRACE,Load_store_unit,FUNCTION," * load and store is the same thread.");
407	Tdcache_address_t load_addr = _load_queue [index_load ]._address;
408	Tdcache_address_t store_addr = _store_queue[index_store]._address;
409
410	log_printf(TRACE,Load_store_unit,FUNCTION," * load_addr : %.8x.",load_addr );
411	log_printf(TRACE,Load_store_unit,FUNCTION," * store_addr : %.8x.",store_addr);
412	log_printf(TRACE,Load_store_unit,FUNCTION," * load_addr & mask_address_msb : %.8x.",load_addr & _param->_mask_address_msb);
413	log_printf(TRACE,Load_store_unit,FUNCTION," * store_addr & mask_address_msb : %.8x.",store_addr & _param->_mask_address_msb);
414	// Test if the both address target the same "word"
415	if ((load_addr & _param->_mask_address_msb) ==
416	(store_addr & _param->_mask_address_msb))
417	{
418	log_printf(TRACE,Load_store_unit,FUNCTION," * address_msb is the same.");
419	// all case - [] : store, () : load
420	// (1) store_max >= load_max and store_min <= load_min ...[...(...)...]... Ok - inclusion in store
421	// (2) store_min > load_max ...[...]...(...)... Ok - no conflit
422	// (3) store_max < load_min ...(...)...[...]... Ok - no conflit
423	// (4) store_max < load_max and store_min > load_min ...(...[...]...)... Ko - inclusion in load
424	// (5) store_max >= load_max and store_min > load_min ...[...(...]...)... Ko - conflit
425	// (6) store_max < load_max and store_min <= load_min ...(...[...)...]... Ko - conflit
426	// but :
427	// load in the cache is a word !
428	// the mask can be make when the load is commited. Also, the rdata content a full word.
429	// the only case is (4)
430
431	// Read data
432	bool is_big_endian = true;
433
434	Tgeneral_data_t load_data = _load_queue [index_load ]._rdata ;
435	Tgeneral_data_t store_data = _store_queue[index_store]._wdata ;
436	Tdcache_address_t check_hit_byte = _load_queue [index_load ]._check_hit_byte;
437	Tcontrol_t check_hit = _load_queue [index_load ]._check_hit;
438	uint32_t load_size_access = memory_size(_load_queue [index_load ]._operation)>>3;
439	uint32_t store_size_access = memory_size(_store_queue[index_store]._operation)>>3;
440
441	log_printf(TRACE,Load_store_unit,FUNCTION," * is_big_endian : %d",is_big_endian);
442	log_printf(TRACE,Load_store_unit,FUNCTION," * load_data : 0x%.8x",load_data);
443	log_printf(TRACE,Load_store_unit,FUNCTION," * store_data : 0x%.8x",store_data);
444	log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",check_hit_byte);
445	log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %d",check_hit);
446
447	log_printf(TRACE,Load_store_unit,FUNCTION," * load_size_access : %d",load_size_access );
448	log_printf(TRACE,Load_store_unit,FUNCTION," * store_size_access : %d",store_size_access);
449
450	if (is_big_endian)
451	{
452	// swap in little endian
453	load_data = swapBytes<Tgeneral_data_t >(load_data , _param->_size_general_data>>3,load_size_access);
454	store_data = swapBytes<Tgeneral_data_t >(store_data , _param->_size_general_data>>3,store_size_access);
455	check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access);
456
457
458	log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (swap 1) : 0x%.8x",load_data);
459	log_printf(TRACE,Load_store_unit,FUNCTION," * store_data (swap 1) : 0x%.8x",store_data);
460	log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte (swap 1) : %x",check_hit_byte);
461	}
462
463	uint32_t store_nb_byte = (1<<memory_access(_store_queue[index_store]._operation));
464
465	// Take interval to the store
466	uint32_t store_num_byte_min = (store_addr & _param->_mask_address_lsb);
467	uint32_t store_num_byte_max = store_num_byte_min+store_nb_byte;
468
469	log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_min : %d",store_num_byte_min);
470	log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_max : %d",store_num_byte_max);
471
472	// uint32_t load_nb_byte = (1<<memory_access(_load_queue[index_load]._operation));
473
474	// uint32_t load_num_byte_min = (load_addr & _param->_mask_address_lsb);
475	// uint32_t load_num_byte_max = load_num_byte_min+load_nb_byte;
476
477	// log_printf(TRACE,Load_store_unit,FUNCTION," * load_num_byte_min : %d",load_num_byte_min);
478	// log_printf(TRACE,Load_store_unit,FUNCTION," * load_num_byte_max : %d",load_num_byte_max);
479
480	// for (uint32_t num_load_byte=load_num_byte_min; num_load_byte<load_num_byte_max; num_load_byte ++)
481	// {
482	// // Make a mask
483	// uint32_t num_store_byte = num_load_byte;
484
485
486
487	// The bypass is checked byte per byte
488	// Is same endianness : because to change endianness, we must write in special register. Also the pipeline is flushed.
489	for (uint32_t num_store_byte=store_num_byte_min; num_store_byte<store_num_byte_max; num_store_byte ++)
490	{
491	// Make a mask
492	uint32_t num_load_byte = num_store_byte;
493
494	// if (is_big_endian)
495	// {
496	// // sd 0 : 0 1 2 3 4 5 6 7
497	// // ld 0 : 0 1 2 3 4 5 6 7 >> 0
498	// // lw 0 : 0 1 2 3 >> 0 -4
499	// // lw 4 : 4 5 6 7 >> 32 +4
500	// // lh 0 : 0 1 >> 0 -6
501	// // lh 2 : 2 3 >> 16 -2
502	// // lh 4 : 4 5 >> 32 +2
503	// // lh 6 : 6 7 >> 48 +6
504	// // lb 0 : 0 >> 0 -7
505	// // lb 1 : 1 >> 8 -5
506	// // lb 2 : 2 >> 16 -3
507	// // lb 3 : 3 >> 24 -1
508	// // lb 4 : 4 >> 32 +1
509	// // lb 5 : 5 >> 40 +3
510	// // lb 6 : 6 >> 48 +5
511	// // lb 7 : 7 >> 56 +7
512
513	// // diff : (store_nb_byte + load_nb_byte) - 2nb_load_byte((num_store_byte+1)
514
515	// // store duplicate = all store access can be see as full size_data store
516	// // uint32_t load_nb_byte = (1<<memory_access(_load_queue [index_load ]._operation));
517
518	// // int32_t diff = ((_param->_size_general_data>>3)+load_nb_byte-2load_nb_byte((num_store_byte/load_nb_byte)+1));
519
520	// // num_load_byte =num_store_byte+diff;
521
522	// // log_printf(TRACE,Load_store_unit,FUNCTION," * load_nb_byte : %d",load_nb_byte);
523	// // log_printf(TRACE,Load_store_unit,FUNCTION," * diff : %d",diff);
524
525
526	// num_load_byte = num_store_byte;
527	// }
528	// else
529	// {
530	// // sd 0 : 0 1 2 3 4 5 6 7
531	// // ld 0 : 0 1 2 3 4 5 6 7 >> 0
532	// // lw 0 : 4 5 6 7 >> 0
533	// // lw 4 : 0 1 2 3 >> 32
534	// // lh 0 : 6 7 >> 0
535	// // lh 2 : 4 5 >> 16
536	// // lh 4 : 2 3 >> 32
537	// // lh 6 : 0 1 >> 48
538	// // lb 0 : 7 >> 0
539	// // lb 1 : 6 >> 8
540	// // lb 2 : 5 >> 16
541	// // lb 3 : 4 >> 24
542	// // lb 4 : 3 >> 32
543	// // lb 5 : 2 >> 40
544	// // lb 6 : 1 >> 48
545	// // lb 7 : 0 >> 56
546
547	// num_load_byte = num_store_byte;
548	// }
549
550	uint32_t mask = 1<<num_load_byte;
551
552	log_printf(TRACE,Load_store_unit,FUNCTION," * num_store_byte : %d",num_store_byte);
553	log_printf(TRACE,Load_store_unit,FUNCTION," * num_load_byte : %d",num_load_byte);
554	log_printf(TRACE,Load_store_unit,FUNCTION," * mask : %d",mask);
555
556	// Accept the bypass if :
557	// * they have not a previous bypass with an another store
558	// * it's a valid request of load
559	if ((check_hit_byte&mask)==0)
560	{
561	// Note : Store is duplicate = all store access can be see as full size_data store
562
563	uint32_t num_store_bit_min = num_store_byte<<3; //*8
564	// uint32_t num_store_bit_max = num_store_bit_min+8-1;
565	uint32_t num_load_bit_min = num_load_byte <<3; //*8
566	uint32_t num_load_bit_max = num_load_bit_min+8-1;
567
568	log_printf(TRACE,Load_store_unit,FUNCTION," * bypass !!!");
569	// log_printf(TRACE,Load_store_unit,FUNCTION," * interval store : [%d:%d]",num_store_bit_max,num_store_bit_min);
570	log_printf(TRACE,Load_store_unit,FUNCTION," * interval store : [..:%d]",num_store_bit_min);
571	log_printf(TRACE,Load_store_unit,FUNCTION," * interval load : [%d:%d]",num_load_bit_max,num_load_bit_min);
572	log_printf(TRACE,Load_store_unit,FUNCTION," * rdata_old : 0x%.8x", load_data);
573
574	load_data = ((((store_data>>num_store_bit_min) & 0xff) << num_load_bit_min) \|
575	mask_not<Tdcache_data_t>(load_data,num_load_bit_max,num_load_bit_min));
576
577	check_hit_byte \|= mask;
578	check_hit = 1;
579	change_state = true;
580
581	log_printf(TRACE,Load_store_unit,FUNCTION," * rdata_new : 0x%.8x", load_data);
582	}
583	}
584
585	if (is_big_endian)
586	{
587	// swap in little endian
588	load_data = swapBytes<Tgeneral_data_t >(load_data , _param->_size_general_data>>3,load_size_access);
589	check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access);
590
591
592	log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (swap 2) : 0x%.8x",load_data);
593	log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte (swap 2) : %x",check_hit_byte);
594	}
595
596	_load_queue[index_load]._rdata = load_data;
597	_load_queue[index_load]._check_hit_byte = check_hit_byte;
598	_load_queue[index_load]._check_hit = check_hit;
599
600	log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (after) : 0x%.8x",load_data);
601
602	log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %x",check_hit);
603	log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",check_hit_byte);
604
605	log_printf(TRACE,Load_store_unit,FUNCTION," * mask_end_check : %x",(-1& _param->_mask_address_lsb));
606	log_printf(TRACE,Load_store_unit,FUNCTION," * mask_check_hit_byte: %x",_param->_mask_check_hit_byte);
607	// The check is finish if all bit is set
608	end_check = (_load_queue[index_load]._check_hit_byte == _param->_mask_check_hit_byte);
609
610	}
611	}
612
613	next = true;
614	break;
615	}
616	case STORE_QUEUE_EMPTY :
617	case STORE_QUEUE_NO_VALID_NO_SPECULATIVE :
618	{
619	log_printf(TRACE,Load_store_unit,FUNCTION," * store have an invalid entry");
620	break;
621	}
622	}
623	}
624
625	if (next)
626	{
627	log_printf(TRACE,Load_store_unit,FUNCTION," * next");
628	log_printf(TRACE,Load_store_unit,FUNCTION," * new store_queue_ptr_write : %d",index_store);
629
630	log_printf(TRACE,Load_store_unit,FUNCTION," * update reg_STORE_QUEUE_NB_CHECK");
631	#ifdef DEBUG
632	if (reg_STORE_QUEUE_NB_CHECK [index_store] == 0)
633	throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
634	#endif
635	reg_STORE_QUEUE_NB_CHECK [index_store] --;
636
637	// if (_load_queue[index_load]._store_queue_ptr_write == 0)
638	// _load_queue[index_load]._store_queue_ptr_write = _param->_size_store_queue-1;
639	// else
640	// _load_queue[index_load]._store_queue_ptr_write --;
641	_load_queue[index_load]._store_queue_ptr_write = index_store; // because the index store have be decrease
642
643	// FIXME : peut n'est pas obliger de faire cette comparaison. Au prochain cycle on le détectera que les pointeur sont égaux. Ceci évitera d'avoir deux comparateurs avec le registre "reg_STORE_QUEUE_PTR_READ"
644	if (index_store == reg_STORE_QUEUE_PTR_READ)
645	{
646	end_check = true;
647	change_state = true;
648	}
649	}
650
651	if (change_state)
652	{
653	log_printf(TRACE,Load_store_unit,FUNCTION," * change_state");
654	log_printf(TRACE,Load_store_unit,FUNCTION," * end_check : %d",end_check);
655
656	log_printf(TRACE,Load_store_unit,FUNCTION," * state old : %s",toString(_load_queue[index_load]._state).c_str());
657
658	switch (_load_queue[index_load]._state)
659	{
660	case LOAD_QUEUE_WAIT_CHECK :
661	{
662	if (end_check)
663	_load_queue[index_load]._state = LOAD_QUEUE_WAIT ;
664	break;
665	}
666	case LOAD_QUEUE_COMMIT_CHECK :
667	{
668	if (end_check)
669	_load_queue[index_load]._state = LOAD_QUEUE_COMMIT;
670	else
671	_load_queue[index_load]._state = LOAD_QUEUE_CHECK; // No commit : check hit and no end
672	break;
673	}
674	case LOAD_QUEUE_CHECK :
675	{
676	if (end_check)
677	_load_queue[index_load]._state = LOAD_QUEUE_COMMIT;
678
679	// check find a bypass. A speculative load have been committed : report a speculation miss.
680	if ((_load_queue[index_load]._check_hit != 0) and
681	(_load_queue[index_load]._write_rd == 0) // is commit
682	)
683	{
684	_load_queue[index_load]._exception = EXCEPTION_MEMORY_MISS_SPECULATION;
685	_load_queue[index_load]._write_rd = 1; // write the good result
686
687	#ifdef STATISTICS
688	if (usage_is_set(_usage,USE_STATISTICS))
689	(*_stat_nb_inst_load_commit_miss) ++;
690	#endif
691	}
692
693	break;
694	}
695	default : break;
696	}
697	log_printf(TRACE,Load_store_unit,FUNCTION," * state new : %s",toString(_load_queue[index_load]._state).c_str());
698	log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",_load_queue[index_load]._exception);
699
700	if (end_check)
701	{
702	log_printf(TRACE,Load_store_unit,FUNCTION," * end check, decrease all nb_check");
703
704	uint32_t i=index_store;
705	while (i!=reg_STORE_QUEUE_PTR_READ)
706	{
707	i=((i==0)?_param->_size_store_queue:i)-1;
708
709	#ifdef DEBUG
710	if (reg_STORE_QUEUE_NB_CHECK [i] == 0)
711	throw ERRORMORPHEO(FUNCTION,_("reg_STORE_QUEUE_NB_CHECK must be > 0\n"));
712	#endif
713
714	reg_STORE_QUEUE_NB_CHECK [i] --;
715	//i=(i+1)%_param->_size_store_queue;
716	}
717	}
718	}
719	}
720	// else : don't use a port
721	}
722
723	//================================================================
724	// Interface "MEMORY_IN"
725	//================================================================
726
727	if ((PORT_READ(in_MEMORY_IN_VAL [internal_MEMORY_IN_PORT]) == 1) and
728	( internal_MEMORY_IN_ACK == 1))
729	{
730	log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_IN [%d]",internal_MEMORY_IN_PORT);
731
732	// Test operation :
733	//~~~~~~~~~~~~~~~~~
734	// store in store_queue
735	// load in speculation_access_queue
736	// others in speculation_access_queue
737
738	#ifdef DEBUG_TEST
739	if (PORT_READ(in_MEMORY_IN_TYPE [internal_MEMORY_IN_PORT]) != TYPE_MEMORY)
740	throw ERRORMORPHEO(FUNCTION,"The type is different at 'TYPE_MEMORY'");
741	#endif
742	Toperation_t operation = PORT_READ(in_MEMORY_IN_OPERATION[internal_MEMORY_IN_PORT]);
743	Tgeneral_data_t address = (PORT_READ(in_MEMORY_IN_IMMEDIAT[internal_MEMORY_IN_PORT]) +
744	PORT_READ(in_MEMORY_IN_DATA_RA [internal_MEMORY_IN_PORT]));
745	bool exception_alignement = (mask_memory_access(operation) & address) != 0;
746
747	if (is_operation_memory_store(operation) == true)
748	{
749	// =======================
750	// ===== STORE_QUEUE =====
751	// =======================
752	// There a two store request type :
753	// - first is operation with address and data
754	// - second is the information of re order buffer : the store become not speculative and can access at the data cache
755
756	log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue");
757	log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH");
758
759	// Write pointer is define in rename stage :
760	Tlsq_ptr_t index = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
761	log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index);
762
763	// Need read : state and exception.
764	Tstore_queue_state_t old_state = _store_queue [index]._state;
765	Tstore_queue_state_t new_state = old_state;
766	bool update_info = false;
767
768	Texception_t old_exception = _store_queue [index]._exception;
769	Texception_t new_exception = old_exception;
770
771	// Compute next state
772	switch (old_state)
773	{
774	case STORE_QUEUE_EMPTY :
775	{
776	if (is_operation_memory_store_head(operation) == true)
777	{
778	new_state = STORE_QUEUE_NO_VALID_NO_SPECULATIVE;
779
780	// test if is a speculation
781	if (operation == OPERATION_MEMORY_STORE_HEAD_KO)
782	new_exception = EXCEPTION_MEMORY_MISS_SPECULATION;
783	else
784	new_exception = EXCEPTION_MEMORY_NONE;
785	}
786	else
787	{
788	new_state = STORE_QUEUE_VALID_SPECULATIVE;
789
790	// Test if have an exception
791	if (exception_alignement == true)
792	new_exception = EXCEPTION_MEMORY_ALIGNMENT;
793	else
794	new_exception = EXCEPTION_MEMORY_NONE;
795
796	update_info = true;
797	}
798	break;
799	}
800	case STORE_QUEUE_NO_VALID_NO_SPECULATIVE :
801	{
802	#ifdef DEBUG_TEST
803	if (is_operation_memory_store_head(operation) == true)
804	throw ERRORMORPHEO(FUNCTION,_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_NO_VALID_NO_SPECULATIVE\", also a previous store_head have been receiveid. But this operation is a store_head."));
805	#endif
806	// Test if have a new exception (priority : miss_speculation)
807	if ((exception_alignement == true) and (old_exception == EXCEPTION_MEMORY_NONE))
808	new_exception = EXCEPTION_MEMORY_ALIGNMENT;
809
810	if (new_exception != EXCEPTION_MEMORY_NONE)
811	new_state = STORE_QUEUE_COMMIT;
812	else
813	new_state = STORE_QUEUE_VALID_NO_SPECULATIVE;
814
815	update_info = true;
816	break;
817	}
818	case STORE_QUEUE_VALID_SPECULATIVE :
819	{
820	#ifdef DEBUG_TEST
821	if (is_operation_memory_store_head(operation) == false)
822	throw ERRORMORPHEO(FUNCTION,_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_VALID_SPECULATIVE\", also a previous access with register and address have been receiveid. But this operation is a not store_head."));
823	#endif
824	if (operation == OPERATION_MEMORY_STORE_HEAD_KO)
825	new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; // great prioritary
826
827	if (new_exception != EXCEPTION_MEMORY_NONE)
828	new_state = STORE_QUEUE_COMMIT;
829	else
830	new_state = STORE_QUEUE_VALID_NO_SPECULATIVE;
831
832	break;
833	}
834	case STORE_QUEUE_VALID_NO_SPECULATIVE :
835	case STORE_QUEUE_COMMIT :
836	{
837	throw ERRORMORPHEO(FUNCTION,"<Load_store_unit::function_speculative_load_commit_transition> Invalid state and operation");
838	}
839	}
840
841	_store_queue [index]._state = new_state;
842	_store_queue [index]._exception = new_exception;
843
844	if (update_info == true)
845	{
846	log_printf(TRACE,Load_store_unit,FUNCTION," * Update information");
847
848	_store_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]);
849	_store_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]);
850	_store_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]);
851	_store_queue [index]._packet_id = (not _param->_have_port_rob_ptr )?0:PORT_READ(in_MEMORY_IN_PACKET_ID [internal_MEMORY_IN_PORT]);
852	_store_queue [index]._operation = operation;
853	_store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
854	_store_queue [index]._address = address;
855
856	// reordering data
857	_store_queue [index]._wdata = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB[internal_MEMORY_IN_PORT]), memory_size(operation), 0);
858	// _store_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD [internal_MEMORY_IN_PORT]);
859	}
860	}
861	else
862	{
863	// ====================================
864	// ===== SPECULATIVE_ACCESS_QUEUE =====
865	// ====================================
866
867	// In speculative access queue, they are many type's request
868	log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue");
869	log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH");
870
871	// Write in reservation station
872	uint32_t index = _speculative_access_queue_control->push();
873
874	log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d", index);
875
876	Texception_t exception;
877
878	if (exception_alignement == true)
879	exception = EXCEPTION_MEMORY_ALIGNMENT;
880	else
881	exception = EXCEPTION_MEMORY_NONE;
882
883	// if exception, don't access at the cache
884	// NOTE : type "other" (lock, invalidate, flush and sync) can't make an alignement exception (access is equivalent at a 8 bits)
885	_speculative_access_queue [index]._state = (exception == EXCEPTION_MEMORY_NONE)?SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE:SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE;
886	_speculative_access_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]);
887	_speculative_access_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]);
888	_speculative_access_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]);
889	_speculative_access_queue [index]._packet_id = (not _param->_have_port_rob_ptr )?0:PORT_READ(in_MEMORY_IN_PACKET_ID [internal_MEMORY_IN_PORT]);
890
891	_speculative_access_queue [index]._operation = operation;
892	_speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
893	_speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
894	_speculative_access_queue [index]._address = address;
895	// NOTE : is operation is a load, then they are a result and must write in the register file
896	_speculative_access_queue [index]._write_rd = is_operation_memory_load(operation);
897	_speculative_access_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD [internal_MEMORY_IN_PORT]);
898
899	_speculative_access_queue [index]._exception = exception;
900
901	log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index);
902	}
903	}
904
905	//================================================================
906	// Interface "DCACHE_REQ"
907	//================================================================
908	bool load_queue_push = (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE);
909
910	if (( internal_DCACHE_REQ_VAL == 1) and
911	(PORT_READ(in_DCACHE_REQ_ACK[0]) == 1))
912	{
913	log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_REQ [0]");
914
915	switch (internal_DCACHE_REQ_SELECT_QUEUE)
916	{
917	case SELECT_STORE_QUEUE :
918	{
919	// =======================
920	// ===== STORE_QUEUE =====
921	// =======================
922
923	// Entry flush and increase the read pointer
924
925	_store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_COMMIT;
926
927	break;
928	}
929	case SELECT_LOAD_QUEUE_SPECULATIVE :
930	{
931	// =========================================
932	// ===== SELECT_LOAD_QUEUE_SPECULATIVE =====
933	// =========================================
934
935	load_queue_push = true;
936	break;
937	}
938	case SELECT_LOAD_QUEUE :
939	{
940	throw ERRORMORPHEO(FUNCTION,_("Invalid selection"));
941	break;
942	}
943
944	break;
945	}
946	}
947
948	if (load_queue_push)
949	{
950	Tlsq_ptr_t ptr_write = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write;
951	Toperation_t operation = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation;
952	Texception_t exception = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._exception;
953	bool have_exception = (exception != EXCEPTION_MEMORY_NONE);
954
955	if (have_exception)
956	_load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT;
957	else
958	{
959	if (have_dcache_rsp(operation))
960	{
961	// load and synchronisation
962	if (must_check(operation))
963	{
964	// load
965	_load_queue [ptr_write]._state = LOAD_QUEUE_WAIT_CHECK;
966	}
967	else
968	{
969	// synchronisation
970	_load_queue [ptr_write]._state = LOAD_QUEUE_WAIT;
971	}
972	}
973	else
974	{
975	// lock, prefecth, flush and invalidate
976	_load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT;
977	}
978	}
979
980	Tdcache_address_t address = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;
981	Tdcache_address_t address_lsb = (address & _param->_mask_address_lsb);
982	Tdcache_address_t check_hit_byte = gen_mask_not<Tdcache_address_t>(address_lsb+(memory_size(operation)>>3)-1,address_lsb) & _param->_mask_check_hit_byte;
983	Tlsq_ptr_t store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write;
984
985	log_printf(TRACE,Load_store_unit,FUNCTION," * address : 0x%.8x", address);
986	log_printf(TRACE,Load_store_unit,FUNCTION," * address_lsb : 0x%.8x", address_lsb);
987	log_printf(TRACE,Load_store_unit,FUNCTION," * operation : %d", operation);
988	log_printf(TRACE,Load_store_unit,FUNCTION," * memory_size : %d", memory_size(operation));
989	log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : 0x%x", check_hit_byte);
990
991	_load_queue [ptr_write]._context_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id;
992	_load_queue [ptr_write]._front_end_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id;
993	_load_queue [ptr_write]._ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id;
994	_load_queue [ptr_write]._packet_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._packet_id;
995	_load_queue [ptr_write]._operation = operation;
996	_load_queue [ptr_write]._store_queue_ptr_write = store_queue_ptr_write;
997	_load_queue [ptr_write]._address = address;
998	_load_queue [ptr_write]._check_hit_byte = check_hit_byte;
999	_load_queue [ptr_write]._check_hit = 0;
1000	_load_queue [ptr_write]._shift = address_lsb<<3;// *8
1001	_load_queue [ptr_write]._is_load_signed = is_operation_memory_load_signed(operation);
1002	_load_queue [ptr_write]._access_size = memory_size(operation);
1003	// NOTE : if have an exception, must write in register, because a depend instruction wait the load data.
1004	_load_queue [ptr_write]._write_rd = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._write_rd ;
1005	_load_queue [ptr_write]._num_reg_rd = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._num_reg_rd ;
1006	_load_queue [ptr_write]._exception = exception;
1007	_load_queue [ptr_write]._rdata = address; // to the exception
1008
1009	log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue");
1010	log_printf(TRACE,Load_store_unit,FUNCTION," * POP[%d]",(*_speculative_access_queue_control)[0]);
1011
1012	_speculative_access_queue [(*_speculative_access_queue_control)[0]]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY;
1013
1014	_speculative_access_queue_control->pop();
1015
1016	#ifdef STATISTICS
1017	if (usage_is_set(_usage,USE_STATISTICS))
1018	(*_stat_nb_inst_load) ++;
1019	#endif
1020
1021	// Only load need check
1022	if (is_operation_memory_load(_load_queue [ptr_write]._operation))
1023	{
1024	log_printf(TRACE,Load_store_unit,FUNCTION," * update nb_check");
1025	log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue_ptr_write : %d",store_queue_ptr_write);
1026	log_printf(TRACE,Load_store_unit,FUNCTION," * reg_STORE_QUEUE_PTR_READ : %d",reg_STORE_QUEUE_PTR_READ);
1027
1028	uint32_t i=store_queue_ptr_write;
1029	while (i!=reg_STORE_QUEUE_PTR_READ)
1030	{
1031	i=((i==0)?_param->_size_store_queue:i)-1;
1032
1033	log_printf(TRACE,Load_store_unit,FUNCTION," * i : %d",i);
1034
1035	reg_STORE_QUEUE_NB_CHECK [i] ++;
1036	}
1037	}
1038	}
1039
1040	//================================================================
1041	// Interface "DCACHE_RSP"
1042	//================================================================
1043	if ((PORT_READ(in_DCACHE_RSP_VAL[0])== 1) and
1044	( internal_DCACHE_RSP_ACK == 1))
1045	{
1046	log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_RSP [0]");
1047
1048	// don't use context_id : because there are one queue for all thread
1049	//Tcontext_t context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID[0]);
1050	Tpacket_t packet_id = PORT_READ(in_DCACHE_RSP_PACKET_ID [0]);
1051	Tdcache_data_t rdata = PORT_READ(in_DCACHE_RSP_RDATA [0]);
1052	Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR [0]);
1053
1054	log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d" , packet_id);
1055	log_printf(TRACE,Load_store_unit,FUNCTION," * packet_id : %d" , packet_id>>1);
1056	log_printf(TRACE,Load_store_unit,FUNCTION," * rdata : %.8x", rdata);
1057	log_printf(TRACE,Load_store_unit,FUNCTION," * error : %d" , error);
1058
1059	if (DCACHE_RSP_IS_LOAD(packet_id) == 1)
1060	{
1061	packet_id >>= 1;
1062
1063	log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a LOAD");
1064
1065	#ifdef DEBUG_TEST
1066	if (not have_dcache_rsp(_load_queue [packet_id]._operation))
1067	throw ERRORMORPHEO(FUNCTION,_("Receive of respons, but the corresponding operation don't wait a respons."));
1068	#endif
1069
1070	Tdcache_data_t data = _load_queue [packet_id]._rdata;
1071
1072	log_printf(TRACE,Load_store_unit,FUNCTION," * data construction");
1073	log_printf(TRACE,Load_store_unit,FUNCTION," * data from cache : 0x%.8x",rdata);
1074	log_printf(TRACE,Load_store_unit,FUNCTION," * data (before) : 0x%.8x", data);
1075	log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : 0x%x" ,_load_queue [packet_id]._check_hit_byte);
1076	for (uint32_t i=0;i<(_param->_size_general_data>>3)/8/; ++i)
1077	// Test if this byte has been checked
1078	if ((_load_queue [packet_id]._check_hit_byte & (1<<i)) == 0)
1079	{
1080	log_printf(TRACE,Load_store_unit,FUNCTION," * no previous check ]%d:%d]",(i+1)<<3,i<<3);
1081	data = insert<Tdcache_data_t>(data,rdata,((i+1)<<3)-1,i<<3);
1082	}
1083	log_printf(TRACE,Load_store_unit,FUNCTION," * data (after) : 0x%.8x", data);
1084
1085	_load_queue [packet_id]._rdata = data;
1086
1087	if (error != DCACHE_ERROR_NONE)
1088	{
1089	log_printf(TRACE,Load_store_unit,FUNCTION," * have a bus error !!!");
1090
1091	_load_queue [packet_id]._exception = EXCEPTION_MEMORY_BUS_ERROR;
1092	_load_queue [packet_id]._state = LOAD_QUEUE_COMMIT;
1093	}
1094	else
1095	{
1096	log_printf(TRACE,Load_store_unit,FUNCTION," * have no bus error.");
1097	log_printf(TRACE,Load_store_unit,FUNCTION," * previous state : %s",toString(_load_queue [packet_id]._state).c_str());
1098
1099	// FIXME : convention : if bus error, the cache return the fautive address !
1100	// But, the load's address is aligned !
1101
1102	switch (_load_queue [packet_id]._state)
1103	{
1104	case LOAD_QUEUE_WAIT_CHECK : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT_CHECK; break;
1105	case LOAD_QUEUE_WAIT : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT ; break;
1106	default : throw ERRORMORPHEO(FUNCTION,_("Illegal state (dcache_rsp).")); break;
1107	}
1108	}
1109	}
1110	else
1111	{
1112	log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a STORE");
1113
1114	// TODO : les stores ne génére pas de réponse sauf quand c'est un bus error !!!
1115	throw ERRORMORPHEO(FUNCTION,_("dcache_rsp : no respons to a write. (TODO : manage bus error to the store operation.)"));
1116	}
1117
1118	}
1119
1120	// this register is to manage the priority of check -> Round robin
1121	reg_LOAD_QUEUE_CHECK_PRIORITY = (reg_LOAD_QUEUE_CHECK_PRIORITY+1)%_param->_size_load_queue;
1122
1123
1124	#if defined(DEBUG) and (DEBUG>=DEBUG_TRACE)
1125	// ***** dump store queue
1126	log_printf(TRACE,Load_store_unit,FUNCTION," * Dump STORE_QUEUE");
1127	log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read : %d",reg_STORE_QUEUE_PTR_READ);
1128
1129	for (uint32_t i=0; i<_param->_size_store_queue; i++)
1130	{
1131	uint32_t j = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue;
1132
1133	log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.8x, %.2d, %.2d %s",
1134	j,
1135	_store_queue[j]._context_id ,
1136	_store_queue[j]._front_end_id ,
1137	_store_queue[j]._ooo_engine_id ,
1138	_store_queue[j]._packet_id ,
1139	_store_queue[j]._operation ,
1140	_store_queue[j]._load_queue_ptr_write,
1141	_store_queue[j]._address ,
1142	_store_queue[j]._wdata ,
1143	//_store_queue[j]._write_rd ,
1144	//_store_queue[j]._num_reg_rd ,
1145	_store_queue[j]._exception ,
1146	reg_STORE_QUEUE_NB_CHECK [j] ,
1147	toString(_store_queue[j]._state).c_str());
1148	}
1149
1150	// ***** dump speculative_access queue
1151	log_printf(TRACE,Load_store_unit,FUNCTION," * Dump SPECULATIVE_ACCESS_QUEUE");
1152
1153	for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++)
1154	{
1155	uint32_t j = (*_speculative_access_queue_control)[i];
1156
1157	log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %.4d, %.2d, %s",
1158	j,
1159	_speculative_access_queue[j]._context_id ,
1160	_speculative_access_queue[j]._front_end_id ,
1161	_speculative_access_queue[j]._ooo_engine_id ,
1162	_speculative_access_queue[j]._packet_id ,
1163	_speculative_access_queue[j]._operation ,
1164	_speculative_access_queue[j]._load_queue_ptr_write,
1165	_speculative_access_queue[j]._store_queue_ptr_write,
1166	_speculative_access_queue[j]._address ,
1167	_speculative_access_queue[j]._write_rd ,
1168	_speculative_access_queue[j]._num_reg_rd ,
1169	_speculative_access_queue[j]._exception ,
1170	toString(_speculative_access_queue[j]._state).c_str());
1171	}
1172
1173	// ***** dump load queue
1174	log_printf(TRACE,Load_store_unit,FUNCTION," * Dump LOAD_QUEUE");
1175	log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read_check_priority : %d",reg_LOAD_QUEUE_CHECK_PRIORITY);
1176
1177	for (uint32_t i=0; i<_param->_size_load_queue; i++)
1178	{
1179	uint32_t j = i;
1180
1181	log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.4d, %.2d, %s",
1182	j,
1183	_load_queue[j]._context_id ,
1184	_load_queue[j]._front_end_id ,
1185	_load_queue[j]._ooo_engine_id ,
1186	_load_queue[j]._packet_id ,
1187	_load_queue[j]._operation ,
1188	_load_queue[j]._store_queue_ptr_write,
1189	_load_queue[j]._address ,
1190	_load_queue[j]._check_hit_byte ,
1191	_load_queue[j]._check_hit ,
1192	_load_queue[j]._shift ,
1193	_load_queue[j]._is_load_signed ,
1194	_load_queue[j]._access_size ,
1195	_load_queue[j]._rdata ,
1196	_load_queue[j]._write_rd ,
1197	_load_queue[j]._num_reg_rd ,
1198	_load_queue[j]._exception ,
1199	toString(_load_queue[j]._state).c_str());
1200	}
1201	#endif
1202
1203	#ifdef STATISTICS
1204	if (usage_is_set(_usage,USE_STATISTICS))
1205	{
1206	for (uint32_t i=0; i<_param->_size_store_queue; i++)
1207	if (_store_queue[i]._state != STORE_QUEUE_EMPTY)
1208	(*_stat_use_store_queue) ++;
1209	for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++)
1210	if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY)
1211	(*_stat_use_speculative_access_queue) ++;
1212	for (uint32_t i=0; i<_param->_size_load_queue; i++)
1213	if (_load_queue[i]._state != LOAD_QUEUE_EMPTY)
1214	(*_stat_use_load_queue) ++;
1215	}
1216	#endif
1217	}
1218
1219	log_end(Load_store_unit,FUNCTION);
1220	};
1221
1222	}; // end namespace load_store_unit
1223	}; // end namespace execute_unit
1224	}; // end namespace multi_execute_unit
1225	}; // end namespace execute_loop
1226	}; // end namespace multi_execute_loop
1227	}; // end namespace core
1228
1229	}; // end namespace behavioural
1230	}; // end namespace morpheo
1231	#endif

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