1 | /* |
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2 | * $Id$ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | * Test |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/include/test.h" |
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10 | #include "Common/include/Test.h" |
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11 | #include "Common/include/BitManipulation.h" |
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12 | |
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13 | #define NB_ITERATION 2 |
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14 | #define CYCLE_MAX (2048*NB_ITERATION) |
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15 | |
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16 | #define LABEL(str) \ |
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17 | { \ |
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18 | cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \ |
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19 | } while(0) |
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20 | |
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21 | static uint32_t cycle = 0; |
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22 | |
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23 | #define SC_START(cycle_offset) \ |
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24 | do \ |
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25 | { \ |
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26 | /*cout << "SC_START (begin)" << endl;*/ \ |
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27 | \ |
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28 | uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \ |
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29 | sc_start(cycle_offset); \ |
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30 | if (cycle_current != cycle) \ |
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31 | { \ |
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32 | cycle = cycle_current; \ |
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33 | cout << "##########[ cycle "<< cycle << " ]" << endl; \ |
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34 | } \ |
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35 | \ |
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36 | if (cycle_current > CYCLE_MAX) \ |
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37 | { \ |
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38 | TEST_KO("Maximal cycles Reached"); \ |
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39 | } \ |
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40 | /*cout << "SC_START (end )" << endl;*/ \ |
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41 | } while(0) |
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42 | |
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43 | void test (string name, |
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44 | morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::reservation_station::Parameters * _param) |
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45 | { |
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46 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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47 | |
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48 | #ifdef STATISTICS |
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49 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); |
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50 | #endif |
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51 | |
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52 | Reservation_station * _Reservation_station = new Reservation_station (name.c_str(), |
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53 | #ifdef STATISTICS |
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54 | _parameters_statistics, |
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55 | #endif |
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56 | _param); |
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57 | |
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58 | #ifdef SYSTEMC |
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59 | /********************************************************************* |
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60 | * Déclarations des signaux |
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61 | *********************************************************************/ |
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62 | string rename = ""; |
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63 | |
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64 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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65 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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66 | |
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67 | sc_signal<Tcontrol_t > * in_INSERT_VAL = new sc_signal<Tcontrol_t >; |
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68 | sc_signal<Tcontrol_t > * out_INSERT_ACK = new sc_signal<Tcontrol_t >; |
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69 | sc_signal<Tcontext_t > * in_INSERT_CONTEXT_ID = new sc_signal<Tcontext_t >; |
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70 | sc_signal<Tcontext_t > * in_INSERT_FRONT_END_ID = new sc_signal<Tcontext_t >; |
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71 | sc_signal<Tcontext_t > * in_INSERT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >; |
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72 | sc_signal<Tpacket_t > * in_INSERT_ROB_ID = new sc_signal<Tpacket_t >; |
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73 | sc_signal<Toperation_t > * in_INSERT_OPERATION = new sc_signal<Toperation_t >; |
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74 | sc_signal<Ttype_t > * in_INSERT_TYPE = new sc_signal<Ttype_t >; |
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75 | sc_signal<Tlsq_ptr_t > * in_INSERT_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t>; |
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76 | sc_signal<Tlsq_ptr_t > * in_INSERT_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t>; |
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77 | sc_signal<Tcontrol_t > * in_INSERT_HAS_IMMEDIAT = new sc_signal<Tcontrol_t >; |
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78 | sc_signal<Tgeneral_data_t > * in_INSERT_IMMEDIAT = new sc_signal<Tgeneral_data_t >; |
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79 | //sc_signal<Tcontrol_t > * in_INSERT_READ_RA = new sc_signal<Tcontrol_t >; |
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80 | sc_signal<Tgeneral_address_t> * in_INSERT_NUM_REG_RA = new sc_signal<Tgeneral_address_t>; |
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81 | sc_signal<Tcontrol_t > * in_INSERT_DATA_RA_VAL = new sc_signal<Tcontrol_t >; |
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82 | sc_signal<Tgeneral_data_t > * in_INSERT_DATA_RA = new sc_signal<Tgeneral_data_t >; |
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83 | //sc_signal<Tcontrol_t > * in_INSERT_READ_RB = new sc_signal<Tcontrol_t >; |
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84 | sc_signal<Tgeneral_address_t> * in_INSERT_NUM_REG_RB = new sc_signal<Tgeneral_address_t>; |
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85 | sc_signal<Tcontrol_t > * in_INSERT_DATA_RB_VAL = new sc_signal<Tcontrol_t >; |
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86 | sc_signal<Tgeneral_data_t > * in_INSERT_DATA_RB = new sc_signal<Tgeneral_data_t >; |
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87 | //sc_signal<Tcontrol_t > * in_INSERT_READ_RC = new sc_signal<Tcontrol_t >; |
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88 | sc_signal<Tspecial_address_t> * in_INSERT_NUM_REG_RC = new sc_signal<Tspecial_address_t>; |
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89 | sc_signal<Tcontrol_t > * in_INSERT_DATA_RC_VAL = new sc_signal<Tcontrol_t >; |
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90 | sc_signal<Tspecial_data_t > * in_INSERT_DATA_RC = new sc_signal<Tspecial_data_t >; |
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91 | sc_signal<Tcontrol_t > * in_INSERT_WRITE_RD = new sc_signal<Tcontrol_t >; |
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92 | sc_signal<Tgeneral_address_t> * in_INSERT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>; |
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93 | sc_signal<Tcontrol_t > * in_INSERT_WRITE_RE = new sc_signal<Tcontrol_t >; |
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94 | sc_signal<Tspecial_address_t> * in_INSERT_NUM_REG_RE = new sc_signal<Tspecial_address_t>; |
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95 | |
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96 | sc_signal<Tcontrol_t > ** out_RETIRE_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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97 | sc_signal<Tcontrol_t > ** in_RETIRE_ACK = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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98 | sc_signal<Tcontext_t > ** out_RETIRE_CONTEXT_ID = new sc_signal<Tcontext_t > * [_param->_nb_inst_retire]; |
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99 | sc_signal<Tcontext_t > ** out_RETIRE_FRONT_END_ID = new sc_signal<Tcontext_t > * [_param->_nb_inst_retire]; |
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100 | sc_signal<Tcontext_t > ** out_RETIRE_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_inst_retire]; |
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101 | sc_signal<Tpacket_t > ** out_RETIRE_ROB_ID = new sc_signal<Tpacket_t > * [_param->_nb_inst_retire]; |
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102 | sc_signal<Toperation_t > ** out_RETIRE_OPERATION = new sc_signal<Toperation_t > * [_param->_nb_inst_retire]; |
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103 | sc_signal<Ttype_t > ** out_RETIRE_TYPE = new sc_signal<Ttype_t > * [_param->_nb_inst_retire]; |
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104 | sc_signal<Tlsq_ptr_t > ** out_RETIRE_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t> * [_param->_nb_inst_retire]; |
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105 | sc_signal<Tlsq_ptr_t > ** out_RETIRE_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t> * [_param->_nb_inst_retire]; |
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106 | sc_signal<Tcontrol_t > ** out_RETIRE_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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107 | sc_signal<Tgeneral_data_t > ** out_RETIRE_IMMEDIAT = new sc_signal<Tgeneral_data_t > * [_param->_nb_inst_retire]; |
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108 | sc_signal<Tgeneral_data_t > ** out_RETIRE_DATA_RA = new sc_signal<Tgeneral_data_t > * [_param->_nb_inst_retire]; |
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109 | sc_signal<Tgeneral_data_t > ** out_RETIRE_DATA_RB = new sc_signal<Tgeneral_data_t > * [_param->_nb_inst_retire]; |
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110 | sc_signal<Tspecial_data_t > ** out_RETIRE_DATA_RC = new sc_signal<Tspecial_data_t > * [_param->_nb_inst_retire]; |
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111 | sc_signal<Tcontrol_t > ** out_RETIRE_WRITE_RD = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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112 | sc_signal<Tgeneral_address_t> ** out_RETIRE_NUM_REG_RD = new sc_signal<Tgeneral_address_t> * [_param->_nb_inst_retire]; |
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113 | sc_signal<Tcontrol_t > ** out_RETIRE_WRITE_RE = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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114 | sc_signal<Tspecial_address_t> ** out_RETIRE_NUM_REG_RE = new sc_signal<Tspecial_address_t> * [_param->_nb_inst_retire]; |
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115 | |
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116 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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117 | { |
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118 | out_RETIRE_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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119 | in_RETIRE_ACK [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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120 | out_RETIRE_CONTEXT_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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121 | out_RETIRE_FRONT_END_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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122 | out_RETIRE_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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123 | out_RETIRE_ROB_ID [i] = new sc_signal<Tpacket_t > (rename.c_str()); |
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124 | out_RETIRE_OPERATION [i] = new sc_signal<Toperation_t > (rename.c_str()); |
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125 | out_RETIRE_TYPE [i] = new sc_signal<Ttype_t > (rename.c_str()); |
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126 | out_RETIRE_STORE_QUEUE_PTR_WRITE [i] = new sc_signal<Tlsq_ptr_t> (rename.c_str()); |
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127 | out_RETIRE_LOAD_QUEUE_PTR_WRITE [i] = new sc_signal<Tlsq_ptr_t> (rename.c_str()); |
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128 | out_RETIRE_HAS_IMMEDIAT [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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129 | out_RETIRE_IMMEDIAT [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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130 | out_RETIRE_DATA_RA [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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131 | out_RETIRE_DATA_RB [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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132 | out_RETIRE_DATA_RC [i] = new sc_signal<Tspecial_data_t > (rename.c_str()); |
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133 | out_RETIRE_WRITE_RD [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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134 | out_RETIRE_NUM_REG_RD [i] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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135 | out_RETIRE_WRITE_RE [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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136 | out_RETIRE_NUM_REG_RE [i] = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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137 | } |
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138 | |
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139 | sc_signal<Tcontrol_t > ** in_GPR_WRITE_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_gpr_write]; |
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140 | sc_signal<Tcontext_t > ** in_GPR_WRITE_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_gpr_write]; |
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141 | sc_signal<Tgeneral_address_t> ** in_GPR_WRITE_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_gpr_write]; |
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142 | sc_signal<Tgeneral_data_t > ** in_GPR_WRITE_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_gpr_write]; |
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143 | |
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144 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
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145 | { |
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146 | in_GPR_WRITE_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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147 | in_GPR_WRITE_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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148 | in_GPR_WRITE_NUM_REG [i] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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149 | in_GPR_WRITE_DATA [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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150 | } |
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151 | |
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152 | sc_signal<Tcontrol_t > ** in_SPR_WRITE_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_spr_write]; |
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153 | sc_signal<Tcontext_t > ** in_SPR_WRITE_OOO_ENGINE_ID= new sc_signal<Tcontext_t > * [_param->_nb_spr_write]; |
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154 | sc_signal<Tspecial_address_t> ** in_SPR_WRITE_NUM_REG = new sc_signal<Tspecial_address_t> * [_param->_nb_spr_write]; |
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155 | sc_signal<Tspecial_data_t > ** in_SPR_WRITE_DATA = new sc_signal<Tspecial_data_t > * [_param->_nb_spr_write]; |
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156 | |
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157 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
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158 | { |
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159 | in_SPR_WRITE_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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160 | in_SPR_WRITE_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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161 | in_SPR_WRITE_NUM_REG [i] = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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162 | in_SPR_WRITE_DATA [i] = new sc_signal<Tspecial_data_t > (rename.c_str()); |
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163 | } |
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164 | |
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165 | sc_signal<Tcontext_t > ** in_BYPASS_WRITE_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_write]; |
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166 | sc_signal<Tcontrol_t > ** in_BYPASS_WRITE_GPR_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_write]; |
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167 | sc_signal<Tgeneral_address_t> ** in_BYPASS_WRITE_GPR_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_write]; |
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168 | sc_signal<Tgeneral_data_t > ** in_BYPASS_WRITE_GPR_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_write]; |
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169 | sc_signal<Tcontrol_t > ** in_BYPASS_WRITE_SPR_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_write]; |
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170 | sc_signal<Tspecial_address_t> ** in_BYPASS_WRITE_SPR_NUM_REG = new sc_signal<Tspecial_address_t> * [_param->_nb_bypass_write]; |
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171 | sc_signal<Tspecial_data_t > ** in_BYPASS_WRITE_SPR_DATA = new sc_signal<Tspecial_data_t > * [_param->_nb_bypass_write]; |
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172 | |
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173 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
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174 | { |
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175 | in_BYPASS_WRITE_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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176 | in_BYPASS_WRITE_GPR_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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177 | in_BYPASS_WRITE_GPR_NUM_REG [i] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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178 | in_BYPASS_WRITE_GPR_DATA [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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179 | in_BYPASS_WRITE_SPR_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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180 | in_BYPASS_WRITE_SPR_NUM_REG [i] = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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181 | in_BYPASS_WRITE_SPR_DATA [i] = new sc_signal<Tspecial_data_t > (rename.c_str()); |
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182 | } |
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183 | sc_signal<Tcontrol_t > ** in_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_memory]; |
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184 | sc_signal<Tcontext_t > ** in_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_memory]; |
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185 | sc_signal<Tgeneral_address_t> ** in_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_memory]; |
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186 | sc_signal<Tgeneral_data_t > ** in_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_memory]; |
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187 | |
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188 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
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189 | { |
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190 | in_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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191 | in_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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192 | in_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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193 | in_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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194 | } |
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195 | |
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196 | /******************************************************** |
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197 | * Instanciation |
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198 | ********************************************************/ |
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199 | |
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200 | cout << "<" << name << "> Instanciation of _Reservation_station" << endl; |
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201 | |
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202 | (*(_Reservation_station->in_CLOCK)) (*(in_CLOCK)); |
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203 | (*(_Reservation_station->in_NRESET)) (*(in_NRESET)); |
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204 | |
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205 | (*(_Reservation_station-> in_INSERT_VAL )) (*( in_INSERT_VAL )); |
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206 | (*(_Reservation_station->out_INSERT_ACK )) (*(out_INSERT_ACK )); |
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207 | if (_param->_have_port_context_id) |
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208 | (*(_Reservation_station-> in_INSERT_CONTEXT_ID )) (*( in_INSERT_CONTEXT_ID )); |
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209 | if (_param->_have_port_front_end_id) |
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210 | (*(_Reservation_station-> in_INSERT_FRONT_END_ID )) (*( in_INSERT_FRONT_END_ID )); |
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211 | if (_param->_have_port_ooo_engine_id) |
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212 | (*(_Reservation_station-> in_INSERT_OOO_ENGINE_ID )) (*( in_INSERT_OOO_ENGINE_ID )); |
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213 | if (_param->_have_port_rob_id) |
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214 | (*(_Reservation_station-> in_INSERT_ROB_ID )) (*( in_INSERT_ROB_ID )); |
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215 | (*(_Reservation_station-> in_INSERT_OPERATION )) (*( in_INSERT_OPERATION )); |
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216 | (*(_Reservation_station-> in_INSERT_TYPE )) (*( in_INSERT_TYPE )); |
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217 | (*(_Reservation_station-> in_INSERT_STORE_QUEUE_PTR_WRITE)) (*( in_INSERT_STORE_QUEUE_PTR_WRITE)); |
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218 | (*(_Reservation_station-> in_INSERT_LOAD_QUEUE_PTR_WRITE )) (*( in_INSERT_LOAD_QUEUE_PTR_WRITE )); |
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219 | (*(_Reservation_station-> in_INSERT_HAS_IMMEDIAT )) (*( in_INSERT_HAS_IMMEDIAT )); |
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220 | (*(_Reservation_station-> in_INSERT_IMMEDIAT )) (*( in_INSERT_IMMEDIAT )); |
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221 | // (*(_Reservation_station-> in_INSERT_READ_RA )) (*( in_INSERT_READ_RA )); |
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222 | (*(_Reservation_station-> in_INSERT_NUM_REG_RA )) (*( in_INSERT_NUM_REG_RA )); |
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223 | (*(_Reservation_station-> in_INSERT_DATA_RA_VAL )) (*( in_INSERT_DATA_RA_VAL )); |
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224 | (*(_Reservation_station-> in_INSERT_DATA_RA )) (*( in_INSERT_DATA_RA )); |
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225 | // (*(_Reservation_station-> in_INSERT_READ_RB )) (*( in_INSERT_READ_RB )); |
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226 | (*(_Reservation_station-> in_INSERT_NUM_REG_RB )) (*( in_INSERT_NUM_REG_RB )); |
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227 | (*(_Reservation_station-> in_INSERT_DATA_RB_VAL )) (*( in_INSERT_DATA_RB_VAL )); |
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228 | (*(_Reservation_station-> in_INSERT_DATA_RB )) (*( in_INSERT_DATA_RB )); |
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229 | // (*(_Reservation_station-> in_INSERT_READ_RC )) (*( in_INSERT_READ_RC )); |
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230 | (*(_Reservation_station-> in_INSERT_NUM_REG_RC )) (*( in_INSERT_NUM_REG_RC )); |
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231 | (*(_Reservation_station-> in_INSERT_DATA_RC_VAL )) (*( in_INSERT_DATA_RC_VAL )); |
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232 | (*(_Reservation_station-> in_INSERT_DATA_RC )) (*( in_INSERT_DATA_RC )); |
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233 | (*(_Reservation_station-> in_INSERT_WRITE_RD )) (*( in_INSERT_WRITE_RD )); |
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234 | (*(_Reservation_station-> in_INSERT_NUM_REG_RD )) (*( in_INSERT_NUM_REG_RD )); |
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235 | (*(_Reservation_station-> in_INSERT_WRITE_RE )) (*( in_INSERT_WRITE_RE )); |
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236 | (*(_Reservation_station-> in_INSERT_NUM_REG_RE )) (*( in_INSERT_NUM_REG_RE )); |
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237 | |
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238 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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239 | { |
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240 | (*(_Reservation_station->out_RETIRE_VAL [i])) (*(out_RETIRE_VAL [i])); |
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241 | (*(_Reservation_station-> in_RETIRE_ACK [i])) (*( in_RETIRE_ACK [i])); |
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242 | if (_param->_have_port_context_id) |
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243 | (*(_Reservation_station->out_RETIRE_CONTEXT_ID [i])) (*(out_RETIRE_CONTEXT_ID [i])); |
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244 | if (_param->_have_port_front_end_id) |
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245 | (*(_Reservation_station->out_RETIRE_FRONT_END_ID [i])) (*(out_RETIRE_FRONT_END_ID [i])); |
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246 | if (_param->_have_port_ooo_engine_id) |
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247 | (*(_Reservation_station->out_RETIRE_OOO_ENGINE_ID [i])) (*(out_RETIRE_OOO_ENGINE_ID [i])); |
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248 | if (_param->_have_port_rob_id) |
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249 | (*(_Reservation_station->out_RETIRE_ROB_ID [i])) (*(out_RETIRE_ROB_ID [i])); |
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250 | (*(_Reservation_station->out_RETIRE_OPERATION [i])) (*(out_RETIRE_OPERATION [i])); |
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251 | (*(_Reservation_station->out_RETIRE_TYPE [i])) (*(out_RETIRE_TYPE [i])); |
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252 | (*(_Reservation_station->out_RETIRE_STORE_QUEUE_PTR_WRITE [i])) (*(out_RETIRE_STORE_QUEUE_PTR_WRITE [i])); |
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253 | (*(_Reservation_station->out_RETIRE_LOAD_QUEUE_PTR_WRITE [i])) (*(out_RETIRE_LOAD_QUEUE_PTR_WRITE [i])); |
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254 | (*(_Reservation_station->out_RETIRE_HAS_IMMEDIAT [i])) (*(out_RETIRE_HAS_IMMEDIAT [i])); |
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255 | (*(_Reservation_station->out_RETIRE_IMMEDIAT [i])) (*(out_RETIRE_IMMEDIAT [i])); |
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256 | (*(_Reservation_station->out_RETIRE_DATA_RA [i])) (*(out_RETIRE_DATA_RA [i])); |
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257 | (*(_Reservation_station->out_RETIRE_DATA_RB [i])) (*(out_RETIRE_DATA_RB [i])); |
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258 | (*(_Reservation_station->out_RETIRE_DATA_RC [i])) (*(out_RETIRE_DATA_RC [i])); |
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259 | (*(_Reservation_station->out_RETIRE_WRITE_RD [i])) (*(out_RETIRE_WRITE_RD [i])); |
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260 | (*(_Reservation_station->out_RETIRE_NUM_REG_RD [i])) (*(out_RETIRE_NUM_REG_RD [i])); |
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261 | (*(_Reservation_station->out_RETIRE_WRITE_RE [i])) (*(out_RETIRE_WRITE_RE [i])); |
---|
262 | (*(_Reservation_station->out_RETIRE_NUM_REG_RE [i])) (*(out_RETIRE_NUM_REG_RE [i])); |
---|
263 | } |
---|
264 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
---|
265 | { |
---|
266 | (*(_Reservation_station-> in_GPR_WRITE_VAL [i])) (*( in_GPR_WRITE_VAL [i])); |
---|
267 | if (_param->_have_port_ooo_engine_id) |
---|
268 | (*(_Reservation_station-> in_GPR_WRITE_OOO_ENGINE_ID [i])) (*( in_GPR_WRITE_OOO_ENGINE_ID [i])); |
---|
269 | (*(_Reservation_station-> in_GPR_WRITE_NUM_REG [i])) (*( in_GPR_WRITE_NUM_REG [i])); |
---|
270 | (*(_Reservation_station-> in_GPR_WRITE_DATA [i])) (*( in_GPR_WRITE_DATA [i])); |
---|
271 | } |
---|
272 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
---|
273 | { |
---|
274 | (*(_Reservation_station-> in_SPR_WRITE_VAL [i])) (*( in_SPR_WRITE_VAL [i])); |
---|
275 | if (_param->_have_port_ooo_engine_id) |
---|
276 | (*(_Reservation_station-> in_SPR_WRITE_OOO_ENGINE_ID [i])) (*( in_SPR_WRITE_OOO_ENGINE_ID [i])); |
---|
277 | (*(_Reservation_station-> in_SPR_WRITE_NUM_REG [i])) (*( in_SPR_WRITE_NUM_REG [i])); |
---|
278 | (*(_Reservation_station-> in_SPR_WRITE_DATA [i])) (*( in_SPR_WRITE_DATA [i])); |
---|
279 | } |
---|
280 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
---|
281 | { |
---|
282 | if (_param->_have_port_ooo_engine_id) |
---|
283 | (*(_Reservation_station-> in_BYPASS_WRITE_OOO_ENGINE_ID [i])) (*( in_BYPASS_WRITE_OOO_ENGINE_ID [i])); |
---|
284 | (*(_Reservation_station-> in_BYPASS_WRITE_GPR_VAL [i])) (*( in_BYPASS_WRITE_GPR_VAL [i])); |
---|
285 | (*(_Reservation_station-> in_BYPASS_WRITE_GPR_NUM_REG [i])) (*( in_BYPASS_WRITE_GPR_NUM_REG [i])); |
---|
286 | (*(_Reservation_station-> in_BYPASS_WRITE_GPR_DATA [i])) (*( in_BYPASS_WRITE_GPR_DATA [i])); |
---|
287 | (*(_Reservation_station-> in_BYPASS_WRITE_SPR_VAL [i])) (*( in_BYPASS_WRITE_SPR_VAL [i])); |
---|
288 | (*(_Reservation_station-> in_BYPASS_WRITE_SPR_NUM_REG [i])) (*( in_BYPASS_WRITE_SPR_NUM_REG [i])); |
---|
289 | (*(_Reservation_station-> in_BYPASS_WRITE_SPR_DATA [i])) (*( in_BYPASS_WRITE_SPR_DATA [i])); |
---|
290 | } |
---|
291 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
---|
292 | { |
---|
293 | (*(_Reservation_station-> in_BYPASS_MEMORY_VAL [i])) (*( in_BYPASS_MEMORY_VAL [i])); |
---|
294 | if (_param->_have_port_ooo_engine_id) |
---|
295 | (*(_Reservation_station-> in_BYPASS_MEMORY_OOO_ENGINE_ID [i])) (*( in_BYPASS_MEMORY_OOO_ENGINE_ID [i])); |
---|
296 | (*(_Reservation_station-> in_BYPASS_MEMORY_NUM_REG [i])) (*( in_BYPASS_MEMORY_NUM_REG [i])); |
---|
297 | (*(_Reservation_station-> in_BYPASS_MEMORY_DATA [i])) (*( in_BYPASS_MEMORY_DATA [i])); |
---|
298 | } |
---|
299 | |
---|
300 | cout << "<" << name << "> Start Simulation ............" << endl; |
---|
301 | Time * _time = new Time(); |
---|
302 | |
---|
303 | /******************************************************** |
---|
304 | * Simulation - Begin |
---|
305 | ********************************************************/ |
---|
306 | |
---|
307 | // Initialisation |
---|
308 | |
---|
309 | const uint32_t nb_request = _param->_nb_packet; |
---|
310 | const uint32_t seed = 0; |
---|
311 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
---|
312 | srand(seed); |
---|
313 | |
---|
314 | Tcontext_t _ooo_engine_id [nb_request]; |
---|
315 | Tcontrol_t _read_ra [nb_request]; |
---|
316 | Tgeneral_address_t _num_reg_ra [nb_request]; |
---|
317 | Tcontrol_t _read_rb [nb_request]; |
---|
318 | Tgeneral_address_t _num_reg_rb [nb_request]; |
---|
319 | Tcontrol_t _read_rc [nb_request]; |
---|
320 | Tspecial_address_t _num_reg_rc [nb_request]; |
---|
321 | |
---|
322 | // emulation of registerFile |
---|
323 | Tcontrol_t _gpr_val [_param->_nb_general_register][_param->_nb_ooo_engine]; |
---|
324 | Tgeneral_data_t _gpr [_param->_nb_general_register][_param->_nb_ooo_engine]; |
---|
325 | Tcontrol_t _spr_val [_param->_nb_special_register][_param->_nb_ooo_engine]; |
---|
326 | Tspecial_data_t _spr [_param->_nb_special_register][_param->_nb_ooo_engine]; |
---|
327 | |
---|
328 | SC_START(0); |
---|
329 | |
---|
330 | LABEL("Initialisation"); |
---|
331 | in_INSERT_VAL ->write(0); |
---|
332 | for (uint32_t i=0; i<_param->_nb_inst_retire ; i++) |
---|
333 | in_RETIRE_ACK [i]->write(0); |
---|
334 | for (uint32_t i=0; i<_param->_nb_gpr_write ; i++) |
---|
335 | in_GPR_WRITE_VAL [i]->write(0); |
---|
336 | for (uint32_t i=0; i<_param->_nb_spr_write ; i++) |
---|
337 | in_SPR_WRITE_VAL [i]->write(0); |
---|
338 | for (uint32_t i=0; i<_param->_nb_bypass_write ; i++) |
---|
339 | { |
---|
340 | in_BYPASS_WRITE_GPR_VAL [i]->write(0); |
---|
341 | in_BYPASS_WRITE_SPR_VAL [i]->write(0); |
---|
342 | } |
---|
343 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
---|
344 | in_BYPASS_MEMORY_VAL [i]->write(0); |
---|
345 | |
---|
346 | in_NRESET->write(0); |
---|
347 | SC_START(5); |
---|
348 | in_NRESET->write(1); |
---|
349 | |
---|
350 | LABEL("Loop of Test"); |
---|
351 | |
---|
352 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
---|
353 | { |
---|
354 | LABEL("Iteration "+toString(iteration)); |
---|
355 | |
---|
356 | int32_t percent_transaction_queue_in = (rand()%50)+25; |
---|
357 | int32_t percent_transaction_queue_out = (rand()%50)+25; |
---|
358 | int32_t percent_registerfile_valid = (rand()%50)+25; |
---|
359 | int32_t percent_transaction_registerfile = (rand()%50)+25; |
---|
360 | int32_t percent_transaction_bypass = (rand()%50)+25; |
---|
361 | |
---|
362 | LABEL("Initialisation"); |
---|
363 | |
---|
364 | for (uint32_t i=0; i<nb_request; i++) |
---|
365 | { |
---|
366 | _ooo_engine_id [i] = rand()% _param->_nb_ooo_engine ; |
---|
367 | _read_ra [i] = rand()% 2 ; |
---|
368 | _num_reg_ra [i] = rand()% _param->_nb_general_register ; |
---|
369 | _read_rb [i] = rand()% 2 ; |
---|
370 | _num_reg_rb [i] = rand()% _param->_nb_general_register ; |
---|
371 | _read_rc [i] = rand()% 2 ; |
---|
372 | _num_reg_rc [i] = rand()% _param->_nb_special_register ; |
---|
373 | } |
---|
374 | |
---|
375 | // emulation of registerFile |
---|
376 | for (uint32_t j=0; j<_param->_nb_ooo_engine; j++) |
---|
377 | { |
---|
378 | for (uint32_t i=0; i<_param->_nb_general_register; i++) |
---|
379 | { |
---|
380 | _gpr_val [i][j] = ((rand()%100) < percent_registerfile_valid); |
---|
381 | _gpr [i][j] = range<Tgeneral_data_t>(rand(),_param->_size_general_data); |
---|
382 | } |
---|
383 | for (uint32_t i=0; i<_param->_nb_special_register; i++) |
---|
384 | { |
---|
385 | _spr_val [i][j] = ((rand()%100) < percent_registerfile_valid); |
---|
386 | _spr [i][j] = range<Tspecial_data_t>(rand(),_param->_size_special_data); |
---|
387 | } |
---|
388 | } |
---|
389 | // End initialisation ....... |
---|
390 | |
---|
391 | uint32_t request_in = 0; |
---|
392 | uint32_t request_out = 0; |
---|
393 | bool request_out_wait [nb_request]; |
---|
394 | |
---|
395 | for (uint32_t i=0; i<nb_request; i++) |
---|
396 | request_out_wait [i] = true; |
---|
397 | |
---|
398 | bool can_gpr_use [_param->_nb_ooo_engine][_param->_nb_general_register]; |
---|
399 | bool can_spr_use [_param->_nb_ooo_engine][_param->_nb_special_register]; |
---|
400 | bool need_gpr [_param->_nb_ooo_engine][_param->_nb_general_register]; |
---|
401 | bool need_spr [_param->_nb_ooo_engine][_param->_nb_special_register]; |
---|
402 | |
---|
403 | |
---|
404 | for (uint32_t j=0; j<_param->_nb_ooo_engine; j++) |
---|
405 | { |
---|
406 | for (uint32_t i=0; i<_param->_nb_general_register; i++) |
---|
407 | need_gpr [j][i] = false; |
---|
408 | for (uint32_t i=0; i<_param->_nb_special_register; i++) |
---|
409 | need_spr [j][i] = false; |
---|
410 | } |
---|
411 | |
---|
412 | while (request_out < nb_request) |
---|
413 | { |
---|
414 | for (uint32_t j=0; j<_param->_nb_ooo_engine; j++) |
---|
415 | { |
---|
416 | for (uint32_t i=0; i<_param->_nb_general_register; i++) |
---|
417 | can_gpr_use [j][i] = true; |
---|
418 | for (uint32_t i=0; i<_param->_nb_special_register; i++) |
---|
419 | can_spr_use [j][i] = true; |
---|
420 | } |
---|
421 | |
---|
422 | Tcontrol_t insert_val = (request_in < nb_request) and ((rand()%100) < percent_transaction_queue_in); |
---|
423 | Tcontext_t insert_ooo_engine_id; |
---|
424 | Tgeneral_address_t insert_num_reg_ra; |
---|
425 | Tgeneral_address_t insert_num_reg_rb; |
---|
426 | Tspecial_address_t insert_num_reg_rc; |
---|
427 | |
---|
428 | in_INSERT_VAL ->write(insert_val); |
---|
429 | if (insert_val) |
---|
430 | { |
---|
431 | bool data_val; |
---|
432 | insert_ooo_engine_id = _ooo_engine_id [request_in]; |
---|
433 | insert_num_reg_ra = _num_reg_ra [request_in]; |
---|
434 | insert_num_reg_rb = _num_reg_rb [request_in]; |
---|
435 | insert_num_reg_rc = _num_reg_rc [request_in]; |
---|
436 | |
---|
437 | if (_param->_have_port_context_id) |
---|
438 | in_INSERT_CONTEXT_ID ->write((2*insert_ooo_engine_id)%_param->_nb_context ); |
---|
439 | if (_param->_have_port_front_end_id) |
---|
440 | in_INSERT_FRONT_END_ID ->write((3*insert_ooo_engine_id)%_param->_nb_front_end); |
---|
441 | if (_param->_have_port_ooo_engine_id) |
---|
442 | in_INSERT_OOO_ENGINE_ID ->write(insert_ooo_engine_id); |
---|
443 | if (_param->_have_port_rob_id) |
---|
444 | in_INSERT_ROB_ID ->write(request_in); |
---|
445 | in_INSERT_OPERATION ->write(0); |
---|
446 | in_INSERT_TYPE ->write(0); |
---|
447 | in_INSERT_STORE_QUEUE_PTR_WRITE->write(0); |
---|
448 | in_INSERT_LOAD_QUEUE_PTR_WRITE ->write(0); |
---|
449 | in_INSERT_HAS_IMMEDIAT->write(0); |
---|
450 | in_INSERT_IMMEDIAT ->write(0); |
---|
451 | // in_INSERT_READ_RA ->write(_read_ra[request_in]); |
---|
452 | data_val = not(_read_ra[request_in]) or _gpr_val[insert_num_reg_ra][insert_ooo_engine_id]; |
---|
453 | |
---|
454 | need_gpr [insert_ooo_engine_id][insert_num_reg_ra] |= not data_val; |
---|
455 | |
---|
456 | in_INSERT_NUM_REG_RA ->write(insert_num_reg_ra); |
---|
457 | in_INSERT_DATA_RA_VAL ->write(data_val); |
---|
458 | in_INSERT_DATA_RA ->write((data_val)?_gpr[insert_num_reg_ra][insert_ooo_engine_id]:0); |
---|
459 | // in_INSERT_READ_RB ->write(_read_rb[request_in]); |
---|
460 | data_val = not(_read_rb[request_in]) or _gpr_val[insert_num_reg_rb][insert_ooo_engine_id]; |
---|
461 | |
---|
462 | need_gpr [insert_ooo_engine_id][insert_num_reg_rb] |= not data_val; |
---|
463 | |
---|
464 | in_INSERT_NUM_REG_RB ->write(insert_num_reg_rb); |
---|
465 | in_INSERT_DATA_RB_VAL ->write(data_val); |
---|
466 | in_INSERT_DATA_RB ->write((data_val)?_gpr[insert_num_reg_rb][insert_ooo_engine_id]:0); |
---|
467 | // in_INSERT_READ_RC ->write(_read_rc[request_in]); |
---|
468 | data_val = not(_read_rc[request_in]) or _spr_val[insert_num_reg_rc][insert_ooo_engine_id]; |
---|
469 | |
---|
470 | need_spr [insert_ooo_engine_id][insert_num_reg_rc] |= not data_val; |
---|
471 | |
---|
472 | in_INSERT_NUM_REG_RC ->write(insert_num_reg_rc); |
---|
473 | in_INSERT_DATA_RC_VAL ->write(data_val); |
---|
474 | in_INSERT_DATA_RC ->write((data_val)?_spr[insert_num_reg_rc][insert_ooo_engine_id]:0); |
---|
475 | in_INSERT_WRITE_RD ->write(0); |
---|
476 | in_INSERT_NUM_REG_RD ->write(0); |
---|
477 | in_INSERT_WRITE_RE ->write(0); |
---|
478 | in_INSERT_NUM_REG_RE ->write(0); |
---|
479 | |
---|
480 | can_gpr_use [insert_ooo_engine_id][insert_num_reg_ra] = false; |
---|
481 | can_gpr_use [insert_ooo_engine_id][insert_num_reg_rb] = false; |
---|
482 | can_spr_use [insert_ooo_engine_id][insert_num_reg_rc] = false; |
---|
483 | } |
---|
484 | |
---|
485 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
---|
486 | in_RETIRE_ACK[i]->write((rand()%100)<percent_transaction_queue_out); |
---|
487 | |
---|
488 | LABEL("Bypass Network :"); |
---|
489 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
---|
490 | { |
---|
491 | Tgeneral_address_t num_reg = rand()% _param->_nb_general_register; |
---|
492 | Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; |
---|
493 | Tcontrol_t val = (_gpr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_registerfile):0; |
---|
494 | Tgeneral_data_t data = range<Tgeneral_data_t>(rand(),_param->_size_general_data); |
---|
495 | |
---|
496 | val = (val and can_gpr_use [ooo_engine][num_reg] and need_gpr [ooo_engine][num_reg]); |
---|
497 | |
---|
498 | in_GPR_WRITE_VAL [i]->write(val); |
---|
499 | if (_param->_have_port_ooo_engine_id) |
---|
500 | in_GPR_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
501 | in_GPR_WRITE_NUM_REG [i]->write(num_reg); |
---|
502 | in_GPR_WRITE_DATA [i]->write(data); |
---|
503 | |
---|
504 | if (val) |
---|
505 | { |
---|
506 | LABEL(" * GPR_WRITE ["+toString(i)+"] - gpr["+toString(num_reg)+"]["+toString(ooo_engine)+"] <- "+toString(data)); |
---|
507 | can_gpr_use [ooo_engine][num_reg] = false; |
---|
508 | need_gpr [ooo_engine][num_reg] = false; |
---|
509 | |
---|
510 | |
---|
511 | _gpr [num_reg][ooo_engine] = data; |
---|
512 | _gpr_val [num_reg][ooo_engine] = 1; |
---|
513 | } |
---|
514 | } |
---|
515 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
---|
516 | { |
---|
517 | Tspecial_address_t num_reg = rand()% _param->_nb_special_register; |
---|
518 | Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; |
---|
519 | Tcontrol_t val = (_spr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_registerfile):0; |
---|
520 | Tspecial_data_t data = range<Tspecial_data_t>(rand(),_param->_size_special_data); |
---|
521 | |
---|
522 | val = (val and can_spr_use [ooo_engine][num_reg] and need_spr[ooo_engine][num_reg]); |
---|
523 | |
---|
524 | in_SPR_WRITE_VAL [i]->write(val); |
---|
525 | if (_param->_have_port_ooo_engine_id) |
---|
526 | in_SPR_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
527 | in_SPR_WRITE_NUM_REG [i]->write(num_reg); |
---|
528 | in_SPR_WRITE_DATA [i]->write(data); |
---|
529 | |
---|
530 | if (val == 1) |
---|
531 | { |
---|
532 | LABEL(" * SPR_WRITE ["+toString(i)+"] - spr["+toString(num_reg)+"]["+toString(ooo_engine)+"] <- "+toString(data)); |
---|
533 | can_spr_use [ooo_engine][num_reg] = false; |
---|
534 | need_spr[ooo_engine][num_reg] = false; |
---|
535 | |
---|
536 | _spr [num_reg][ooo_engine] = data; |
---|
537 | _spr_val [num_reg][ooo_engine] = 1; |
---|
538 | } |
---|
539 | } |
---|
540 | |
---|
541 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
---|
542 | { |
---|
543 | Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; |
---|
544 | if (_param->_have_port_ooo_engine_id) |
---|
545 | in_BYPASS_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
546 | |
---|
547 | Tgeneral_address_t gpr_num_reg = rand()% _param->_nb_general_register; |
---|
548 | Tcontrol_t gpr_val = (_gpr_val [gpr_num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; |
---|
549 | Tgeneral_data_t gpr_data = range<Tgeneral_data_t>(rand(),_param->_size_general_data); |
---|
550 | |
---|
551 | gpr_val = (gpr_val and can_gpr_use [ooo_engine][gpr_num_reg] and need_gpr[ooo_engine][gpr_num_reg]); |
---|
552 | |
---|
553 | in_BYPASS_WRITE_GPR_VAL [i]->write(gpr_val); |
---|
554 | in_BYPASS_WRITE_GPR_NUM_REG[i]->write(gpr_num_reg); |
---|
555 | in_BYPASS_WRITE_GPR_DATA [i]->write(gpr_data); |
---|
556 | |
---|
557 | if (gpr_val) |
---|
558 | { |
---|
559 | LABEL(" * BYPASS_WRITE ["+toString(i)+"] - gpr["+toString(gpr_num_reg)+"]["+toString(ooo_engine)+"] <- "+toString(gpr_data)); |
---|
560 | can_gpr_use [ooo_engine][gpr_num_reg] = false; |
---|
561 | need_gpr[ooo_engine][gpr_num_reg] = false; |
---|
562 | |
---|
563 | _gpr [gpr_num_reg][ooo_engine] = gpr_data; |
---|
564 | _gpr_val [gpr_num_reg][ooo_engine] = 1; |
---|
565 | } |
---|
566 | |
---|
567 | Tspecial_address_t spr_num_reg = rand()% _param->_nb_special_register; |
---|
568 | Tcontrol_t spr_val = (_spr_val [spr_num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; |
---|
569 | Tspecial_data_t spr_data = range<Tspecial_data_t>(rand(),_param->_size_special_data); |
---|
570 | |
---|
571 | spr_val = (spr_val and can_spr_use [ooo_engine][spr_num_reg] and need_spr[ooo_engine][spr_num_reg]); |
---|
572 | |
---|
573 | in_BYPASS_WRITE_SPR_VAL [i]->write(spr_val); |
---|
574 | in_BYPASS_WRITE_SPR_NUM_REG[i]->write(spr_num_reg); |
---|
575 | in_BYPASS_WRITE_SPR_DATA [i]->write(spr_data); |
---|
576 | |
---|
577 | if (spr_val) |
---|
578 | { |
---|
579 | LABEL(" * BYPASS_WRITE ["+toString(i)+"] - spr["+toString(spr_num_reg)+"]["+toString(ooo_engine)+"] <- "+toString(spr_data)); |
---|
580 | can_spr_use [ooo_engine][spr_num_reg] = false; |
---|
581 | need_spr[ooo_engine][spr_num_reg] = false; |
---|
582 | |
---|
583 | _spr [spr_num_reg][ooo_engine] = spr_data; |
---|
584 | _spr_val [spr_num_reg][ooo_engine] = 1; |
---|
585 | } |
---|
586 | |
---|
587 | } |
---|
588 | |
---|
589 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
---|
590 | { |
---|
591 | Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; |
---|
592 | if (_param->_have_port_ooo_engine_id) |
---|
593 | in_BYPASS_MEMORY_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
594 | |
---|
595 | Tgeneral_address_t num_reg = rand()% _param->_nb_general_register; |
---|
596 | Tcontrol_t val = (_gpr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; |
---|
597 | Tgeneral_data_t data = range<Tgeneral_data_t>(rand(),_param->_size_general_data); |
---|
598 | |
---|
599 | val = (val and can_gpr_use [ooo_engine][num_reg] and need_gpr [ooo_engine][num_reg]); |
---|
600 | |
---|
601 | in_BYPASS_MEMORY_VAL [i]->write(val); |
---|
602 | in_BYPASS_MEMORY_NUM_REG[i]->write(num_reg); |
---|
603 | in_BYPASS_MEMORY_DATA [i]->write(data); |
---|
604 | |
---|
605 | if (val) |
---|
606 | { |
---|
607 | LABEL(" * BYPASS_MEMORY ["+toString(i)+"] - gpr["+toString(num_reg)+"]["+toString(ooo_engine)+"] <- "+toString(data)); |
---|
608 | can_gpr_use [ooo_engine][num_reg] = false; |
---|
609 | need_gpr [ooo_engine][num_reg] = false; |
---|
610 | |
---|
611 | _gpr [num_reg][ooo_engine] = data; |
---|
612 | _gpr_val [num_reg][ooo_engine] = 1; |
---|
613 | } |
---|
614 | } |
---|
615 | SC_START(0); // to mealy function |
---|
616 | |
---|
617 | // LABEL("Test INSERT : "+toString(in_INSERT_VAL->read())+","+toString(out_INSERT_ACK->read())); |
---|
618 | if (( in_INSERT_VAL->read() == 1) and |
---|
619 | (out_INSERT_ACK->read() == 1)) |
---|
620 | { |
---|
621 | LABEL("Accepted INSERT number : "+toString(request_in)); |
---|
622 | request_in ++; |
---|
623 | } |
---|
624 | |
---|
625 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
---|
626 | { |
---|
627 | LABEL("Test RETIRE "+toString(i)+" : "+toString(out_RETIRE_VAL[i]->read())+","+toString(in_RETIRE_ACK[i]->read())); |
---|
628 | if ((out_RETIRE_VAL [i]->read() == 1) and |
---|
629 | ( in_RETIRE_ACK [i]->read() == 1)) |
---|
630 | { |
---|
631 | Tpacket_t rob_id; |
---|
632 | if (_param->_have_port_rob_id) |
---|
633 | rob_id = out_RETIRE_ROB_ID [i]->read(); |
---|
634 | else |
---|
635 | rob_id = 0; |
---|
636 | LABEL("Accepted RETIRE ["+toString(i)+"] number : "+toString(rob_id)+", request number : "+toString(request_out)); |
---|
637 | TEST(bool, request_out_wait [rob_id] , true); |
---|
638 | |
---|
639 | request_out ++; |
---|
640 | request_out_wait [rob_id] = false; |
---|
641 | |
---|
642 | Tcontext_t ooo_engine_id = _ooo_engine_id [rob_id]; |
---|
643 | |
---|
644 | if (_param->_have_port_context_id) |
---|
645 | TEST(Tcontext_t ,out_RETIRE_CONTEXT_ID [i]->read(),(2*ooo_engine_id)%_param->_nb_context ); |
---|
646 | if (_param->_have_port_front_end_id) |
---|
647 | TEST(Tcontext_t ,out_RETIRE_FRONT_END_ID [i]->read(),(3*ooo_engine_id)%_param->_nb_front_end); |
---|
648 | if (_param->_have_port_ooo_engine_id) |
---|
649 | TEST(Tcontext_t ,out_RETIRE_OOO_ENGINE_ID[i]->read(),ooo_engine_id); |
---|
650 | |
---|
651 | if (_read_ra [rob_id]) |
---|
652 | TEST(Tgeneral_data_t ,out_RETIRE_DATA_RA [i]->read(),_gpr[_num_reg_ra[rob_id]][ooo_engine_id]); |
---|
653 | |
---|
654 | if (_read_rb [rob_id]) |
---|
655 | TEST(Tgeneral_data_t ,out_RETIRE_DATA_RB [i]->read(),_gpr[_num_reg_rb[rob_id]][ooo_engine_id]); |
---|
656 | |
---|
657 | if (_read_rc [rob_id]) |
---|
658 | TEST(Tspecial_data_t ,out_RETIRE_DATA_RC [i]->read(),_spr[_num_reg_rc[rob_id]][ooo_engine_id]); |
---|
659 | |
---|
660 | // need_gpr [ooo_engine_id][_num_reg_ra[rob_id]]= true; |
---|
661 | // need_gpr [ooo_engine_id][_num_reg_rb[rob_id]]= true; |
---|
662 | // need_spr [ooo_engine_id][_num_reg_rc[rob_id]]= true; |
---|
663 | } |
---|
664 | } |
---|
665 | |
---|
666 | SC_START(1); |
---|
667 | } |
---|
668 | } |
---|
669 | |
---|
670 | /******************************************************** |
---|
671 | * Simulation - End |
---|
672 | ********************************************************/ |
---|
673 | |
---|
674 | TEST_OK ("End of Simulation"); |
---|
675 | delete _time; |
---|
676 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
---|
677 | |
---|
678 | delete in_CLOCK ; |
---|
679 | delete in_NRESET; |
---|
680 | |
---|
681 | delete in_INSERT_VAL ; |
---|
682 | delete out_INSERT_ACK ; |
---|
683 | if (_param->_have_port_context_id) |
---|
684 | delete in_INSERT_CONTEXT_ID ; |
---|
685 | if (_param->_have_port_front_end_id) |
---|
686 | delete in_INSERT_FRONT_END_ID ; |
---|
687 | if (_param->_have_port_ooo_engine_id) |
---|
688 | delete in_INSERT_OOO_ENGINE_ID ; |
---|
689 | if (_param->_have_port_rob_id) |
---|
690 | delete in_INSERT_ROB_ID ; |
---|
691 | delete in_INSERT_OPERATION ; |
---|
692 | delete in_INSERT_TYPE ; |
---|
693 | delete in_INSERT_STORE_QUEUE_PTR_WRITE; |
---|
694 | delete in_INSERT_LOAD_QUEUE_PTR_WRITE ; |
---|
695 | delete in_INSERT_HAS_IMMEDIAT; |
---|
696 | delete in_INSERT_IMMEDIAT ; |
---|
697 | //delete in_INSERT_READ_RA ; |
---|
698 | delete in_INSERT_NUM_REG_RA ; |
---|
699 | delete in_INSERT_DATA_RA_VAL ; |
---|
700 | delete in_INSERT_DATA_RA ; |
---|
701 | //delete in_INSERT_READ_RB ; |
---|
702 | delete in_INSERT_NUM_REG_RB ; |
---|
703 | delete in_INSERT_DATA_RB_VAL ; |
---|
704 | delete in_INSERT_DATA_RB ; |
---|
705 | //delete in_INSERT_READ_RC ; |
---|
706 | delete in_INSERT_NUM_REG_RC ; |
---|
707 | delete in_INSERT_DATA_RC_VAL ; |
---|
708 | delete in_INSERT_DATA_RC ; |
---|
709 | delete in_INSERT_WRITE_RD ; |
---|
710 | delete in_INSERT_NUM_REG_RD ; |
---|
711 | delete in_INSERT_WRITE_RE ; |
---|
712 | delete in_INSERT_NUM_REG_RE ; |
---|
713 | |
---|
714 | delete [] out_RETIRE_VAL ; |
---|
715 | delete [] in_RETIRE_ACK ; |
---|
716 | if (_param->_have_port_context_id) |
---|
717 | delete [] out_RETIRE_CONTEXT_ID ; |
---|
718 | if (_param->_have_port_front_end_id) |
---|
719 | delete [] out_RETIRE_FRONT_END_ID; |
---|
720 | if (_param->_have_port_ooo_engine_id) |
---|
721 | delete [] out_RETIRE_OOO_ENGINE_ID ; |
---|
722 | if (_param->_have_port_rob_id) |
---|
723 | delete [] out_RETIRE_ROB_ID ; |
---|
724 | delete [] out_RETIRE_OPERATION ; |
---|
725 | delete [] out_RETIRE_TYPE ; |
---|
726 | delete [] out_RETIRE_STORE_QUEUE_PTR_WRITE; |
---|
727 | delete [] out_RETIRE_LOAD_QUEUE_PTR_WRITE ; |
---|
728 | delete [] out_RETIRE_HAS_IMMEDIAT; |
---|
729 | delete [] out_RETIRE_IMMEDIAT ; |
---|
730 | delete [] out_RETIRE_DATA_RA ; |
---|
731 | delete [] out_RETIRE_DATA_RB ; |
---|
732 | delete [] out_RETIRE_DATA_RC ; |
---|
733 | delete [] out_RETIRE_WRITE_RD ; |
---|
734 | delete [] out_RETIRE_NUM_REG_RD ; |
---|
735 | delete [] out_RETIRE_WRITE_RE ; |
---|
736 | delete [] out_RETIRE_NUM_REG_RE ; |
---|
737 | |
---|
738 | delete [] in_GPR_WRITE_VAL ; |
---|
739 | if (_param->_have_port_ooo_engine_id) |
---|
740 | delete [] in_GPR_WRITE_OOO_ENGINE_ID; |
---|
741 | delete [] in_GPR_WRITE_NUM_REG ; |
---|
742 | delete [] in_GPR_WRITE_DATA ; |
---|
743 | |
---|
744 | delete [] in_SPR_WRITE_VAL ; |
---|
745 | if (_param->_have_port_ooo_engine_id) |
---|
746 | delete [] in_SPR_WRITE_OOO_ENGINE_ID; |
---|
747 | delete [] in_SPR_WRITE_NUM_REG ; |
---|
748 | delete [] in_SPR_WRITE_DATA ; |
---|
749 | |
---|
750 | if (_param->_have_port_ooo_engine_id) |
---|
751 | delete [] in_BYPASS_WRITE_OOO_ENGINE_ID ; |
---|
752 | delete [] in_BYPASS_WRITE_GPR_VAL ; |
---|
753 | delete [] in_BYPASS_WRITE_GPR_NUM_REG; |
---|
754 | delete [] in_BYPASS_WRITE_GPR_DATA ; |
---|
755 | delete [] in_BYPASS_WRITE_SPR_VAL ; |
---|
756 | delete [] in_BYPASS_WRITE_SPR_NUM_REG; |
---|
757 | delete [] in_BYPASS_WRITE_SPR_DATA ; |
---|
758 | |
---|
759 | delete [] in_BYPASS_MEMORY_VAL ; |
---|
760 | if (_param->_have_port_ooo_engine_id) |
---|
761 | delete [] in_BYPASS_MEMORY_OOO_ENGINE_ID; |
---|
762 | delete [] in_BYPASS_MEMORY_NUM_REG ; |
---|
763 | delete [] in_BYPASS_MEMORY_DATA ; |
---|
764 | #endif |
---|
765 | |
---|
766 | delete _Reservation_station; |
---|
767 | #ifdef STATISTICS |
---|
768 | delete _parameters_statistics; |
---|
769 | #endif |
---|
770 | } |
---|