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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/src/test.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 15 years ago
Almost complete design with Test and test platform
Property svn:keywords set to `Id`
File size: 37.6 KB

Line
1	/*
2	* $Id: test.cpp 88 2008-12-10 18:31:39Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 16
10	#define CYCLE_MAX (1024*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Common/include/BitManipulation.h"
15	#include "Behavioural/include/Allocation.h"
16
17	class write_req_t
18	{
19	public : uint32_t ooo;
20	public : uint32_t reg;
21
22	write_req_t (uint32_t ooo,
23	uint32_t reg)
24	{
25	this->ooo = ooo;
26	this->reg = reg;
27	}
28	};
29
30	void test (string name,
31	morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::Parameters * _param)
32	{
33	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
34
35	#ifdef STATISTICS
36	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
37	#endif
38
39	Tusage_t _usage = USE_ALL;
40
41	// _usage = usage_unset(_usage,USE_SYSTEMC );
42	// _usage = usage_unset(_usage,USE_VHDL );
43	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
44	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
45	// _usage = usage_unset(_usage,USE_POSITION );
46	// _usage = usage_unset(_usage,USE_STATISTICS );
47	// _usage = usage_unset(_usage,USE_INFORMATION );
48
49	Read_unit * _Read_unit = new Read_unit
50	(name.c_str(),
51	#ifdef STATISTICS
52	_parameters_statistics,
53	#endif
54	_param,
55	_usage);
56
57	#ifdef SYSTEMC
58	/*********************************************************************
59	* Déclarations des signaux
60	*********************************************************************/
61	string rename;
62
63	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
64	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
65
66	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_VAL ," in_READ_UNIT_IN_VAL ",Tcontrol_t );
67	ALLOC_SC_SIGNAL (out_READ_UNIT_IN_ACK ,"out_READ_UNIT_IN_ACK ",Tcontrol_t );
68	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_CONTEXT_ID ," in_READ_UNIT_IN_CONTEXT_ID ",Tcontext_t );
69	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_FRONT_END_ID ," in_READ_UNIT_IN_FRONT_END_ID ",Tcontext_t );
70	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_OOO_ENGINE_ID ," in_READ_UNIT_IN_OOO_ENGINE_ID ",Tcontext_t );
71	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_PACKET_ID ," in_READ_UNIT_IN_PACKET_ID ",Tpacket_t );
72	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_OPERATION ," in_READ_UNIT_IN_OPERATION ",Toperation_t );
73	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_TYPE ," in_READ_UNIT_IN_TYPE ",Ttype_t );
74	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE ," in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE ",Tlsq_ptr_t );
75	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ," in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t );
76	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_HAS_IMMEDIAT ," in_READ_UNIT_IN_HAS_IMMEDIAT ",Tcontrol_t );
77	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_IMMEDIAT ," in_READ_UNIT_IN_IMMEDIAT ",Tgeneral_data_t );
78	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_READ_RA ," in_READ_UNIT_IN_READ_RA ",Tcontrol_t );
79	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_NUM_REG_RA ," in_READ_UNIT_IN_NUM_REG_RA ",Tgeneral_address_t);
80	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_READ_RB ," in_READ_UNIT_IN_READ_RB ",Tcontrol_t );
81	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_NUM_REG_RB ," in_READ_UNIT_IN_NUM_REG_RB ",Tgeneral_address_t);
82	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_READ_RC ," in_READ_UNIT_IN_READ_RC ",Tcontrol_t );
83	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_NUM_REG_RC ," in_READ_UNIT_IN_NUM_REG_RC ",Tspecial_address_t);
84	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_WRITE_RD ," in_READ_UNIT_IN_WRITE_RD ",Tcontrol_t );
85	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_NUM_REG_RD ," in_READ_UNIT_IN_NUM_REG_RD ",Tgeneral_address_t);
86	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_WRITE_RE ," in_READ_UNIT_IN_WRITE_RE ",Tcontrol_t );
87	ALLOC_SC_SIGNAL ( in_READ_UNIT_IN_NUM_REG_RE ," in_READ_UNIT_IN_NUM_REG_RE ",Tspecial_address_t);
88	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_VAL ,"out_READ_UNIT_OUT_VAL ",Tcontrol_t ,_param->_nb_inst_retire);
89	ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_ACK ," in_READ_UNIT_OUT_ACK ",Tcontrol_t ,_param->_nb_inst_retire);
90	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_CONTEXT_ID ,"out_READ_UNIT_OUT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_retire);
91	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_FRONT_END_ID ,"out_READ_UNIT_OUT_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_retire);
92	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_OOO_ENGINE_ID ,"out_READ_UNIT_OUT_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_inst_retire);
93	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_PACKET_ID ,"out_READ_UNIT_OUT_PACKET_ID ",Tpacket_t ,_param->_nb_inst_retire);
94	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_OPERATION ,"out_READ_UNIT_OUT_OPERATION ",Toperation_t ,_param->_nb_inst_retire);
95	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_TYPE ,"out_READ_UNIT_OUT_TYPE ",Ttype_t ,_param->_nb_inst_retire);
96	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE,"out_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_inst_retire);
97	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ,"out_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_inst_retire);
98	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_HAS_IMMEDIAT ,"out_READ_UNIT_OUT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_retire);
99	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_IMMEDIAT ,"out_READ_UNIT_OUT_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_retire);
100	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_DATA_RA ,"out_READ_UNIT_OUT_DATA_RA ",Tgeneral_data_t ,_param->_nb_inst_retire);
101	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_DATA_RB ,"out_READ_UNIT_OUT_DATA_RB ",Tgeneral_data_t ,_param->_nb_inst_retire);
102	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_DATA_RC ,"out_READ_UNIT_OUT_DATA_RC ",Tspecial_data_t ,_param->_nb_inst_retire);
103	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_WRITE_RD ,"out_READ_UNIT_OUT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_retire);
104	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_NUM_REG_RD ,"out_READ_UNIT_OUT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_retire);
105	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_WRITE_RE ,"out_READ_UNIT_OUT_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_retire);
106	ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_NUM_REG_RE ,"out_READ_UNIT_OUT_NUM_REG_RE ",Tspecial_address_t,_param->_nb_inst_retire);
107	ALLOC1_SC_SIGNAL(out_GPR_READ_VAL ,"out_GPR_READ_VAL ",Tcontrol_t ,_param->_nb_gpr_read);
108	ALLOC1_SC_SIGNAL( in_GPR_READ_ACK ," in_GPR_READ_ACK ",Tcontrol_t ,_param->_nb_gpr_read);
109	ALLOC1_SC_SIGNAL(out_GPR_READ_OOO_ENGINE_ID ,"out_GPR_READ_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_gpr_read);
110	ALLOC1_SC_SIGNAL(out_GPR_READ_NUM_REG ,"out_GPR_READ_NUM_REG ",Tgeneral_address_t,_param->_nb_gpr_read);
111	ALLOC1_SC_SIGNAL( in_GPR_READ_DATA ," in_GPR_READ_DATA ",Tgeneral_data_t ,_param->_nb_gpr_read);
112	ALLOC1_SC_SIGNAL( in_GPR_READ_DATA_VAL ," in_GPR_READ_DATA_VAL ",Tcontrol_t ,_param->_nb_gpr_read);
113	ALLOC1_SC_SIGNAL(out_SPR_READ_VAL ,"out_SPR_READ_VAL ",Tcontrol_t ,_param->_nb_spr_read);
114	ALLOC1_SC_SIGNAL( in_SPR_READ_ACK ," in_SPR_READ_ACK ",Tcontrol_t ,_param->_nb_spr_read);
115	ALLOC1_SC_SIGNAL(out_SPR_READ_OOO_ENGINE_ID ,"out_SPR_READ_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_spr_read);
116	ALLOC1_SC_SIGNAL(out_SPR_READ_NUM_REG ,"out_SPR_READ_NUM_REG ",Tspecial_address_t,_param->_nb_spr_read);
117	ALLOC1_SC_SIGNAL( in_SPR_READ_DATA ," in_SPR_READ_DATA ",Tspecial_data_t ,_param->_nb_spr_read);
118	ALLOC1_SC_SIGNAL( in_SPR_READ_DATA_VAL ," in_SPR_READ_DATA_VAL ",Tcontrol_t ,_param->_nb_spr_read);
119	ALLOC1_SC_SIGNAL( in_GPR_WRITE_VAL ," in_GPR_WRITE_VAL ",Tcontrol_t ,_param->_nb_gpr_write);
120	ALLOC1_SC_SIGNAL( in_GPR_WRITE_OOO_ENGINE_ID ," in_GPR_WRITE_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_gpr_write);
121	ALLOC1_SC_SIGNAL( in_GPR_WRITE_NUM_REG ," in_GPR_WRITE_NUM_REG ",Tgeneral_address_t,_param->_nb_gpr_write);
122	ALLOC1_SC_SIGNAL( in_GPR_WRITE_DATA ," in_GPR_WRITE_DATA ",Tgeneral_data_t ,_param->_nb_gpr_write);
123	ALLOC1_SC_SIGNAL( in_SPR_WRITE_VAL ," in_SPR_WRITE_VAL ",Tcontrol_t ,_param->_nb_spr_write);
124	ALLOC1_SC_SIGNAL( in_SPR_WRITE_OOO_ENGINE_ID ," in_SPR_WRITE_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_spr_write);
125	ALLOC1_SC_SIGNAL( in_SPR_WRITE_NUM_REG ," in_SPR_WRITE_NUM_REG ",Tspecial_address_t,_param->_nb_spr_write);
126	ALLOC1_SC_SIGNAL( in_SPR_WRITE_DATA ," in_SPR_WRITE_DATA ",Tspecial_data_t ,_param->_nb_spr_write);
127	ALLOC1_SC_SIGNAL( in_BYPASS_WRITE_OOO_ENGINE_ID ," in_BYPASS_WRITE_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_bypass_write);
128	ALLOC1_SC_SIGNAL( in_BYPASS_WRITE_GPR_VAL ," in_BYPASS_WRITE_GPR_VAL ",Tcontrol_t ,_param->_nb_bypass_write);
129	ALLOC1_SC_SIGNAL( in_BYPASS_WRITE_GPR_NUM_REG ," in_BYPASS_WRITE_GPR_NUM_REG ",Tgeneral_address_t,_param->_nb_bypass_write);
130	ALLOC1_SC_SIGNAL( in_BYPASS_WRITE_GPR_DATA ," in_BYPASS_WRITE_GPR_DATA ",Tgeneral_data_t ,_param->_nb_bypass_write);
131	ALLOC1_SC_SIGNAL( in_BYPASS_WRITE_SPR_VAL ," in_BYPASS_WRITE_SPR_VAL ",Tcontrol_t ,_param->_nb_bypass_write);
132	ALLOC1_SC_SIGNAL( in_BYPASS_WRITE_SPR_NUM_REG ," in_BYPASS_WRITE_SPR_NUM_REG ",Tspecial_address_t,_param->_nb_bypass_write);
133	ALLOC1_SC_SIGNAL( in_BYPASS_WRITE_SPR_DATA ," in_BYPASS_WRITE_SPR_DATA ",Tspecial_data_t ,_param->_nb_bypass_write);
134	ALLOC1_SC_SIGNAL( in_BYPASS_MEMORY_VAL ," in_BYPASS_MEMORY_VAL ",Tcontrol_t ,_param->_nb_bypass_memory);
135	ALLOC1_SC_SIGNAL( in_BYPASS_MEMORY_OOO_ENGINE_ID ," in_BYPASS_MEMORY_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_bypass_memory);
136	ALLOC1_SC_SIGNAL( in_BYPASS_MEMORY_NUM_REG ," in_BYPASS_MEMORY_NUM_REG ",Tgeneral_address_t,_param->_nb_bypass_memory);
137	ALLOC1_SC_SIGNAL( in_BYPASS_MEMORY_DATA ," in_BYPASS_MEMORY_DATA ",Tgeneral_data_t ,_param->_nb_bypass_memory);
138
139	/********************************************************
140	* Instanciation
141	********************************************************/
142
143	msg(_("<%s> : Instanciation of _Read_unit.\n"),name.c_str());
144
145	((_Read_unit->in_CLOCK)) ((in_CLOCK));
146	((_Read_unit->in_NRESET)) ((in_NRESET));
147
148	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_VAL );
149	INSTANCE_SC_SIGNAL (_Read_unit,out_READ_UNIT_IN_ACK );
150	if (_param->_have_port_context_id)
151	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_CONTEXT_ID );
152	if (_param->_have_port_front_end_id)
153	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_FRONT_END_ID );
154	if (_param->_have_port_ooo_engine_id)
155	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_OOO_ENGINE_ID );
156	if (_param->_have_port_rob_ptr)
157	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_PACKET_ID );
158	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_OPERATION );
159	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_TYPE );
160	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE );
161	if (_param->_have_port_load_queue_ptr)
162	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE );
163	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_HAS_IMMEDIAT );
164	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_IMMEDIAT );
165	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_READ_RA );
166	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_NUM_REG_RA );
167	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_READ_RB );
168	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_NUM_REG_RB );
169	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_READ_RC );
170	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_NUM_REG_RC );
171	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_WRITE_RD );
172	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_NUM_REG_RD );
173	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_WRITE_RE );
174	INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_NUM_REG_RE );
175	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_VAL ,_param->_nb_inst_retire);
176	INSTANCE1_SC_SIGNAL(_Read_unit, in_READ_UNIT_OUT_ACK ,_param->_nb_inst_retire);
177	if (_param->_have_port_context_id)
178	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_CONTEXT_ID ,_param->_nb_inst_retire);
179	if (_param->_have_port_front_end_id)
180	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_FRONT_END_ID ,_param->_nb_inst_retire);
181	if (_param->_have_port_ooo_engine_id)
182	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_OOO_ENGINE_ID ,_param->_nb_inst_retire);
183	if (_param->_have_port_rob_ptr)
184	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_PACKET_ID ,_param->_nb_inst_retire);
185	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_OPERATION ,_param->_nb_inst_retire);
186	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_TYPE ,_param->_nb_inst_retire);
187	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_retire);
188	if (_param->_have_port_load_queue_ptr)
189	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_retire);
190	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_HAS_IMMEDIAT ,_param->_nb_inst_retire);
191	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_IMMEDIAT ,_param->_nb_inst_retire);
192	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_DATA_RA ,_param->_nb_inst_retire);
193	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_DATA_RB ,_param->_nb_inst_retire);
194	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_DATA_RC ,_param->_nb_inst_retire);
195	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_WRITE_RD ,_param->_nb_inst_retire);
196	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_NUM_REG_RD ,_param->_nb_inst_retire);
197	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_WRITE_RE ,_param->_nb_inst_retire);
198	INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_NUM_REG_RE ,_param->_nb_inst_retire);
199	INSTANCE1_SC_SIGNAL(_Read_unit,out_GPR_READ_VAL ,_param->_nb_gpr_read);
200	INSTANCE1_SC_SIGNAL(_Read_unit, in_GPR_READ_ACK ,_param->_nb_gpr_read);
201	if (_param->_have_port_ooo_engine_id)
202	INSTANCE1_SC_SIGNAL(_Read_unit,out_GPR_READ_OOO_ENGINE_ID ,_param->_nb_gpr_read);
203	INSTANCE1_SC_SIGNAL(_Read_unit,out_GPR_READ_NUM_REG ,_param->_nb_gpr_read);
204	INSTANCE1_SC_SIGNAL(_Read_unit, in_GPR_READ_DATA ,_param->_nb_gpr_read);
205	INSTANCE1_SC_SIGNAL(_Read_unit, in_GPR_READ_DATA_VAL ,_param->_nb_gpr_read);
206	INSTANCE1_SC_SIGNAL(_Read_unit,out_SPR_READ_VAL ,_param->_nb_spr_read);
207	INSTANCE1_SC_SIGNAL(_Read_unit, in_SPR_READ_ACK ,_param->_nb_spr_read);
208	if (_param->_have_port_ooo_engine_id)
209	INSTANCE1_SC_SIGNAL(_Read_unit,out_SPR_READ_OOO_ENGINE_ID ,_param->_nb_spr_read);
210	INSTANCE1_SC_SIGNAL(_Read_unit,out_SPR_READ_NUM_REG ,_param->_nb_spr_read);
211	INSTANCE1_SC_SIGNAL(_Read_unit, in_SPR_READ_DATA ,_param->_nb_spr_read);
212	INSTANCE1_SC_SIGNAL(_Read_unit, in_SPR_READ_DATA_VAL ,_param->_nb_spr_read);
213	INSTANCE1_SC_SIGNAL(_Read_unit, in_GPR_WRITE_VAL ,_param->_nb_gpr_write);
214	if (_param->_have_port_ooo_engine_id)
215	INSTANCE1_SC_SIGNAL(_Read_unit, in_GPR_WRITE_OOO_ENGINE_ID ,_param->_nb_gpr_write);
216	INSTANCE1_SC_SIGNAL(_Read_unit, in_GPR_WRITE_NUM_REG ,_param->_nb_gpr_write);
217	INSTANCE1_SC_SIGNAL(_Read_unit, in_GPR_WRITE_DATA ,_param->_nb_gpr_write);
218	INSTANCE1_SC_SIGNAL(_Read_unit, in_SPR_WRITE_VAL ,_param->_nb_spr_write);
219	if (_param->_have_port_ooo_engine_id)
220	INSTANCE1_SC_SIGNAL(_Read_unit, in_SPR_WRITE_OOO_ENGINE_ID ,_param->_nb_spr_write);
221	INSTANCE1_SC_SIGNAL(_Read_unit, in_SPR_WRITE_NUM_REG ,_param->_nb_spr_write);
222	INSTANCE1_SC_SIGNAL(_Read_unit, in_SPR_WRITE_DATA ,_param->_nb_spr_write);
223	if (_param->_have_port_ooo_engine_id)
224	INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_WRITE_OOO_ENGINE_ID ,_param->_nb_bypass_write);
225	INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_WRITE_GPR_VAL ,_param->_nb_bypass_write);
226	INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_WRITE_GPR_NUM_REG ,_param->_nb_bypass_write);
227	INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_WRITE_GPR_DATA ,_param->_nb_bypass_write);
228	INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_WRITE_SPR_VAL ,_param->_nb_bypass_write);
229	INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_WRITE_SPR_NUM_REG ,_param->_nb_bypass_write);
230	INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_WRITE_SPR_DATA ,_param->_nb_bypass_write);
231	INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_MEMORY_VAL ,_param->_nb_bypass_memory);
232	if (_param->_have_port_ooo_engine_id)
233	INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory);
234	INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_MEMORY_NUM_REG ,_param->_nb_bypass_memory);
235	INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_MEMORY_DATA ,_param->_nb_bypass_memory);
236
237	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
238
239	// Initialisation
240	const uint32_t seed = 0;
241	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
242
243	srand(seed);
244
245	SC_START(0);
246
247	Time * _time = new Time();
248
249	/********************************************************
250	* Simulation - Begin
251	********************************************************/
252	{
253	// Initialisation
254
255	const uint32_t nb_request = _param->_nb_packet;
256
257	Tcontext_t _ooo_engine_id [nb_request];
258	Tcontrol_t _read_ra [nb_request];
259	Tgeneral_address_t _num_reg_ra [nb_request];
260	Tcontrol_t _read_rb [nb_request];
261	Tgeneral_address_t _num_reg_rb [nb_request];
262	Tcontrol_t _read_rc [nb_request];
263	Tspecial_address_t _num_reg_rc [nb_request];
264
265	// emulation of registerFile
266	Tcontrol_t _gpr_val [_param->_nb_general_register][_param->_nb_ooo_engine];
267	Tgeneral_data_t _gpr [_param->_nb_general_register][_param->_nb_ooo_engine];
268	Tcontrol_t _spr_val [_param->_nb_special_register][_param->_nb_ooo_engine];
269	Tspecial_data_t _spr [_param->_nb_special_register][_param->_nb_ooo_engine];
270
271	LABEL("Initialisation");
272	in_READ_UNIT_IN_VAL ->write(0);
273	for (uint32_t i=0; i<_param->_nb_inst_retire ; i++)
274	in_READ_UNIT_OUT_ACK [i]->write(0);
275	for (uint32_t i=0; i<_param->_nb_gpr_write ; i++)
276	in_GPR_WRITE_VAL [i]->write(0);
277	for (uint32_t i=0; i<_param->_nb_spr_write ; i++)
278	in_SPR_WRITE_VAL [i]->write(0);
279	for (uint32_t i=0; i<_param->_nb_bypass_write ; i++)
280	{
281	in_BYPASS_WRITE_GPR_VAL [i]->write(0);
282	in_BYPASS_WRITE_SPR_VAL [i]->write(0);
283	}
284	for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
285	in_BYPASS_MEMORY_VAL [i]->write(0);
286
287	in_NRESET->write(0);
288	SC_START(5);
289	in_NRESET->write(1);
290
291	LABEL("Loop of Test");
292
293	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
294	{
295	LABEL("Iteration %d",iteration);
296
297	int32_t percent_transaction_queue_in = (rand()%50)+25;
298	int32_t percent_transaction_queue_out = (rand()%50)+25;
299	int32_t percent_registerfile_valid = (rand()%50)+25;
300	int32_t percent_transaction_registerfile = (rand()%50)+25;
301	int32_t percent_transaction_bypass = (rand()%50)+25;
302
303	LABEL("Initialisation");
304
305	for (uint32_t i=0; i<nb_request; i++)
306	{
307	_ooo_engine_id [i] = rand()% _param->_nb_ooo_engine ;
308	_read_ra [i] = rand()% 2 ;
309	_num_reg_ra [i] = rand()% _param->_nb_general_register ;
310	_read_rb [i] = rand()% 2 ;
311	_num_reg_rb [i] = rand()% _param->_nb_general_register ;
312	_read_rc [i] = rand()% 2 ;
313	_num_reg_rc [i] = rand()% _param->_nb_special_register ;
314	}
315
316	// emulation of registerFile
317	for (uint32_t j=0; j<_param->_nb_ooo_engine; j++)
318	{
319	for (uint32_t i=0; i<_param->_nb_general_register; i++)
320	{
321	_gpr_val [i][j] = ((rand()%100) < percent_registerfile_valid);
322	_gpr [i][j] = range<Tgeneral_data_t>(rand(),_param->_size_general_data);
323	}
324	for (uint32_t i=0; i<_param->_nb_special_register; i++)
325	{
326	_spr_val [i][j] = ((rand()%100) < percent_registerfile_valid);
327	_spr [i][j] = range<Tspecial_data_t>(rand(),_param->_size_special_data);
328	}
329	}
330	// End initialisation .......
331
332	uint32_t request_in = 0;
333	uint32_t request_out = 0;
334	bool request_out_wait [nb_request];
335
336	for (uint32_t i=0; i<nb_request; i++)
337	request_out_wait [i] = true;
338
339	// bool can_gpr_use [_param->_nb_ooo_engine][_param->_nb_general_register];
340	// bool can_spr_use [_param->_nb_ooo_engine][_param->_nb_special_register];
341
342	list<write_req_t> write_req_gpr;
343	list<write_req_t> write_req_spr;
344
345	while (request_out < nb_request)
346	{
347	LABEL("request_in : %d",request_in );
348	LABEL("request_out : %d",request_out);
349	for (uint32_t i=0; i<nb_request; i++)
350	if (request_out_wait [i])
351	LABEL("request_out_wait : %d",i);
352	LABEL("write_req_gpr size : %d",write_req_gpr.size());
353	LABEL("write_req_spr size : %d",write_req_spr.size());
354
355	// for (uint32_t j=0; j<_param->_nb_ooo_engine; j++)
356	// {
357	// for (uint32_t i=0; i<_param->_nb_general_register; i++)
358	// can_gpr_use [j][i] = true;
359	// for (uint32_t i=0; i<_param->_nb_special_register; i++)
360	// can_spr_use [j][i] = true;
361	// }
362
363	Tcontrol_t read_unit_in_val = (request_in < nb_request) and ((rand()%100) < percent_transaction_queue_in);
364	Tcontext_t read_unit_in_ooo_engine_id;
365	Tgeneral_address_t read_unit_in_num_reg_ra;
366	Tgeneral_address_t read_unit_in_num_reg_rb;
367	Tspecial_address_t read_unit_in_num_reg_rc;
368
369	in_READ_UNIT_IN_VAL ->write(read_unit_in_val);
370	if (read_unit_in_val)
371	{
372	bool data_val;
373	read_unit_in_ooo_engine_id = _ooo_engine_id [request_in];
374	read_unit_in_num_reg_ra = _num_reg_ra [request_in];
375	read_unit_in_num_reg_rb = _num_reg_rb [request_in];
376	read_unit_in_num_reg_rc = _num_reg_rc [request_in];
377
378	if (_param->_have_port_context_id)
379	in_READ_UNIT_IN_CONTEXT_ID ->write((2*read_unit_in_ooo_engine_id)%_param->_nb_context );
380	if (_param->_have_port_front_end_id)
381	in_READ_UNIT_IN_FRONT_END_ID ->write((3*read_unit_in_ooo_engine_id)%_param->_nb_front_end);
382	if (_param->_have_port_ooo_engine_id)
383	in_READ_UNIT_IN_OOO_ENGINE_ID ->write(read_unit_in_ooo_engine_id);
384	if (_param->_have_port_rob_ptr)
385	in_READ_UNIT_IN_PACKET_ID ->write(request_in);
386	in_READ_UNIT_IN_OPERATION ->write(0);
387	in_READ_UNIT_IN_TYPE ->write(0);
388	in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE->write(0);
389	if (_param->_have_port_load_queue_ptr)
390	in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ->write(0);
391	in_READ_UNIT_IN_HAS_IMMEDIAT->write(0);
392	in_READ_UNIT_IN_IMMEDIAT ->write(0);
393	in_READ_UNIT_IN_READ_RA ->write(_read_ra[request_in]);
394	data_val = not(_read_ra[request_in]) or _gpr_val[read_unit_in_num_reg_ra][read_unit_in_ooo_engine_id];
395
396	if (not data_val)
397	if (rand ()%2)
398	write_req_gpr.push_back (write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_ra));
399	else
400	write_req_gpr.push_front(write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_ra));
401
402
403	in_READ_UNIT_IN_NUM_REG_RA ->write(read_unit_in_num_reg_ra);
404	// in_READ_UNIT_IN_DATA_RA_VAL ->write(data_val);
405	// in_READ_UNIT_IN_DATA_RA ->write((data_val)?_gpr[read_unit_in_num_reg_ra][read_unit_in_ooo_engine_id]:0);
406	in_READ_UNIT_IN_READ_RB ->write(_read_rb[request_in]);
407	data_val = not(_read_rb[request_in]) or _gpr_val[read_unit_in_num_reg_rb][read_unit_in_ooo_engine_id];
408
409	if (not data_val)
410	if (rand ()%2)
411	write_req_gpr.push_back (write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_rb));
412	else
413	write_req_gpr.push_front(write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_rb));
414
415
416	in_READ_UNIT_IN_NUM_REG_RB ->write(read_unit_in_num_reg_rb);
417	// in_READ_UNIT_IN_DATA_RB_VAL ->write(data_val);
418	// in_READ_UNIT_IN_DATA_RB ->write((data_val)?_gpr[read_unit_in_num_reg_rb][read_unit_in_ooo_engine_id]:0);
419	in_READ_UNIT_IN_READ_RC ->write(_read_rc[request_in]);
420	data_val = not(_read_rc[request_in]) or _spr_val[read_unit_in_num_reg_rc][read_unit_in_ooo_engine_id];
421
422	if (not data_val)
423	if (rand ()%2)
424	write_req_spr.push_back (write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_rc));
425	else
426	write_req_spr.push_front(write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_rc));
427
428	in_READ_UNIT_IN_NUM_REG_RC ->write(read_unit_in_num_reg_rc);
429	// in_READ_UNIT_IN_DATA_RC_VAL ->write(data_val);
430	// in_READ_UNIT_IN_DATA_RC ->write((data_val)?_spr[read_unit_in_num_reg_rc][read_unit_in_ooo_engine_id]:0);
431	in_READ_UNIT_IN_WRITE_RD ->write(0);
432	in_READ_UNIT_IN_NUM_REG_RD ->write(0);
433	in_READ_UNIT_IN_WRITE_RE ->write(0);
434	in_READ_UNIT_IN_NUM_REG_RE ->write(0);
435
436	// can_gpr_use [read_unit_in_ooo_engine_id][read_unit_in_num_reg_ra] = false;
437	// can_gpr_use [read_unit_in_ooo_engine_id][read_unit_in_num_reg_rb] = false;
438	// can_spr_use [read_unit_in_ooo_engine_id][read_unit_in_num_reg_rc] = false;
439	}
440
441	for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
442	in_READ_UNIT_OUT_ACK[i]->write((rand()%100)<percent_transaction_queue_out);
443
444	// RegisterFile access
445	for (uint32_t i=0; i<_param->_nb_gpr_read ; i++)
446	{
447	Tcontrol_t ack = (rand()%100) < percent_transaction_registerfile;
448	in_GPR_READ_ACK [i]->write(ack);
449
450	SC_START(0);
451
452	if (out_GPR_READ_VAL [i]->read())
453	{
454	Tgeneral_address_t num_reg = out_GPR_READ_NUM_REG [i]->read();
455	Tcontext_t ooo_engine = (_param->_have_port_ooo_engine_id)?out_GPR_READ_OOO_ENGINE_ID [i]->read():0;
456	Tgeneral_data_t data = _gpr [num_reg][ooo_engine];
457	Tcontrol_t data_val = _gpr_val[num_reg][ooo_engine];
458
459	if (ack)
460	LABEL(" * GPR_READ [%d] - gpr[%d][%d] -> (%d) 0x%x",i,num_reg,ooo_engine,data_val,data);
461
462	in_GPR_READ_DATA [i]->write(data);
463	in_GPR_READ_DATA_VAL [i]->write(data_val);
464	}
465	}
466
467	for (uint32_t i=0; i<_param->_nb_spr_read ; i++)
468	{
469	Tcontrol_t ack = (rand()%100) < percent_transaction_registerfile;
470	in_SPR_READ_ACK [i]->write(ack);
471
472	SC_START(0);
473
474	if (out_SPR_READ_VAL [i]->read())
475	{
476	Tspecial_address_t num_reg = out_SPR_READ_NUM_REG [i]->read();
477	Tcontext_t ooo_engine = (_param->_have_port_ooo_engine_id)?out_SPR_READ_OOO_ENGINE_ID [i]->read():0;
478	Tspecial_data_t data = _spr [num_reg][ooo_engine];
479	Tcontrol_t data_val = _spr_val[num_reg][ooo_engine];
480
481	if (ack)
482	LABEL(" * SPR_READ [%d] - spr[%d][%d] -> (%d) 0x%x",i,num_reg,ooo_engine,data_val,data);
483
484	in_SPR_READ_DATA [i]->write(data);
485	in_SPR_READ_DATA_VAL [i]->write(data_val);
486	}
487	}
488
489	list<write_req_t>::iterator it_gpr = write_req_gpr.begin();
490	list<write_req_t>::iterator it_spr = write_req_spr.begin();
491
492	LABEL("Bypass Network :");
493	for (uint32_t i=0; i<_param->_nb_gpr_write; i++)
494	{
495	Tcontext_t ooo_engine = (it_gpr != write_req_gpr.end())?(*it_gpr).ooo:0;
496	Tgeneral_address_t num_reg = (it_gpr != write_req_gpr.end())?(*it_gpr).reg:0;
497	Tcontrol_t val = (_gpr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_registerfile):0;
498	Tgeneral_data_t data = range<Tgeneral_data_t>(rand(),_param->_size_general_data);
499
500	val = (val// and can_spr_use [ooo_engine][num_reg]
501	and (it_gpr != write_req_gpr.end()));
502
503	in_GPR_WRITE_VAL [i]->write(val);
504	if (_param->_have_port_ooo_engine_id)
505	in_GPR_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine);
506	in_GPR_WRITE_NUM_REG [i]->write(num_reg);
507	in_GPR_WRITE_DATA [i]->write(data);
508
509	if (val)
510	{
511	LABEL(" * GPR_WRITE [%d] - gpr[%d][%d] <- 0x%x",i,num_reg,ooo_engine,data);
512
513	// can_gpr_use [ooo_engine][num_reg] = false;
514
515	_gpr [num_reg][ooo_engine] = data;
516	_gpr_val [num_reg][ooo_engine] = 1;
517	}
518
519	if (it_gpr != write_req_gpr.end())
520	it_gpr ++;
521	}
522	for (uint32_t i=0; i<_param->_nb_spr_write; i++)
523	{
524	Tcontext_t ooo_engine = (it_spr != write_req_spr.end())?(*it_spr).ooo:0;
525	Tgeneral_address_t num_reg = (it_spr != write_req_spr.end())?(*it_spr).reg:0;
526
527	Tcontrol_t val = (_spr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_registerfile):0;
528	Tspecial_data_t data = range<Tspecial_data_t>(rand(),_param->_size_special_data);
529
530	val = (val // and can_spr_use [ooo_engine][num_reg]
531	and (it_spr != write_req_spr.end()));
532
533	in_SPR_WRITE_VAL [i]->write(val);
534	if (_param->_have_port_ooo_engine_id)
535	in_SPR_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine);
536	in_SPR_WRITE_NUM_REG [i]->write(num_reg);
537	in_SPR_WRITE_DATA [i]->write(data);
538
539	if (val == 1)
540	{
541	LABEL(" * SPR_WRITE [%d] - spr[%d][%d] <- 0x%x",i,num_reg,ooo_engine,data);
542
543	// can_spr_use [ooo_engine][num_reg] = false;
544
545	_spr [num_reg][ooo_engine] = data;
546	_spr_val [num_reg][ooo_engine] = 1;
547	}
548
549	if (it_spr != write_req_spr.end())
550	it_spr ++;
551
552	}
553
554	for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
555	{
556	Tcontext_t ooo_engine = (it_gpr != write_req_gpr.end())?(*it_gpr).ooo:0;
557	Tgeneral_address_t gpr_num_reg= (it_gpr != write_req_gpr.end())?(*it_gpr).reg:0;
558
559	if (_param->_have_port_ooo_engine_id)
560	in_BYPASS_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine);
561
562	Tcontrol_t gpr_val = (_gpr_val [gpr_num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0;
563	Tgeneral_data_t gpr_data = range<Tgeneral_data_t>(rand(),_param->_size_general_data);
564
565	gpr_val = (gpr_val // and can_gpr_use [ooo_engine][gpr_num_reg]
566	and (it_gpr != write_req_gpr.end()));
567
568	in_BYPASS_WRITE_GPR_VAL [i]->write(gpr_val);
569	in_BYPASS_WRITE_GPR_NUM_REG[i]->write(gpr_num_reg);
570	in_BYPASS_WRITE_GPR_DATA [i]->write(gpr_data);
571
572	if (gpr_val)
573	{
574	LABEL(" * BYPASS_WRITE [%d] - gpr[%d][%d] <- 0x%x",i,gpr_num_reg,ooo_engine,gpr_data);
575	// can_gpr_use [ooo_engine][gpr_num_reg] = false;
576
577	_gpr [gpr_num_reg][ooo_engine] = gpr_data;
578	_gpr_val [gpr_num_reg][ooo_engine] = 1;
579	}
580
581	if (it_gpr != write_req_gpr.end())
582	it_gpr ++;
583
584	Tspecial_address_t spr_num_reg = (it_spr != write_req_spr.end())?(*it_spr).reg:0;
585	Tcontrol_t spr_val = (_spr_val [spr_num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0;
586	Tspecial_data_t spr_data = range<Tspecial_data_t>(rand(),_param->_size_special_data);
587
588	spr_val = (spr_val // and can_spr_use [ooo_engine][spr_num_reg]
589	and (it_spr != write_req_spr.end()) and ((*it_spr).ooo == ooo_engine));
590
591	in_BYPASS_WRITE_SPR_VAL [i]->write(spr_val);
592	in_BYPASS_WRITE_SPR_NUM_REG[i]->write(spr_num_reg);
593	in_BYPASS_WRITE_SPR_DATA [i]->write(spr_data);
594
595	if (spr_val)
596	{
597	LABEL(" * BYPASS_WRITE [%d] - spr[%d][%d] <- 0x%x",i,spr_num_reg,ooo_engine,spr_data);
598
599	// can_spr_use [ooo_engine][spr_num_reg] = false;
600
601	_spr [spr_num_reg][ooo_engine] = spr_data;
602	_spr_val [spr_num_reg][ooo_engine] = 1;
603	}
604
605	if (it_spr != write_req_spr.end())
606	it_spr ++;
607	}
608
609	for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
610	{
611	Tcontext_t ooo_engine = (it_gpr != write_req_gpr.end())?(*it_gpr).ooo:0;
612	Tgeneral_address_t num_reg = (it_gpr != write_req_gpr.end())?(*it_gpr).reg:0;
613
614	if (_param->_have_port_ooo_engine_id)
615	in_BYPASS_MEMORY_OOO_ENGINE_ID [i]->write(ooo_engine);
616
617	Tcontrol_t val = (_gpr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0;
618	Tgeneral_data_t data = range<Tgeneral_data_t>(rand(),_param->_size_general_data);
619
620	val = (val // and can_gpr_use [ooo_engine][num_reg]
621	and (it_gpr != write_req_gpr.end()));
622
623	in_BYPASS_MEMORY_VAL [i]->write(val);
624	in_BYPASS_MEMORY_NUM_REG[i]->write(num_reg);
625	in_BYPASS_MEMORY_DATA [i]->write(data);
626
627	if (val)
628	{
629	LABEL(" * BYPASS_MEMORY [%d] - gpr[%d][%d] <- 0x%x",i,num_reg,ooo_engine,data);
630
631	// can_gpr_use [ooo_engine][num_reg] = false;
632
633	_gpr [num_reg][ooo_engine] = data;
634	_gpr_val [num_reg][ooo_engine] = 1;
635	}
636
637	if (it_gpr != write_req_gpr.end())
638	it_gpr ++;
639	}
640
641	SC_START(0); // to mealy function
642
643	// LABEL("Test READ_UNIT_IN : "+toString(in_READ_UNIT_IN_VAL->read())+","+toString(out_READ_UNIT_IN_ACK->read()));
644	if (( in_READ_UNIT_IN_VAL->read() == 1) and
645	(out_READ_UNIT_IN_ACK->read() == 1))
646	{
647	LABEL("Accepted READ_UNIT_IN number : %d",request_in);
648	request_in ++;
649	}
650
651	for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
652	{
653	LABEL("Test READ_UNIT_OUT %d : %d,%d",i,out_READ_UNIT_OUT_VAL[i]->read(),in_READ_UNIT_OUT_ACK[i]->read());
654	if ((out_READ_UNIT_OUT_VAL [i]->read() == 1) and
655	( in_READ_UNIT_OUT_ACK [i]->read() == 1))
656	{
657	Tpacket_t packet_id;
658	if (_param->_have_port_rob_ptr)
659	packet_id = out_READ_UNIT_OUT_PACKET_ID [i]->read();
660	else
661	packet_id = 0;
662	LABEL("Accepted READ_UNIT_OUT [%d] number : %d, request number : %d",i,packet_id,request_out);
663	TEST(bool, request_out_wait [packet_id] , true);
664
665	request_out ++;
666	request_out_wait [packet_id] = false;
667
668	Tcontext_t ooo_engine_id = _ooo_engine_id [packet_id];
669
670	if (_param->_have_port_context_id)
671	TEST(Tcontext_t ,out_READ_UNIT_OUT_CONTEXT_ID [i]->read(),(2*ooo_engine_id)%_param->_nb_context );
672	if (_param->_have_port_front_end_id)
673	TEST(Tcontext_t ,out_READ_UNIT_OUT_FRONT_END_ID [i]->read(),(3*ooo_engine_id)%_param->_nb_front_end);
674	if (_param->_have_port_ooo_engine_id)
675	TEST(Tcontext_t ,out_READ_UNIT_OUT_OOO_ENGINE_ID[i]->read(),ooo_engine_id);
676
677	if (_read_ra [packet_id])
678	TEST(Tgeneral_data_t ,out_READ_UNIT_OUT_DATA_RA [i]->read(),_gpr[_num_reg_ra[packet_id]][ooo_engine_id]);
679
680	if (_read_rb [packet_id])
681	TEST(Tgeneral_data_t ,out_READ_UNIT_OUT_DATA_RB [i]->read(),_gpr[_num_reg_rb[packet_id]][ooo_engine_id]);
682
683	if (_read_rc [packet_id])
684	TEST(Tspecial_data_t ,out_READ_UNIT_OUT_DATA_RC [i]->read(),_spr[_num_reg_rc[packet_id]][ooo_engine_id]);
685	}
686	}
687
688	SC_START(1);
689
690	for (list<write_req_t>::iterator it = write_req_gpr.begin();
691	it != write_req_gpr.end();
692	)
693	{
694	if (_gpr_val [(it).reg][(it).ooo] == 1)
695	it = write_req_gpr.erase(it);
696	else
697	it ++;
698	}
699
700	for (list<write_req_t>::iterator it = write_req_spr.begin();
701	it != write_req_spr.end();
702	)
703	{
704	if (_spr_val [(it).reg][(it).ooo] == 1)
705	it = write_req_spr.erase(it);
706	else
707	it ++;
708	}
709	}
710
711	for (uint32_t i=0; i<nb_request; i++)
712	TEST(bool, request_out_wait [i] , false);
713	}
714	}
715
716	/********************************************************
717	* Simulation - End
718	********************************************************/
719
720	TEST_OK ("End of Simulation");
721	delete _time;
722
723	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
724
725	delete in_CLOCK;
726	delete in_NRESET;
727	#endif
728
729	delete _Read_unit;
730	#ifdef STATISTICS
731	delete _parameters_statistics;
732	#endif
733	}

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