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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/src/test.cpp @ 77

Last change on this file since 77 was 77, checked in by rosiere, 16 years ago
Add two component : network between read unit and execute unit network between execute unit and write unit remove parameters "nb_operation" and "nb_type" in write_queue add the special case : load_speculative
File size: 26.9 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/include/test.h"
10	#include "Common/include/Test.h"
11	#include "Common/include/BitManipulation.h"
12	#include "Behavioural/include/Allocation.h"
13
14	#define NB_ITERATION 1
15	#define CYCLE_MAX (128*NB_ITERATION)
16
17	#define LABEL(str...) \
18	{ \
19	msg (_("{%d} "),static_cast<uint32_t>(sc_simulation_time())); \
20	msg (str); \
21	msg (_("\n")); \
22	} while(0)
23
24	#define SC_START(cycle_offset) \
25	do \
26	{ \
27	/cout << "SC_START (begin)" << endl;/ \
28	\
29	uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
30	if (cycle_offset != 0) \
31	{ \
32	cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \
33	} \
34	\
35	if (cycle_current > CYCLE_MAX) \
36	{ \
37	TEST_KO("Maximal cycles Reached"); \
38	} \
39	\
40	sc_start(cycle_offset); \
41	\
42	/cout << "SC_START (end )" << endl;/ \
43	} while(0)
44
45	class entry_t
46	{
47	public : Tcontext_t _context_id ;
48	public : Tcontext_t _front_end_id ;
49	public : Tcontext_t _ooo_engine_id;
50	public : Tpacket_t _packet_id ;
51	//public : Toperation_t _operation ;
52	public : Ttype_t _type ;
53	public : Tcontrol_t _write_rd ;
54	public : Tgeneral_address_t _num_reg_rd ;
55	public : Tgeneral_data_t _data_rd ;
56	public : Tcontrol_t _write_re ;
57	public : Tspecial_address_t _num_reg_re ;
58	public : Tspecial_data_t _data_re ;
59	public : Texception_t _exception ;
60	public : Tcontrol_t _no_sequence ;
61	public : Tgeneral_data_t _address ;
62
63	public : entry_t (Tcontext_t context_id ,
64	Tcontext_t front_end_id ,
65	Tcontext_t ooo_engine_id,
66	Tpacket_t packet_id ,
67	//Toperation_t operation ,
68	Ttype_t type ,
69	Tcontrol_t write_rd ,
70	Tgeneral_address_t num_reg_rd ,
71	Tgeneral_data_t data_rd ,
72	Tcontrol_t write_re ,
73	Tspecial_address_t num_reg_re ,
74	Tspecial_data_t data_re ,
75	Texception_t exception ,
76	Tcontrol_t no_sequence ,
77	Tgeneral_data_t address )
78	{
79	_context_id = context_id ;
80	_front_end_id = front_end_id ;
81	_ooo_engine_id = ooo_engine_id;
82	_packet_id = packet_id ;
83	//_operation = operation ;
84	_type = type ;
85	_write_rd = write_rd ;
86	_num_reg_rd = num_reg_rd ;
87	_data_rd = data_rd ;
88	_write_re = write_re ;
89	_num_reg_re = num_reg_re ;
90	_data_re = data_re ;
91	_exception = exception ;
92	_no_sequence = no_sequence ;
93	_address = address ;
94	};
95
96	friend std::ostream& operator<< (std::ostream& output_stream,
97	entry_t & x)
98	{
99	output_stream << " * _context_id : " << toString(x._context_id ) << std::endl
100	<< " * _front_end_id : " << toString(x._front_end_id ) << std::endl
101	<< " * _ooo_engine_id : " << toString(x._ooo_engine_id) << std::endl
102	<< " * _packet_id : " << toString(x._packet_id ) << std::endl
103	//<< " * _operation : " << toString(x._operation ) << std::endl
104	<< " * _type : " << toString(x._type ) << std::endl
105	<< " * _write_rd : " << toString(x._write_rd ) << std::endl
106	<< " * _num_reg_rd : " << toString(x._num_reg_rd ) << std::endl
107	<< " * _data_rd : " << toString(x._data_rd ) << std::endl
108	<< " * _write_re : " << toString(x._write_re ) << std::endl
109	<< " * _num_reg_re : " << toString(x._num_reg_re ) << std::endl
110	<< " * _data_re : " << toString(x._data_re ) << std::endl
111	<< " * _exception : " << toString(x._exception ) << std::endl
112	<< " * _no_sequence : " << toString(x._no_sequence ) << std::endl
113	<< " * _address : " << toString(x._address ) << std::endl;
114
115	return output_stream;
116	}
117	};
118
119
120	void test (string name,
121	morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::Parameters * _param)
122	{
123	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
124
125	#ifdef STATISTICS
126	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
127	#endif
128
129	Write_unit * _Write_unit = new Write_unit (name.c_str(),
130	#ifdef STATISTICS
131	_parameters_statistics,
132	#endif
133	_param);
134
135	#ifdef SYSTEMC
136	/*********************************************************************
137	* Déclarations des signaux
138	*********************************************************************/
139	string rename;
140
141	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
142	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
143
144	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_VAL ," in_WRITE_UNIT_IN_VAL" , Tcontrol_t );
145	ALLOC_SC_SIGNAL (out_WRITE_UNIT_IN_ACK ,"out_WRITE_UNIT_IN_ACK" , Tcontrol_t );
146	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_CONTEXT_ID ," in_WRITE_UNIT_IN_CONTEXT_ID" , Tcontext_t );
147	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_FRONT_END_ID ," in_WRITE_UNIT_IN_FRONT_END_ID" , Tcontext_t );
148	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_OOO_ENGINE_ID ," in_WRITE_UNIT_IN_OOO_ENGINE_ID" , Tcontext_t );
149	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_PACKET_ID ," in_WRITE_UNIT_IN_PACKET_ID" , Tpacket_t );
150	//ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_OPERATION ," in_WRITE_UNIT_IN_OPERATION" , Toperation_t );
151	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_TYPE ," in_WRITE_UNIT_IN_TYPE" , Ttype_t );
152	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_WRITE_RD ," in_WRITE_UNIT_IN_WRITE_RD" , Tcontrol_t );
153	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_NUM_REG_RD ," in_WRITE_UNIT_IN_NUM_REG_RD" , Tgeneral_address_t);
154	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_DATA_RD ," in_WRITE_UNIT_IN_DATA_RD" , Tgeneral_data_t );
155	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_WRITE_RE ," in_WRITE_UNIT_IN_WRITE_RE" , Tcontrol_t );
156	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_NUM_REG_RE ," in_WRITE_UNIT_IN_NUM_REG_RE" , Tspecial_address_t);
157	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_DATA_RE ," in_WRITE_UNIT_IN_DATA_RE" , Tspecial_data_t );
158	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_EXCEPTION ," in_WRITE_UNIT_IN_EXCEPTION" , Texception_t );
159	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_NO_SEQUENCE ," in_WRITE_UNIT_IN_NO_SEQUENCE" , Tcontrol_t );
160	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_ADDRESS ," in_WRITE_UNIT_IN_ADDRESS" , Tgeneral_data_t );
161	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_VAL ,"out_WRITE_UNIT_OUT_VAL" , Tcontrol_t );
162	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_OUT_ACK ," in_WRITE_UNIT_OUT_ACK" , Tcontrol_t );
163	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_CONTEXT_ID ,"out_WRITE_UNIT_OUT_CONTEXT_ID" , Tcontext_t );
164	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_FRONT_END_ID ,"out_WRITE_UNIT_OUT_FRONT_END_ID" , Tcontext_t );
165	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_OOO_ENGINE_ID,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID", Tcontext_t );
166	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_PACKET_ID ,"out_WRITE_UNIT_OUT_PACKET_ID" , Tpacket_t );
167	//ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_OPERATION ,"out_WRITE_UNIT_OUT_OPERATION" , Toperation_t );
168	//ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_TYPE ,"out_WRITE_UNIT_OUT_TYPE" , Ttype_t );
169	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_FLAGS ,"out_WRITE_UNIT_OUT_FLAGS" , Tspecial_data_t );
170	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_EXCEPTION ,"out_WRITE_UNIT_OUT_EXCEPTION" , Texception_t );
171	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_NO_SEQUENCE ,"out_WRITE_UNIT_OUT_NO_SEQUENCE" , Tcontrol_t );
172	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_ADDRESS ,"out_WRITE_UNIT_OUT_ADDRESS" , Tgeneral_data_t );
173	ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write);
174	ALLOC1_SC_SIGNAL( in_GPR_WRITE_ACK ," in_GPR_WRITE_ACK" , Tcontrol_t , _param->_nb_gpr_write);
175	ALLOC1_SC_SIGNAL(out_GPR_WRITE_OOO_ENGINE_ID ,"out_GPR_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_gpr_write);
176	ALLOC1_SC_SIGNAL(out_GPR_WRITE_NUM_REG ,"out_GPR_WRITE_NUM_REG" , Tgeneral_address_t, _param->_nb_gpr_write);
177	ALLOC1_SC_SIGNAL(out_GPR_WRITE_DATA ,"out_GPR_WRITE_DATA" , Tgeneral_data_t , _param->_nb_gpr_write);
178	ALLOC1_SC_SIGNAL(out_SPR_WRITE_VAL ,"out_SPR_WRITE_VAL" , Tcontrol_t , _param->_nb_spr_write);
179	ALLOC1_SC_SIGNAL( in_SPR_WRITE_ACK ," in_SPR_WRITE_ACK" , Tcontrol_t , _param->_nb_spr_write);
180	ALLOC1_SC_SIGNAL(out_SPR_WRITE_OOO_ENGINE_ID ,"out_SPR_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_spr_write);
181	ALLOC1_SC_SIGNAL(out_SPR_WRITE_NUM_REG ,"out_SPR_WRITE_NUM_REG" , Tspecial_address_t, _param->_nb_spr_write);
182	ALLOC1_SC_SIGNAL(out_SPR_WRITE_DATA ,"out_SPR_WRITE_DATA" , Tspecial_data_t , _param->_nb_spr_write);
183	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_OOO_ENGINE_ID ,"out_BYPASS_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_bypass_write);
184	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_VAL ,"out_BYPASS_WRITE_GPR_VAL" , Tcontrol_t , _param->_nb_bypass_write);
185	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_NUM_REG ,"out_BYPASS_WRITE_GPR_NUM_REG" , Tgeneral_address_t, _param->_nb_bypass_write);
186	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_DATA ,"out_BYPASS_WRITE_GPR_DATA" , Tgeneral_data_t , _param->_nb_bypass_write);
187	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_VAL ,"out_BYPASS_WRITE_SPR_VAL" , Tcontrol_t , _param->_nb_bypass_write);
188	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_NUM_REG ,"out_BYPASS_WRITE_SPR_NUM_REG" , Tspecial_address_t, _param->_nb_bypass_write);
189	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_DATA ,"out_BYPASS_WRITE_SPR_DATA" , Tspecial_data_t , _param->_nb_bypass_write);
190
191
192	/********************************************************
193	* Instanciation
194	********************************************************/
195
196	msg(_("<%s> : Instanciation of _Write_unit.\n"),name.c_str());
197
198	((_Write_unit->in_CLOCK)) ((in_CLOCK));
199	((_Write_unit->in_NRESET)) ((in_NRESET));
200
201	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_VAL );
202	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_IN_ACK );
203	if (_param->_have_port_context_id)
204	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_CONTEXT_ID );
205	if (_param->_have_port_front_end_id)
206	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_FRONT_END_ID );
207	if (_param->_have_port_ooo_engine_id)
208	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_OOO_ENGINE_ID );
209	if (_param->_have_port_packet_id)
210	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_PACKET_ID );
211	//INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_OPERATION );
212	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_TYPE );
213	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_WRITE_RD );
214	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_NUM_REG_RD );
215	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_DATA_RD );
216	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_WRITE_RE );
217	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_NUM_REG_RE );
218	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_DATA_RE );
219	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_EXCEPTION );
220	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_NO_SEQUENCE );
221	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_ADDRESS );
222	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_VAL );
223	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_OUT_ACK );
224	if (_param->_have_port_context_id)
225	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_CONTEXT_ID );
226	if (_param->_have_port_front_end_id)
227	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_FRONT_END_ID );
228	if (_param->_have_port_ooo_engine_id)
229	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_OOO_ENGINE_ID);
230	if (_param->_have_port_packet_id)
231	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_PACKET_ID );
232	//INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_OPERATION );
233	//INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_TYPE );
234	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_FLAGS );
235	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_EXCEPTION );
236	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_NO_SEQUENCE );
237	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_ADDRESS );
238	INSTANCE1_SC_SIGNAL(_Write_unit, out_GPR_WRITE_VAL , _param->_nb_gpr_write);
239	INSTANCE1_SC_SIGNAL(_Write_unit, in_GPR_WRITE_ACK , _param->_nb_gpr_write);
240	if (_param->_have_port_ooo_engine_id)
241	INSTANCE1_SC_SIGNAL(_Write_unit, out_GPR_WRITE_OOO_ENGINE_ID , _param->_nb_gpr_write);
242	INSTANCE1_SC_SIGNAL(_Write_unit, out_GPR_WRITE_NUM_REG , _param->_nb_gpr_write);
243	INSTANCE1_SC_SIGNAL(_Write_unit, out_GPR_WRITE_DATA , _param->_nb_gpr_write);
244	INSTANCE1_SC_SIGNAL(_Write_unit, out_SPR_WRITE_VAL , _param->_nb_spr_write);
245	INSTANCE1_SC_SIGNAL(_Write_unit, in_SPR_WRITE_ACK , _param->_nb_spr_write);
246	if (_param->_have_port_ooo_engine_id)
247	INSTANCE1_SC_SIGNAL(_Write_unit, out_SPR_WRITE_OOO_ENGINE_ID , _param->_nb_spr_write);
248	INSTANCE1_SC_SIGNAL(_Write_unit, out_SPR_WRITE_NUM_REG , _param->_nb_spr_write);
249	INSTANCE1_SC_SIGNAL(_Write_unit, out_SPR_WRITE_DATA , _param->_nb_spr_write);
250	if (_param->_have_port_ooo_engine_id)
251	INSTANCE1_SC_SIGNAL(_Write_unit, out_BYPASS_WRITE_OOO_ENGINE_ID , _param->_nb_bypass_write);
252	INSTANCE1_SC_SIGNAL(_Write_unit, out_BYPASS_WRITE_GPR_VAL , _param->_nb_bypass_write);
253	INSTANCE1_SC_SIGNAL(_Write_unit, out_BYPASS_WRITE_GPR_NUM_REG , _param->_nb_bypass_write);
254	INSTANCE1_SC_SIGNAL(_Write_unit, out_BYPASS_WRITE_GPR_DATA , _param->_nb_bypass_write);
255	INSTANCE1_SC_SIGNAL(_Write_unit, out_BYPASS_WRITE_SPR_VAL , _param->_nb_bypass_write);
256	INSTANCE1_SC_SIGNAL(_Write_unit, out_BYPASS_WRITE_SPR_NUM_REG , _param->_nb_bypass_write);
257	INSTANCE1_SC_SIGNAL(_Write_unit, out_BYPASS_WRITE_SPR_DATA , _param->_nb_bypass_write);
258
259	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
260
261	Time * _time = new Time();
262
263	/********************************************************
264	* Simulation - Begin
265	********************************************************/
266
267	// Initialisation
268
269	const uint32_t seed = 0;
270	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
271
272	srand(seed);
273
274	const int32_t percent_transaction_write_unit_in = 75;
275	const int32_t percent_transaction_write_unit_out = 75;
276	const int32_t percent_transaction_gpr = 75;
277	const int32_t percent_transaction_spr = 75;
278
279	bool gpr_val [_param->_nb_ooo_engine][_param->_nb_general_register];
280	bool gpr_use [_param->_nb_ooo_engine][_param->_nb_general_register];
281	Tgeneral_data_t gpr [_param->_nb_ooo_engine][_param->_nb_general_register];
282	bool spr_val [_param->_nb_ooo_engine][_param->_nb_special_register];
283	bool spr_use [_param->_nb_ooo_engine][_param->_nb_special_register];
284	Tgeneral_data_t spr [_param->_nb_ooo_engine][_param->_nb_special_register];
285
286	entry_t * request [_param->_nb_packet];
287
288	SC_START(0);
289	LABEL("Initialisation");
290
291	LABEL("Reset");
292	in_NRESET->write(0);
293	SC_START(5);
294	in_NRESET->write(1);
295
296	LABEL("Loop of Test");
297
298	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
299	{
300	LABEL("Iteration %d",iteration);
301
302	for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
303	{
304	for (uint32_t j=0; j<_param->_nb_general_register; j++)
305	{
306	gpr_val [i][j] = 0;
307	gpr_use [i][j] = 0;
308	gpr [i][j] = rand();
309	}
310	for (uint32_t j=0; j<_param->_nb_special_register; j++)
311	{
312	spr_val [i][j] = 0;
313	spr_use [i][j] = 0;
314	spr [i][j] = rand();
315	}
316	}
317
318	for (uint32_t i=0; i<_param->_nb_packet; i++)
319	{
320	request [i] = new entry_t (range<Tcontext_t >(rand(),_param->_size_context_id ),
321	range<Tcontext_t >(rand(),_param->_size_front_end_id ),
322	range<Tcontext_t >(rand(),_param->_size_ooo_engine_id ),
323	i,
324	//range<Toperation_t >(rand(),_param->_size_operation ),
325	range<Ttype_t >(rand(),_param->_size_type ),
326	range<Tcontrol_t >(rand(),1 ),
327	range<Tgeneral_address_t>(rand(),_param->_size_general_register),
328	range<Tgeneral_data_t >(rand(),_param->_size_general_data ),
329	range<Tcontrol_t >(rand(),1 ),
330	range<Tspecial_address_t>(rand(),_param->_size_special_register),
331	range<Tspecial_data_t >(rand(),_param->_size_special_data ),
332	range<Texception_t >(rand(),_param->_size_exception ),
333	range<Tcontrol_t >(rand(),1 ),
334	range<Tgeneral_data_t >(rand(),_param->_size_general_data ));
335	}
336
337	uint32_t nb_request_in = 0;
338	uint32_t nb_request_out = 0;
339
340	while (nb_request_out < _param->_nb_packet)
341	{
342	bool val = (((rand()%100)<percent_transaction_write_unit_in) and
343	(nb_request_in < _param->_nb_packet) and
344	not (request [nb_request_in]->_write_rd and
345	gpr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd]) and
346	not (request [nb_request_in]->_write_re and
347	spr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re]));
348
349	in_WRITE_UNIT_IN_VAL ->write(val);
350	if (val)
351	{
352	in_WRITE_UNIT_IN_CONTEXT_ID ->write(request [nb_request_in]->_context_id );
353	in_WRITE_UNIT_IN_FRONT_END_ID ->write(request [nb_request_in]->_front_end_id );
354	in_WRITE_UNIT_IN_OOO_ENGINE_ID->write(request [nb_request_in]->_ooo_engine_id);
355	in_WRITE_UNIT_IN_PACKET_ID ->write(request [nb_request_in]->_packet_id );
356	//in_WRITE_UNIT_IN_OPERATION ->write(request [nb_request_in]->_operation );
357	in_WRITE_UNIT_IN_TYPE ->write(request [nb_request_in]->_type );
358	in_WRITE_UNIT_IN_WRITE_RD ->write(request [nb_request_in]->_write_rd );
359	in_WRITE_UNIT_IN_NUM_REG_RD ->write(request [nb_request_in]->_num_reg_rd );
360	in_WRITE_UNIT_IN_DATA_RD ->write(request [nb_request_in]->_data_rd );
361	in_WRITE_UNIT_IN_WRITE_RE ->write(request [nb_request_in]->_write_re );
362	in_WRITE_UNIT_IN_NUM_REG_RE ->write(request [nb_request_in]->_num_reg_re );
363	in_WRITE_UNIT_IN_DATA_RE ->write(request [nb_request_in]->_data_re );
364	in_WRITE_UNIT_IN_EXCEPTION ->write(request [nb_request_in]->_exception );
365	in_WRITE_UNIT_IN_NO_SEQUENCE ->write(request [nb_request_in]->_no_sequence );
366	in_WRITE_UNIT_IN_ADDRESS ->write(request [nb_request_in]->_address );
367	}
368	in_WRITE_UNIT_OUT_ACK ->write((rand()%100)<percent_transaction_write_unit_out);
369	in_GPR_WRITE_ACK [0] ->write((rand()%100)<percent_transaction_gpr);
370	in_SPR_WRITE_ACK [0] ->write((rand()%100)<percent_transaction_spr);
371
372	SC_START(0);
373
374	// ======================================================================
375	// ======================================================================
376	// ======================================================================
377	if (out_GPR_WRITE_VAL [0]->read() and
378	in_GPR_WRITE_ACK [0]->read())
379	{
380	Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_GPR_WRITE_OOO_ENGINE_ID[0]->read():0;
381	Tgeneral_address_t num_reg = out_GPR_WRITE_NUM_REG [0]->read();
382	Tgeneral_data_t data = out_GPR_WRITE_DATA [0]->read();
383
384	LABEL(" * Accepted GPR_WRITE in register [%d][%d]", ooo_engine_id,num_reg);
385
386	TEST(bool , gpr_val [ooo_engine_id][num_reg], 0);
387	TEST(bool , gpr_use [ooo_engine_id][num_reg], 1);
388	TEST(Tgeneral_data_t, gpr [ooo_engine_id][num_reg], data);
389
390	gpr_val [ooo_engine_id][num_reg] = 1;
391	}
392
393	// ======================================================================
394	// ======================================================================
395	// ======================================================================
396	if (out_SPR_WRITE_VAL [0]->read() and
397	in_SPR_WRITE_ACK [0]->read())
398	{
399	Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_SPR_WRITE_OOO_ENGINE_ID[0]->read():0;
400	Tspecial_address_t num_reg = out_SPR_WRITE_NUM_REG [0]->read();
401	Tspecial_data_t data = out_SPR_WRITE_DATA [0]->read();
402
403	LABEL(" * Accepted SPR_WRITE in register [%d][%d]", ooo_engine_id,num_reg);
404
405	TEST(bool , spr_val [ooo_engine_id][num_reg], 0);
406	TEST(bool , spr_use [ooo_engine_id][num_reg], 1);
407	TEST(Tgeneral_data_t, spr [ooo_engine_id][num_reg], data);
408
409	spr_val [ooo_engine_id][num_reg] = 1;
410	}
411
412	// ======================================================================
413	// ======================================================================
414	// ======================================================================
415	for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
416	{
417	Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_BYPASS_WRITE_OOO_ENGINE_ID[i]->read():0;
418
419	if (out_BYPASS_WRITE_GPR_VAL [i]->read())
420	{
421	Tgeneral_address_t num_reg = out_BYPASS_WRITE_GPR_NUM_REG [i]->read(); // RD
422	Tgeneral_data_t data = out_BYPASS_WRITE_GPR_DATA [i]->read();
423
424	LABEL(" * Accepted BYPASS_WRITE in register [%d][%d] (GPR)", ooo_engine_id,num_reg);
425
426
427	TEST(bool , gpr_use [ooo_engine_id][num_reg], 1);
428	TEST(Tgeneral_data_t, gpr [ooo_engine_id][num_reg], data);
429	}
430	if (out_BYPASS_WRITE_SPR_VAL [i]->read())
431	{
432	Tspecial_address_t num_reg = out_BYPASS_WRITE_SPR_NUM_REG [i]->read(); // RE
433	Tspecial_data_t data = out_BYPASS_WRITE_SPR_DATA [i]->read();
434
435	LABEL(" * Accepted BYPASS_WRITE in register [%d][%d] (SPR)", ooo_engine_id,num_reg);
436
437	TEST(bool , spr_use [ooo_engine_id][num_reg], 1);
438	TEST(Tspecial_data_t, spr [ooo_engine_id][num_reg], data);
439	}
440	}
441
442	// ======================================================================
443	// ======================================================================
444	// ======================================================================
445	if ( in_WRITE_UNIT_IN_VAL->read() and
446	out_WRITE_UNIT_IN_ACK->read())
447	{
448	LABEL(" * Accepted WRITE_UNIT_IN [%d]",nb_request_in);
449	// std::cout << *request [nb_request_in] << std::endl;
450
451	if (request [nb_request_in]->_write_rd)
452	{
453	gpr_val [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = 0;
454	gpr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = 1;
455	gpr [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = request [nb_request_in]->_data_rd;
456	}
457	if (request [nb_request_in]->_write_re)
458	{
459	spr_val [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = 0;
460	spr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = 1;
461	spr [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = request [nb_request_in]->_data_re;
462	}
463	nb_request_in ++;
464	}
465
466	// ======================================================================
467	// ======================================================================
468	// ======================================================================
469	if (out_WRITE_UNIT_OUT_VAL->read() and
470	in_WRITE_UNIT_OUT_ACK->read())
471	{
472	Tcontext_t packet;
473	if (_param->_have_port_packet_id)
474	packet = out_WRITE_UNIT_OUT_PACKET_ID->read();
475	else
476	packet = 0;
477
478	LABEL(" * Accepted WRITE_UNIT_OUT [%d]",packet);
479	// std::cout << *request [packet] << std::endl;
480
481	if (request [packet]->_write_rd)
482	{
483	TEST(bool, gpr_val [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd], 1);
484	TEST(bool, gpr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd], 1);
485	gpr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd] = 0;
486	}
487	if (request [packet]->_write_re)
488	{
489	TEST(bool, spr_val [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re], 1);
490	TEST(bool, spr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re], 1);
491	spr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re] = 0;
492	}
493
494	if (_param->_have_port_context_id)
495	TEST(Tcontext_t , out_WRITE_UNIT_OUT_CONTEXT_ID ->read(), request [packet]->_context_id );
496	if (_param->_have_port_front_end_id)
497	TEST(Tcontext_t , out_WRITE_UNIT_OUT_FRONT_END_ID ->read(), request [packet]->_front_end_id );
498	if (_param->_have_port_ooo_engine_id)
499	TEST(Tcontext_t , out_WRITE_UNIT_OUT_OOO_ENGINE_ID->read(), request [packet]->_ooo_engine_id);
500
501	//TEST(Toperation_t , out_WRITE_UNIT_OUT_OPERATION ->read(), request [packet]->_operation );
502	//TEST(Ttype_t , out_WRITE_UNIT_OUT_TYPE ->read(), request [packet]->_type );
503	TEST(Tcontrol_t , out_WRITE_UNIT_OUT_FLAGS ->read(), request [packet]->_data_re );
504	TEST(Texception_t , out_WRITE_UNIT_OUT_EXCEPTION ->read(), request [packet]->_exception );
505	TEST(Tcontrol_t , out_WRITE_UNIT_OUT_NO_SEQUENCE ->read(), request [packet]->_no_sequence );
506	TEST(Tgeneral_data_t, out_WRITE_UNIT_OUT_ADDRESS ->read(), request [packet]->_address );
507
508	nb_request_out ++;
509	}
510
511	SC_START(1);
512	}
513
514	for (uint32_t i=0; i<_param->_nb_packet; i++)
515	delete request [i];
516
517	}
518
519
520	/********************************************************
521	* Simulation - End
522	********************************************************/
523
524	TEST_OK ("End of Simulation");
525	delete _time;
526
527	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
528
529	delete in_CLOCK;
530	delete in_NRESET;
531	#endif
532
533	delete _Write_unit;
534	#ifdef STATISTICS
535	delete _parameters_statistics;
536	#endif
537	}

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