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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/src/test.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 15 years ago
Almost complete design with Test and test platform
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1	/*
2	* $Id: test.cpp 88 2008-12-10 18:31:39Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 1
10	#define CYCLE_MAX (128*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Common/include/BitManipulation.h"
15	#include "Behavioural/include/Allocation.h"
16
17	class entry_t
18	{
19	public : Tcontext_t _context_id ;
20	public : Tcontext_t _front_end_id ;
21	public : Tcontext_t _ooo_engine_id;
22	public : Tpacket_t _packet_id ;
23	//public : Toperation_t _operation ;
24	public : Ttype_t _type ;
25	public : Tcontrol_t _write_rd ;
26	public : Tgeneral_address_t _num_reg_rd ;
27	public : Tgeneral_data_t _data_rd ;
28	public : Tcontrol_t _write_re ;
29	public : Tspecial_address_t _num_reg_re ;
30	public : Tspecial_data_t _data_re ;
31	public : Texception_t _exception ;
32	public : Tcontrol_t _no_sequence ;
33	public : Tgeneral_data_t _address ;
34
35	public : entry_t (Tcontext_t context_id ,
36	Tcontext_t front_end_id ,
37	Tcontext_t ooo_engine_id,
38	Tpacket_t packet_id ,
39	//Toperation_t operation ,
40	Ttype_t type ,
41	Tcontrol_t write_rd ,
42	Tgeneral_address_t num_reg_rd ,
43	Tgeneral_data_t data_rd ,
44	Tcontrol_t write_re ,
45	Tspecial_address_t num_reg_re ,
46	Tspecial_data_t data_re ,
47	Texception_t exception ,
48	Tcontrol_t no_sequence ,
49	Tgeneral_data_t address )
50	{
51	_context_id = context_id ;
52	_front_end_id = front_end_id ;
53	_ooo_engine_id = ooo_engine_id;
54	_packet_id = packet_id ;
55	//_operation = operation ;
56	_type = type ;
57	_write_rd = write_rd ;
58	_num_reg_rd = num_reg_rd ;
59	_data_rd = data_rd ;
60	_write_re = write_re ;
61	_num_reg_re = num_reg_re ;
62	_data_re = data_re ;
63	_exception = exception ;
64	_no_sequence = no_sequence ;
65	_address = address ;
66	};
67
68	friend std::ostream& operator<< (std::ostream& output_stream,
69	entry_t & x)
70	{
71	output_stream << " * _context_id : " << toString(x._context_id ) << std::endl
72	<< " * _front_end_id : " << toString(x._front_end_id ) << std::endl
73	<< " * _ooo_engine_id : " << toString(x._ooo_engine_id) << std::endl
74	<< " * _packet_id : " << toString(x._packet_id ) << std::endl
75	//<< " * _operation : " << toString(x._operation ) << std::endl
76	<< " * _type : " << toString(x._type ) << std::endl
77	<< " * _write_rd : " << toString(x._write_rd ) << std::endl
78	<< " * _num_reg_rd : " << toString(x._num_reg_rd ) << std::endl
79	<< " * _data_rd : " << toString(x._data_rd ) << std::endl
80	<< " * _write_re : " << toString(x._write_re ) << std::endl
81	<< " * _num_reg_re : " << toString(x._num_reg_re ) << std::endl
82	<< " * _data_re : " << toString(x._data_re ) << std::endl
83	<< " * _exception : " << toString(x._exception ) << std::endl
84	<< " * _no_sequence : " << toString(x._no_sequence ) << std::endl
85	<< " * _address : " << toString(x._address ) << std::endl;
86
87	return output_stream;
88	}
89	};
90
91
92	void test (string name,
93	morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::Parameters * _param)
94	{
95	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
96
97	#ifdef STATISTICS
98	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
99	#endif
100
101	Tusage_t _usage = USE_ALL;
102
103	// _usage = usage_unset(_usage,USE_SYSTEMC );
104	// _usage = usage_unset(_usage,USE_VHDL );
105	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
106	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
107	// _usage = usage_unset(_usage,USE_POSITION );
108	_usage = usage_unset(_usage,USE_STATISTICS );
109	// _usage = usage_unset(_usage,USE_INFORMATION );
110
111	Write_unit * _Write_unit = new Write_unit
112	(name.c_str(),
113	#ifdef STATISTICS
114	_parameters_statistics,
115	#endif
116	_param,
117	_usage);
118
119	#ifdef SYSTEMC
120	/*********************************************************************
121	* Déclarations des signaux
122	*********************************************************************/
123	string rename;
124
125	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
126	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
127
128	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_VAL ," in_WRITE_UNIT_IN_VAL" , Tcontrol_t );
129	ALLOC_SC_SIGNAL (out_WRITE_UNIT_IN_ACK ,"out_WRITE_UNIT_IN_ACK" , Tcontrol_t );
130	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_CONTEXT_ID ," in_WRITE_UNIT_IN_CONTEXT_ID" , Tcontext_t );
131	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_FRONT_END_ID ," in_WRITE_UNIT_IN_FRONT_END_ID" , Tcontext_t );
132	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_OOO_ENGINE_ID ," in_WRITE_UNIT_IN_OOO_ENGINE_ID" , Tcontext_t );
133	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_PACKET_ID ," in_WRITE_UNIT_IN_PACKET_ID" , Tpacket_t );
134	//ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_OPERATION ," in_WRITE_UNIT_IN_OPERATION" , Toperation_t );
135	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_TYPE ," in_WRITE_UNIT_IN_TYPE" , Ttype_t );
136	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_WRITE_RD ," in_WRITE_UNIT_IN_WRITE_RD" , Tcontrol_t );
137	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_NUM_REG_RD ," in_WRITE_UNIT_IN_NUM_REG_RD" , Tgeneral_address_t);
138	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_DATA_RD ," in_WRITE_UNIT_IN_DATA_RD" , Tgeneral_data_t );
139	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_WRITE_RE ," in_WRITE_UNIT_IN_WRITE_RE" , Tcontrol_t );
140	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_NUM_REG_RE ," in_WRITE_UNIT_IN_NUM_REG_RE" , Tspecial_address_t);
141	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_DATA_RE ," in_WRITE_UNIT_IN_DATA_RE" , Tspecial_data_t );
142	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_EXCEPTION ," in_WRITE_UNIT_IN_EXCEPTION" , Texception_t );
143	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_NO_SEQUENCE ," in_WRITE_UNIT_IN_NO_SEQUENCE" , Tcontrol_t );
144	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_ADDRESS ," in_WRITE_UNIT_IN_ADDRESS" , Tgeneral_data_t );
145	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_VAL ,"out_WRITE_UNIT_OUT_VAL" , Tcontrol_t );
146	ALLOC_SC_SIGNAL ( in_WRITE_UNIT_OUT_ACK ," in_WRITE_UNIT_OUT_ACK" , Tcontrol_t );
147	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_CONTEXT_ID ,"out_WRITE_UNIT_OUT_CONTEXT_ID" , Tcontext_t );
148	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_FRONT_END_ID ,"out_WRITE_UNIT_OUT_FRONT_END_ID" , Tcontext_t );
149	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_OOO_ENGINE_ID,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID", Tcontext_t );
150	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_PACKET_ID ,"out_WRITE_UNIT_OUT_PACKET_ID" , Tpacket_t );
151	//ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_OPERATION ,"out_WRITE_UNIT_OUT_OPERATION" , Toperation_t );
152	//ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_TYPE ,"out_WRITE_UNIT_OUT_TYPE" , Ttype_t );
153	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_FLAGS ,"out_WRITE_UNIT_OUT_FLAGS" , Tspecial_data_t );
154	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_EXCEPTION ,"out_WRITE_UNIT_OUT_EXCEPTION" , Texception_t );
155	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_NO_SEQUENCE ,"out_WRITE_UNIT_OUT_NO_SEQUENCE" , Tcontrol_t );
156	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_ADDRESS ,"out_WRITE_UNIT_OUT_ADDRESS" , Tgeneral_data_t );
157	ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_DATA ,"out_WRITE_UNIT_OUT_DATA" , Tgeneral_data_t );
158	ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write);
159	ALLOC1_SC_SIGNAL( in_GPR_WRITE_ACK ," in_GPR_WRITE_ACK" , Tcontrol_t , _param->_nb_gpr_write);
160	ALLOC1_SC_SIGNAL(out_GPR_WRITE_OOO_ENGINE_ID ,"out_GPR_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_gpr_write);
161	ALLOC1_SC_SIGNAL(out_GPR_WRITE_NUM_REG ,"out_GPR_WRITE_NUM_REG" , Tgeneral_address_t, _param->_nb_gpr_write);
162	ALLOC1_SC_SIGNAL(out_GPR_WRITE_DATA ,"out_GPR_WRITE_DATA" , Tgeneral_data_t , _param->_nb_gpr_write);
163	ALLOC1_SC_SIGNAL(out_SPR_WRITE_VAL ,"out_SPR_WRITE_VAL" , Tcontrol_t , _param->_nb_spr_write);
164	ALLOC1_SC_SIGNAL( in_SPR_WRITE_ACK ," in_SPR_WRITE_ACK" , Tcontrol_t , _param->_nb_spr_write);
165	ALLOC1_SC_SIGNAL(out_SPR_WRITE_OOO_ENGINE_ID ,"out_SPR_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_spr_write);
166	ALLOC1_SC_SIGNAL(out_SPR_WRITE_NUM_REG ,"out_SPR_WRITE_NUM_REG" , Tspecial_address_t, _param->_nb_spr_write);
167	ALLOC1_SC_SIGNAL(out_SPR_WRITE_DATA ,"out_SPR_WRITE_DATA" , Tspecial_data_t , _param->_nb_spr_write);
168	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_OOO_ENGINE_ID ,"out_BYPASS_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_bypass_write);
169	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_VAL ,"out_BYPASS_WRITE_GPR_VAL" , Tcontrol_t , _param->_nb_bypass_write);
170	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_NUM_REG ,"out_BYPASS_WRITE_GPR_NUM_REG" , Tgeneral_address_t, _param->_nb_bypass_write);
171	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_DATA ,"out_BYPASS_WRITE_GPR_DATA" , Tgeneral_data_t , _param->_nb_bypass_write);
172	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_VAL ,"out_BYPASS_WRITE_SPR_VAL" , Tcontrol_t , _param->_nb_bypass_write);
173	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_NUM_REG ,"out_BYPASS_WRITE_SPR_NUM_REG" , Tspecial_address_t, _param->_nb_bypass_write);
174	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_DATA ,"out_BYPASS_WRITE_SPR_DATA" , Tspecial_data_t , _param->_nb_bypass_write);
175
176
177	/********************************************************
178	* Instanciation
179	********************************************************/
180
181	msg(_("<%s> : Instanciation of _Write_unit.\n"),name.c_str());
182
183	((_Write_unit->in_CLOCK)) ((in_CLOCK));
184	((_Write_unit->in_NRESET)) ((in_NRESET));
185
186	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_VAL );
187	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_IN_ACK );
188	if (_param->_have_port_context_id)
189	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_CONTEXT_ID );
190	if (_param->_have_port_front_end_id)
191	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_FRONT_END_ID );
192	if (_param->_have_port_ooo_engine_id)
193	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_OOO_ENGINE_ID );
194	if (_param->_have_port_rob_ptr)
195	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_PACKET_ID );
196	//INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_OPERATION );
197	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_TYPE );
198	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_WRITE_RD );
199	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_NUM_REG_RD );
200	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_DATA_RD );
201	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_WRITE_RE );
202	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_NUM_REG_RE );
203	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_DATA_RE );
204	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_EXCEPTION );
205	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_NO_SEQUENCE );
206	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_ADDRESS );
207	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_VAL );
208	INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_OUT_ACK );
209	if (_param->_have_port_context_id)
210	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_CONTEXT_ID );
211	if (_param->_have_port_front_end_id)
212	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_FRONT_END_ID );
213	if (_param->_have_port_ooo_engine_id)
214	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_OOO_ENGINE_ID);
215	if (_param->_have_port_rob_ptr)
216	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_PACKET_ID );
217	//INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_OPERATION );
218	//INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_TYPE );
219	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_FLAGS );
220	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_EXCEPTION );
221	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_NO_SEQUENCE );
222	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_ADDRESS );
223	INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_DATA );
224	INSTANCE1_SC_SIGNAL(_Write_unit, out_GPR_WRITE_VAL , _param->_nb_gpr_write);
225	INSTANCE1_SC_SIGNAL(_Write_unit, in_GPR_WRITE_ACK , _param->_nb_gpr_write);
226	if (_param->_have_port_ooo_engine_id)
227	INSTANCE1_SC_SIGNAL(_Write_unit, out_GPR_WRITE_OOO_ENGINE_ID , _param->_nb_gpr_write);
228	INSTANCE1_SC_SIGNAL(_Write_unit, out_GPR_WRITE_NUM_REG , _param->_nb_gpr_write);
229	INSTANCE1_SC_SIGNAL(_Write_unit, out_GPR_WRITE_DATA , _param->_nb_gpr_write);
230	INSTANCE1_SC_SIGNAL(_Write_unit, out_SPR_WRITE_VAL , _param->_nb_spr_write);
231	INSTANCE1_SC_SIGNAL(_Write_unit, in_SPR_WRITE_ACK , _param->_nb_spr_write);
232	if (_param->_have_port_ooo_engine_id)
233	INSTANCE1_SC_SIGNAL(_Write_unit, out_SPR_WRITE_OOO_ENGINE_ID , _param->_nb_spr_write);
234	INSTANCE1_SC_SIGNAL(_Write_unit, out_SPR_WRITE_NUM_REG , _param->_nb_spr_write);
235	INSTANCE1_SC_SIGNAL(_Write_unit, out_SPR_WRITE_DATA , _param->_nb_spr_write);
236	if (_param->_have_port_ooo_engine_id)
237	INSTANCE1_SC_SIGNAL(_Write_unit, out_BYPASS_WRITE_OOO_ENGINE_ID , _param->_nb_bypass_write);
238	INSTANCE1_SC_SIGNAL(_Write_unit, out_BYPASS_WRITE_GPR_VAL , _param->_nb_bypass_write);
239	INSTANCE1_SC_SIGNAL(_Write_unit, out_BYPASS_WRITE_GPR_NUM_REG , _param->_nb_bypass_write);
240	INSTANCE1_SC_SIGNAL(_Write_unit, out_BYPASS_WRITE_GPR_DATA , _param->_nb_bypass_write);
241	INSTANCE1_SC_SIGNAL(_Write_unit, out_BYPASS_WRITE_SPR_VAL , _param->_nb_bypass_write);
242	INSTANCE1_SC_SIGNAL(_Write_unit, out_BYPASS_WRITE_SPR_NUM_REG , _param->_nb_bypass_write);
243	INSTANCE1_SC_SIGNAL(_Write_unit, out_BYPASS_WRITE_SPR_DATA , _param->_nb_bypass_write);
244
245	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
246
247	Time * _time = new Time();
248
249	/********************************************************
250	* Simulation - Begin
251	********************************************************/
252
253	// Initialisation
254
255	const uint32_t seed = 0;
256	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
257
258	srand(seed);
259
260	const int32_t percent_transaction_write_unit_in = 75;
261	const int32_t percent_transaction_write_unit_out = 75;
262	const int32_t percent_transaction_gpr = 75;
263	const int32_t percent_transaction_spr = 75;
264
265	bool gpr_val [_param->_nb_ooo_engine][_param->_nb_general_register];
266	bool gpr_use [_param->_nb_ooo_engine][_param->_nb_general_register];
267	Tgeneral_data_t gpr [_param->_nb_ooo_engine][_param->_nb_general_register];
268	bool spr_val [_param->_nb_ooo_engine][_param->_nb_special_register];
269	bool spr_use [_param->_nb_ooo_engine][_param->_nb_special_register];
270	Tgeneral_data_t spr [_param->_nb_ooo_engine][_param->_nb_special_register];
271
272	entry_t * request [_param->_nb_packet];
273
274	SC_START(0);
275	LABEL("Initialisation");
276
277	LABEL("Reset");
278	in_NRESET->write(0);
279	SC_START(5);
280	in_NRESET->write(1);
281
282	LABEL("Loop of Test");
283
284	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
285	{
286	LABEL("Iteration %d",iteration);
287
288	for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
289	{
290	for (uint32_t j=0; j<_param->_nb_general_register; j++)
291	{
292	gpr_val [i][j] = 0;
293	gpr_use [i][j] = 0;
294	gpr [i][j] = rand();
295	}
296	for (uint32_t j=0; j<_param->_nb_special_register; j++)
297	{
298	spr_val [i][j] = 0;
299	spr_use [i][j] = 0;
300	spr [i][j] = rand();
301	}
302	}
303
304	for (uint32_t i=0; i<_param->_nb_packet; i++)
305	{
306	request [i] = new entry_t (range<Tcontext_t >(rand(),_param->_size_context_id ),
307	range<Tcontext_t >(rand(),_param->_size_front_end_id ),
308	range<Tcontext_t >(rand(),_param->_size_ooo_engine_id ),
309	i,
310	//range<Toperation_t >(rand(),_param->_size_operation ),
311	range<Ttype_t >(rand(),_param->_size_type ),
312	range<Tcontrol_t >(rand(),1 ),
313	range<Tgeneral_address_t>(rand(),_param->_size_general_register),
314	range<Tgeneral_data_t >(rand(),_param->_size_general_data ),
315	range<Tcontrol_t >(rand(),1 ),
316	range<Tspecial_address_t>(rand(),_param->_size_special_register),
317	range<Tspecial_data_t >(rand(),_param->_size_special_data ),
318	range<Texception_t >(rand(),_param->_size_exception ),
319	range<Tcontrol_t >(rand(),1 ),
320	range<Tgeneral_data_t >(rand(),_param->_size_general_data ));
321	}
322
323	uint32_t nb_request_in = 0;
324	uint32_t nb_request_out = 0;
325
326	while (nb_request_out < _param->_nb_packet)
327	{
328	bool val = (((rand()%100)<percent_transaction_write_unit_in) and
329	(nb_request_in < _param->_nb_packet) and
330	not (request [nb_request_in]->_write_rd and
331	gpr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd]) and
332	not (request [nb_request_in]->_write_re and
333	spr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re]));
334
335	in_WRITE_UNIT_IN_VAL ->write(val);
336	if (val)
337	{
338	in_WRITE_UNIT_IN_CONTEXT_ID ->write(request [nb_request_in]->_context_id );
339	in_WRITE_UNIT_IN_FRONT_END_ID ->write(request [nb_request_in]->_front_end_id );
340	in_WRITE_UNIT_IN_OOO_ENGINE_ID->write(request [nb_request_in]->_ooo_engine_id);
341	in_WRITE_UNIT_IN_PACKET_ID ->write(request [nb_request_in]->_packet_id );
342	//in_WRITE_UNIT_IN_OPERATION ->write(request [nb_request_in]->_operation );
343	in_WRITE_UNIT_IN_TYPE ->write(request [nb_request_in]->_type );
344	in_WRITE_UNIT_IN_WRITE_RD ->write(request [nb_request_in]->_write_rd );
345	in_WRITE_UNIT_IN_NUM_REG_RD ->write(request [nb_request_in]->_num_reg_rd );
346	in_WRITE_UNIT_IN_DATA_RD ->write(request [nb_request_in]->_data_rd );
347	in_WRITE_UNIT_IN_WRITE_RE ->write(request [nb_request_in]->_write_re );
348	in_WRITE_UNIT_IN_NUM_REG_RE ->write(request [nb_request_in]->_num_reg_re );
349	in_WRITE_UNIT_IN_DATA_RE ->write(request [nb_request_in]->_data_re );
350	in_WRITE_UNIT_IN_EXCEPTION ->write(request [nb_request_in]->_exception );
351	in_WRITE_UNIT_IN_NO_SEQUENCE ->write(request [nb_request_in]->_no_sequence );
352	in_WRITE_UNIT_IN_ADDRESS ->write(request [nb_request_in]->_address );
353	}
354	in_WRITE_UNIT_OUT_ACK ->write((rand()%100)<percent_transaction_write_unit_out);
355	in_GPR_WRITE_ACK [0] ->write((rand()%100)<percent_transaction_gpr);
356	in_SPR_WRITE_ACK [0] ->write((rand()%100)<percent_transaction_spr);
357
358	SC_START(0);
359
360	// ======================================================================
361	// ======================================================================
362	// ======================================================================
363	if (out_GPR_WRITE_VAL [0]->read() and
364	in_GPR_WRITE_ACK [0]->read())
365	{
366	Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_GPR_WRITE_OOO_ENGINE_ID[0]->read():0;
367	Tgeneral_address_t num_reg = out_GPR_WRITE_NUM_REG [0]->read();
368	Tgeneral_data_t data = out_GPR_WRITE_DATA [0]->read();
369
370	LABEL(" * Accepted GPR_WRITE in register [%d][%d]", ooo_engine_id,num_reg);
371
372	TEST(bool , gpr_val [ooo_engine_id][num_reg], 0);
373	TEST(bool , gpr_use [ooo_engine_id][num_reg], 1);
374	TEST(Tgeneral_data_t, gpr [ooo_engine_id][num_reg], data);
375
376	gpr_val [ooo_engine_id][num_reg] = 1;
377	}
378
379	// ======================================================================
380	// ======================================================================
381	// ======================================================================
382	if (out_SPR_WRITE_VAL [0]->read() and
383	in_SPR_WRITE_ACK [0]->read())
384	{
385	Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_SPR_WRITE_OOO_ENGINE_ID[0]->read():0;
386	Tspecial_address_t num_reg = out_SPR_WRITE_NUM_REG [0]->read();
387	Tspecial_data_t data = out_SPR_WRITE_DATA [0]->read();
388
389	LABEL(" * Accepted SPR_WRITE in register [%d][%d]", ooo_engine_id,num_reg);
390
391	TEST(bool , spr_val [ooo_engine_id][num_reg], 0);
392	TEST(bool , spr_use [ooo_engine_id][num_reg], 1);
393	TEST(Tgeneral_data_t, spr [ooo_engine_id][num_reg], data);
394
395	spr_val [ooo_engine_id][num_reg] = 1;
396	}
397
398	// ======================================================================
399	// ======================================================================
400	// ======================================================================
401	for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
402	{
403	Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_BYPASS_WRITE_OOO_ENGINE_ID[i]->read():0;
404
405	if (out_BYPASS_WRITE_GPR_VAL [i]->read())
406	{
407	Tgeneral_address_t num_reg = out_BYPASS_WRITE_GPR_NUM_REG [i]->read(); // RD
408	Tgeneral_data_t data = out_BYPASS_WRITE_GPR_DATA [i]->read();
409
410	LABEL(" * Accepted BYPASS_WRITE in register [%d][%d] (GPR)", ooo_engine_id,num_reg);
411
412
413	TEST(bool , gpr_use [ooo_engine_id][num_reg], 1);
414	TEST(Tgeneral_data_t, gpr [ooo_engine_id][num_reg], data);
415	}
416	if (out_BYPASS_WRITE_SPR_VAL [i]->read())
417	{
418	Tspecial_address_t num_reg = out_BYPASS_WRITE_SPR_NUM_REG [i]->read(); // RE
419	Tspecial_data_t data = out_BYPASS_WRITE_SPR_DATA [i]->read();
420
421	LABEL(" * Accepted BYPASS_WRITE in register [%d][%d] (SPR)", ooo_engine_id,num_reg);
422
423	TEST(bool , spr_use [ooo_engine_id][num_reg], 1);
424	TEST(Tspecial_data_t, spr [ooo_engine_id][num_reg], data);
425	}
426	}
427
428	// ======================================================================
429	// ======================================================================
430	// ======================================================================
431	if ( in_WRITE_UNIT_IN_VAL->read() and
432	out_WRITE_UNIT_IN_ACK->read())
433	{
434	LABEL(" * Accepted WRITE_UNIT_IN [%d]",nb_request_in);
435	// std::cout << *request [nb_request_in] << std::endl;
436
437	if (request [nb_request_in]->_write_rd)
438	{
439	gpr_val [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = 0;
440	gpr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = 1;
441	gpr [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = request [nb_request_in]->_data_rd;
442	}
443	if (request [nb_request_in]->_write_re)
444	{
445	spr_val [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = 0;
446	spr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = 1;
447	spr [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = request [nb_request_in]->_data_re;
448	}
449	nb_request_in ++;
450	}
451
452	// ======================================================================
453	// ======================================================================
454	// ======================================================================
455	if (out_WRITE_UNIT_OUT_VAL->read() and
456	in_WRITE_UNIT_OUT_ACK->read())
457	{
458	Tcontext_t packet;
459	if (_param->_have_port_rob_ptr)
460	packet = out_WRITE_UNIT_OUT_PACKET_ID->read();
461	else
462	packet = 0;
463
464	LABEL(" * Accepted WRITE_UNIT_OUT [%d]",packet);
465	// std::cout << *request [packet] << std::endl;
466
467	if (request [packet]->_write_rd)
468	{
469	TEST(bool, gpr_val [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd], 1);
470	TEST(bool, gpr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd], 1);
471	gpr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd] = 0;
472	}
473	if (request [packet]->_write_re)
474	{
475	TEST(bool, spr_val [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re], 1);
476	TEST(bool, spr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re], 1);
477	spr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re] = 0;
478	}
479
480	if (_param->_have_port_context_id)
481	TEST(Tcontext_t , out_WRITE_UNIT_OUT_CONTEXT_ID ->read(), request [packet]->_context_id );
482	if (_param->_have_port_front_end_id)
483	TEST(Tcontext_t , out_WRITE_UNIT_OUT_FRONT_END_ID ->read(), request [packet]->_front_end_id );
484	if (_param->_have_port_ooo_engine_id)
485	TEST(Tcontext_t , out_WRITE_UNIT_OUT_OOO_ENGINE_ID->read(), request [packet]->_ooo_engine_id);
486
487	//TEST(Toperation_t , out_WRITE_UNIT_OUT_OPERATION ->read(), request [packet]->_operation );
488	//TEST(Ttype_t , out_WRITE_UNIT_OUT_TYPE ->read(), request [packet]->_type );
489	TEST(Tcontrol_t , out_WRITE_UNIT_OUT_FLAGS ->read(), request [packet]->_data_re );
490	TEST(Texception_t , out_WRITE_UNIT_OUT_EXCEPTION ->read(), request [packet]->_exception );
491	TEST(Tcontrol_t , out_WRITE_UNIT_OUT_NO_SEQUENCE ->read(), request [packet]->_no_sequence );
492	TEST(Tgeneral_data_t, out_WRITE_UNIT_OUT_ADDRESS ->read(), request [packet]->_address );
493	TEST(Tgeneral_data_t, out_WRITE_UNIT_OUT_DATA ->read(), request [packet]->_data_rd );
494
495	nb_request_out ++;
496	}
497
498	SC_START(1);
499	}
500
501	for (uint32_t i=0; i<_param->_nb_packet; i++)
502	delete request [i];
503
504	}
505
506
507	/********************************************************
508	* Simulation - End
509	********************************************************/
510
511	TEST_OK ("End of Simulation");
512	delete _time;
513
514	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
515
516	delete in_CLOCK;
517	delete in_NRESET;
518	#endif
519
520	delete _Write_unit;
521	#ifdef STATISTICS
522	delete _parameters_statistics;
523	#endif
524	}

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