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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/test.cpp @ 74

Last change on this file since 74 was 74, checked in by rosiere, 16 years ago
New component : Read_unit (instance between a write queue and a optionnal execute_queue)
File size: 29.3 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/include/test.h"
10	#include "Common/include/Test.h"
11	#include "Common/include/BitManipulation.h"
12	#include "Behavioural/include/Allocation.h"
13
14	#define NB_ITERATION 1
15	#define CYCLE_MAX (128*NB_ITERATION)
16
17	#define LABEL(str...) \
18	{ \
19	msg (_("{%d} "),static_cast<uint32_t>(sc_simulation_time())); \
20	msg (str); \
21	msg (_("\n")); \
22	} while(0)
23
24	#define SC_START(cycle_offset) \
25	do \
26	{ \
27	/cout << "SC_START (begin)" << endl;/ \
28	\
29	uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
30	if (cycle_offset != 0) \
31	{ \
32	cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \
33	} \
34	\
35	if (cycle_current > CYCLE_MAX) \
36	{ \
37	TEST_KO("Maximal cycles Reached"); \
38	} \
39	\
40	sc_start(cycle_offset); \
41	\
42	/cout << "SC_START (end )" << endl;/ \
43	} while(0)
44
45	class entry_t
46	{
47	public : Tcontext_t _context_id ;
48	public : Tcontext_t _front_end_id ;
49	public : Tcontext_t _ooo_engine_id;
50	public : Tpacket_t _packet_id ;
51	//public : Toperation_t _operation ;
52	//public : Ttype_t _type ;
53	public : Tcontrol_t _write_rd ;
54	public : Tgeneral_address_t _num_reg_rd ;
55	public : Tgeneral_data_t _data_rd ;
56	public : Tcontrol_t _write_re ;
57	public : Tspecial_address_t _num_reg_re ;
58	public : Tspecial_data_t _data_re ;
59	public : Texception_t _exception ;
60	public : Tcontrol_t _no_sequence ;
61	public : Tgeneral_data_t _address ;
62
63	public : entry_t (Tcontext_t context_id ,
64	Tcontext_t front_end_id ,
65	Tcontext_t ooo_engine_id,
66	Tpacket_t packet_id ,
67	//Toperation_t operation ,
68	//Ttype_t type ,
69	Tcontrol_t write_rd ,
70	Tgeneral_address_t num_reg_rd ,
71	Tgeneral_data_t data_rd ,
72	Tcontrol_t write_re ,
73	Tspecial_address_t num_reg_re ,
74	Tspecial_data_t data_re ,
75	Texception_t exception ,
76	Tcontrol_t no_sequence ,
77	Tgeneral_data_t address )
78	{
79	_context_id = context_id ;
80	_front_end_id = front_end_id ;
81	_ooo_engine_id = ooo_engine_id;
82	_packet_id = packet_id ;
83	//_operation = operation ;
84	//_type = type ;
85	_write_rd = write_rd ;
86	_num_reg_rd = num_reg_rd ;
87	_data_rd = data_rd ;
88	_write_re = write_re ;
89	_num_reg_re = num_reg_re ;
90	_data_re = data_re ;
91	_exception = exception ;
92	_no_sequence = no_sequence ;
93	_address = address ;
94	};
95
96	friend std::ostream& operator<< (std::ostream& output_stream,
97	entry_t & x)
98	{
99	output_stream << " * _context_id : " << toString(x._context_id ) << std::endl
100	<< " * _front_end_id : " << toString(x._front_end_id ) << std::endl
101	<< " * _ooo_engine_id : " << toString(x._ooo_engine_id) << std::endl
102	<< " * _packet_id : " << toString(x._packet_id ) << std::endl
103	//<< " * _operation : " << toString(x._operation ) << std::endl
104	//<< " * _type : " << toString(x._type ) << std::endl
105	<< " * _write_rd : " << toString(x._write_rd ) << std::endl
106	<< " * _num_reg_rd : " << toString(x._num_reg_rd ) << std::endl
107	<< " * _data_rd : " << toString(x._data_rd ) << std::endl
108	<< " * _write_re : " << toString(x._write_re ) << std::endl
109	<< " * _num_reg_re : " << toString(x._num_reg_re ) << std::endl
110	<< " * _data_re : " << toString(x._data_re ) << std::endl
111	<< " * _exception : " << toString(x._exception ) << std::endl
112	<< " * _no_sequence : " << toString(x._no_sequence ) << std::endl
113	<< " * _address : " << toString(x._address ) << std::endl;
114
115	return output_stream;
116	}
117	};
118
119	void test (string name,
120	morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Parameters * _param)
121	{
122	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
123
124	#ifdef STATISTICS
125	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
126	#endif
127
128
129	Write_queue * _Write_queue = new Write_queue (name.c_str(),
130	#ifdef STATISTICS
131	_parameters_statistics,
132	#endif
133	_param);
134
135	#ifdef SYSTEMC
136	/*********************************************************************
137	* Déclarations des signaux
138	*********************************************************************/
139	string rename;
140
141	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
142	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
143
144	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_VAL ," in_WRITE_QUEUE_IN_VAL" , Tcontrol_t );
145	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_IN_ACK ,"out_WRITE_QUEUE_IN_ACK" , Tcontrol_t );
146	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_CONTEXT_ID ," in_WRITE_QUEUE_IN_CONTEXT_ID" , Tcontext_t );
147	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_FRONT_END_ID ," in_WRITE_QUEUE_IN_FRONT_END_ID" , Tcontext_t );
148	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_OOO_ENGINE_ID ," in_WRITE_QUEUE_IN_OOO_ENGINE_ID" , Tcontext_t );
149	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_PACKET_ID ," in_WRITE_QUEUE_IN_PACKET_ID" , Tpacket_t );
150	//ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_OPERATION ," in_WRITE_QUEUE_IN_OPERATION" , Toperation_t );
151	//ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_TYPE ," in_WRITE_QUEUE_IN_TYPE" , Ttype_t );
152	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_WRITE_RD ," in_WRITE_QUEUE_IN_WRITE_RD" , Tcontrol_t );
153	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NUM_REG_RD ," in_WRITE_QUEUE_IN_NUM_REG_RD" , Tgeneral_address_t);
154	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_DATA_RD ," in_WRITE_QUEUE_IN_DATA_RD" , Tgeneral_data_t );
155	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_WRITE_RE ," in_WRITE_QUEUE_IN_WRITE_RE" , Tcontrol_t );
156	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NUM_REG_RE ," in_WRITE_QUEUE_IN_NUM_REG_RE" , Tspecial_address_t);
157	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_DATA_RE ," in_WRITE_QUEUE_IN_DATA_RE" , Tspecial_data_t );
158	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_EXCEPTION ," in_WRITE_QUEUE_IN_EXCEPTION" , Texception_t );
159	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NO_SEQUENCE ," in_WRITE_QUEUE_IN_NO_SEQUENCE" , Tcontrol_t );
160	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_ADDRESS ," in_WRITE_QUEUE_IN_ADDRESS" , Tgeneral_data_t );
161	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_VAL ,"out_WRITE_QUEUE_OUT_VAL" , Tcontrol_t );
162	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_OUT_ACK ," in_WRITE_QUEUE_OUT_ACK" , Tcontrol_t );
163	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_CONTEXT_ID ,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , Tcontext_t );
164	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_FRONT_END_ID ,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , Tcontext_t );
165	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_OOO_ENGINE_ID,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", Tcontext_t );
166	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_PACKET_ID ,"out_WRITE_QUEUE_OUT_PACKET_ID" , Tpacket_t );
167	//ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_OPERATION ,"out_WRITE_QUEUE_OUT_OPERATION" , Toperation_t );
168	//ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_TYPE ,"out_WRITE_QUEUE_OUT_TYPE" , Ttype_t );
169	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_FLAGS ,"out_WRITE_QUEUE_OUT_FLAGS" , Tspecial_data_t );
170	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_EXCEPTION ,"out_WRITE_QUEUE_OUT_EXCEPTION" , Texception_t );
171	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , Tcontrol_t );
172	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_ADDRESS ,"out_WRITE_QUEUE_OUT_ADDRESS" , Tgeneral_data_t );
173	ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write);
174	ALLOC1_SC_SIGNAL( in_GPR_WRITE_ACK ," in_GPR_WRITE_ACK" , Tcontrol_t , _param->_nb_gpr_write);
175	ALLOC1_SC_SIGNAL(out_GPR_WRITE_OOO_ENGINE_ID ,"out_GPR_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_gpr_write);
176	ALLOC1_SC_SIGNAL(out_GPR_WRITE_NUM_REG ,"out_GPR_WRITE_NUM_REG" , Tgeneral_address_t, _param->_nb_gpr_write);
177	ALLOC1_SC_SIGNAL(out_GPR_WRITE_DATA ,"out_GPR_WRITE_DATA" , Tgeneral_data_t , _param->_nb_gpr_write);
178	ALLOC1_SC_SIGNAL(out_SPR_WRITE_VAL ,"out_SPR_WRITE_VAL" , Tcontrol_t , _param->_nb_spr_write);
179	ALLOC1_SC_SIGNAL( in_SPR_WRITE_ACK ," in_SPR_WRITE_ACK" , Tcontrol_t , _param->_nb_spr_write);
180	ALLOC1_SC_SIGNAL(out_SPR_WRITE_OOO_ENGINE_ID ,"out_SPR_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_spr_write);
181	ALLOC1_SC_SIGNAL(out_SPR_WRITE_NUM_REG ,"out_SPR_WRITE_NUM_REG" , Tspecial_address_t, _param->_nb_spr_write);
182	ALLOC1_SC_SIGNAL(out_SPR_WRITE_DATA ,"out_SPR_WRITE_DATA" , Tspecial_data_t , _param->_nb_spr_write);
183	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_OOO_ENGINE_ID ,"out_BYPASS_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_bypass_write);
184	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_VAL ,"out_BYPASS_WRITE_GPR_VAL" , Tcontrol_t , _param->_nb_bypass_write);
185	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_NUM_REG ,"out_BYPASS_WRITE_GPR_NUM_REG" , Tgeneral_address_t, _param->_nb_bypass_write);
186	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_DATA ,"out_BYPASS_WRITE_GPR_DATA" , Tgeneral_data_t , _param->_nb_bypass_write);
187	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_VAL ,"out_BYPASS_WRITE_SPR_VAL" , Tcontrol_t , _param->_nb_bypass_write);
188	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_NUM_REG ,"out_BYPASS_WRITE_SPR_NUM_REG" , Tspecial_address_t, _param->_nb_bypass_write);
189	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_DATA ,"out_BYPASS_WRITE_SPR_DATA" , Tspecial_data_t , _param->_nb_bypass_write);
190
191	/********************************************************
192	* Instanciation
193	********************************************************/
194
195	msg(_("<%s> : Instanciation of _Write_queue.\n"),name.c_str());
196
197	((_Write_queue->in_CLOCK)) ((in_CLOCK));
198	((_Write_queue->in_NRESET)) ((in_NRESET));
199
200	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_VAL );
201	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_IN_ACK );
202	if (_param->_have_port_context_id)
203	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_CONTEXT_ID );
204	if (_param->_have_port_front_end_id)
205	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_FRONT_END_ID );
206	if (_param->_have_port_ooo_engine_id)
207	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_OOO_ENGINE_ID );
208	if (_param->_have_port_packet_id)
209	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_PACKET_ID );
210	//INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_OPERATION );
211	//INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_TYPE );
212	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_WRITE_RD );
213	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_NUM_REG_RD );
214	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_DATA_RD );
215	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_WRITE_RE );
216	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_NUM_REG_RE );
217	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_DATA_RE );
218	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_EXCEPTION );
219	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_NO_SEQUENCE );
220	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_ADDRESS );
221	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_VAL );
222	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_OUT_ACK );
223	if (_param->_have_port_context_id)
224	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_CONTEXT_ID );
225	if (_param->_have_port_front_end_id)
226	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_FRONT_END_ID );
227	if (_param->_have_port_ooo_engine_id)
228	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_OOO_ENGINE_ID);
229	if (_param->_have_port_packet_id)
230	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_PACKET_ID );
231	//INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_OPERATION );
232	//INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_TYPE );
233	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_FLAGS );
234	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_EXCEPTION );
235	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_NO_SEQUENCE );
236	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_ADDRESS );
237	INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_VAL , _param->_nb_gpr_write);
238	INSTANCE1_SC_SIGNAL(_Write_queue, in_GPR_WRITE_ACK , _param->_nb_gpr_write);
239	if (_param->_have_port_ooo_engine_id)
240	INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_OOO_ENGINE_ID , _param->_nb_gpr_write);
241	INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_NUM_REG , _param->_nb_gpr_write);
242	INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_DATA , _param->_nb_gpr_write);
243	INSTANCE1_SC_SIGNAL(_Write_queue, out_SPR_WRITE_VAL , _param->_nb_spr_write);
244	INSTANCE1_SC_SIGNAL(_Write_queue, in_SPR_WRITE_ACK , _param->_nb_spr_write);
245	if (_param->_have_port_ooo_engine_id)
246	INSTANCE1_SC_SIGNAL(_Write_queue, out_SPR_WRITE_OOO_ENGINE_ID , _param->_nb_spr_write);
247	INSTANCE1_SC_SIGNAL(_Write_queue, out_SPR_WRITE_NUM_REG , _param->_nb_spr_write);
248	INSTANCE1_SC_SIGNAL(_Write_queue, out_SPR_WRITE_DATA , _param->_nb_spr_write);
249	if (_param->_have_port_ooo_engine_id)
250	INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_OOO_ENGINE_ID , _param->_nb_bypass_write);
251	INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_GPR_VAL , _param->_nb_bypass_write);
252	INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_GPR_NUM_REG , _param->_nb_bypass_write);
253	INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_GPR_DATA , _param->_nb_bypass_write);
254	INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_SPR_VAL , _param->_nb_bypass_write);
255	INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_SPR_NUM_REG , _param->_nb_bypass_write);
256	INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_SPR_DATA , _param->_nb_bypass_write);
257
258	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
259
260	Time * _time = new Time();
261
262	/********************************************************
263	* Simulation - Begin
264	********************************************************/
265
266	// Initialisation
267
268	const uint32_t seed = 0;
269	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
270
271	srand(seed);
272
273	const int32_t percent_transaction_write_queue_in = 75;
274	const int32_t percent_transaction_write_queue_out = 75;
275	const int32_t percent_transaction_gpr = 75;
276	const int32_t percent_transaction_spr = 75;
277
278	bool gpr_val [_param->_nb_ooo_engine][_param->_nb_general_register];
279	bool gpr_use [_param->_nb_ooo_engine][_param->_nb_general_register];
280	Tgeneral_data_t gpr [_param->_nb_ooo_engine][_param->_nb_general_register];
281	bool spr_val [_param->_nb_ooo_engine][_param->_nb_special_register];
282	bool spr_use [_param->_nb_ooo_engine][_param->_nb_special_register];
283	Tgeneral_data_t spr [_param->_nb_ooo_engine][_param->_nb_special_register];
284
285	entry_t * request [_param->_nb_packet];
286
287	SC_START(0);
288	LABEL("Initialisation");
289
290	LABEL("Reset");
291	in_NRESET->write(0);
292	SC_START(5);
293	in_NRESET->write(1);
294
295	LABEL("Loop of Test");
296
297	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
298	{
299	LABEL("Iteration %d",iteration);
300
301	for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
302	{
303	for (uint32_t j=0; j<_param->_nb_general_register; j++)
304	{
305	gpr_val [i][j] = 0;
306	gpr_use [i][j] = 0;
307	gpr [i][j] = rand();
308	}
309	for (uint32_t j=0; j<_param->_nb_special_register; j++)
310	{
311	spr_val [i][j] = 0;
312	spr_use [i][j] = 0;
313	spr [i][j] = rand();
314	}
315	}
316
317	for (uint32_t i=0; i<_param->_nb_packet; i++)
318	{
319	request [i] = new entry_t (range<Tcontext_t >(rand(),_param->_size_context_id ),
320	range<Tcontext_t >(rand(),_param->_size_front_end_id ),
321	range<Tcontext_t >(rand(),_param->_size_ooo_engine_id ),
322	i,
323	//range<Toperation_t >(rand(),_param->_size_operation ),
324	//range<Ttype_t >(rand(),_param->_size_type ),
325	range<Tcontrol_t >(rand(),1 ),
326	range<Tgeneral_address_t>(rand(),_param->_size_general_register),
327	range<Tgeneral_data_t >(rand(),_param->_size_general_data ),
328	range<Tcontrol_t >(rand(),1 ),
329	range<Tspecial_address_t>(rand(),_param->_size_special_register),
330	range<Tspecial_data_t >(rand(),_param->_size_special_data ),
331	range<Texception_t >(rand(),_param->_size_exception ),
332	range<Tcontrol_t >(rand(),1 ),
333	range<Tgeneral_data_t >(rand(),_param->_size_general_data ));
334	}
335
336	uint32_t nb_request_in = 0;
337	uint32_t nb_request_out = 0;
338
339	while (nb_request_out < _param->_nb_packet)
340	{
341	bool val = (((rand()%100)<percent_transaction_write_queue_in) and
342	(nb_request_in < _param->_nb_packet) and
343	not (request [nb_request_in]->_write_rd and
344	gpr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd]) and
345	not (request [nb_request_in]->_write_re and
346	spr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re]));
347
348	in_WRITE_QUEUE_IN_VAL ->write(val);
349	if (val)
350	{
351	in_WRITE_QUEUE_IN_CONTEXT_ID ->write(request [nb_request_in]->_context_id );
352	in_WRITE_QUEUE_IN_FRONT_END_ID ->write(request [nb_request_in]->_front_end_id );
353	in_WRITE_QUEUE_IN_OOO_ENGINE_ID->write(request [nb_request_in]->_ooo_engine_id);
354	in_WRITE_QUEUE_IN_PACKET_ID ->write(request [nb_request_in]->_packet_id );
355	//in_WRITE_QUEUE_IN_OPERATION ->write(request [nb_request_in]->_operation );
356	//in_WRITE_QUEUE_IN_TYPE ->write(request [nb_request_in]->_type );
357	in_WRITE_QUEUE_IN_WRITE_RD ->write(request [nb_request_in]->_write_rd );
358	in_WRITE_QUEUE_IN_NUM_REG_RD ->write(request [nb_request_in]->_num_reg_rd );
359	in_WRITE_QUEUE_IN_DATA_RD ->write(request [nb_request_in]->_data_rd );
360	in_WRITE_QUEUE_IN_WRITE_RE ->write(request [nb_request_in]->_write_re );
361	in_WRITE_QUEUE_IN_NUM_REG_RE ->write(request [nb_request_in]->_num_reg_re );
362	in_WRITE_QUEUE_IN_DATA_RE ->write(request [nb_request_in]->_data_re );
363	in_WRITE_QUEUE_IN_EXCEPTION ->write(request [nb_request_in]->_exception );
364	in_WRITE_QUEUE_IN_NO_SEQUENCE ->write(request [nb_request_in]->_no_sequence );
365	in_WRITE_QUEUE_IN_ADDRESS ->write(request [nb_request_in]->_address );
366	}
367	in_WRITE_QUEUE_OUT_ACK ->write((rand()%100)<percent_transaction_write_queue_out);
368	in_GPR_WRITE_ACK [0] ->write((rand()%100)<percent_transaction_gpr);
369	in_SPR_WRITE_ACK [0] ->write((rand()%100)<percent_transaction_spr);
370
371	SC_START(0);
372
373	// ======================================================================
374	// ======================================================================
375	// ======================================================================
376	if (out_GPR_WRITE_VAL [0]->read() and
377	in_GPR_WRITE_ACK [0]->read())
378	{
379	Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_GPR_WRITE_OOO_ENGINE_ID[0]->read():0;
380	Tgeneral_address_t num_reg = out_GPR_WRITE_NUM_REG [0]->read();
381	Tgeneral_data_t data = out_GPR_WRITE_DATA [0]->read();
382
383	LABEL(" * Accepted GPR_WRITE in register [%d][%d]", ooo_engine_id,num_reg);
384
385	TEST(bool , gpr_val [ooo_engine_id][num_reg], 0);
386	TEST(bool , gpr_use [ooo_engine_id][num_reg], 1);
387	TEST(Tgeneral_data_t, gpr [ooo_engine_id][num_reg], data);
388
389	gpr_val [ooo_engine_id][num_reg] = 1;
390	}
391
392	// ======================================================================
393	// ======================================================================
394	// ======================================================================
395	if (out_SPR_WRITE_VAL [0]->read() and
396	in_SPR_WRITE_ACK [0]->read())
397	{
398	Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_SPR_WRITE_OOO_ENGINE_ID[0]->read():0;
399	Tspecial_address_t num_reg = out_SPR_WRITE_NUM_REG [0]->read();
400	Tspecial_data_t data = out_SPR_WRITE_DATA [0]->read();
401
402	LABEL(" * Accepted SPR_WRITE in register [%d][%d]", ooo_engine_id,num_reg);
403
404	TEST(bool , spr_val [ooo_engine_id][num_reg], 0);
405	TEST(bool , spr_use [ooo_engine_id][num_reg], 1);
406	TEST(Tgeneral_data_t, spr [ooo_engine_id][num_reg], data);
407
408	spr_val [ooo_engine_id][num_reg] = 1;
409	}
410
411	// ======================================================================
412	// ======================================================================
413	// ======================================================================
414	for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
415	{
416	Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_BYPASS_WRITE_OOO_ENGINE_ID[i]->read():0;
417
418	if (out_BYPASS_WRITE_GPR_VAL [i]->read())
419	{
420	Tgeneral_address_t num_reg = out_BYPASS_WRITE_GPR_NUM_REG [i]->read(); // RD
421	Tgeneral_data_t data = out_BYPASS_WRITE_GPR_DATA [i]->read();
422
423	LABEL(" * Accepted BYPASS_WRITE in register [%d][%d] (GPR)", ooo_engine_id,num_reg);
424
425
426	TEST(bool , gpr_use [ooo_engine_id][num_reg], 1);
427	TEST(Tgeneral_data_t, gpr [ooo_engine_id][num_reg], data);
428	}
429	if (out_BYPASS_WRITE_SPR_VAL [i]->read())
430	{
431	Tspecial_address_t num_reg = out_BYPASS_WRITE_SPR_NUM_REG [i]->read(); // RE
432	Tspecial_data_t data = out_BYPASS_WRITE_SPR_DATA [i]->read();
433
434	LABEL(" * Accepted BYPASS_WRITE in register [%d][%d] (SPR)", ooo_engine_id,num_reg);
435
436	TEST(bool , spr_use [ooo_engine_id][num_reg], 1);
437	TEST(Tspecial_data_t, spr [ooo_engine_id][num_reg], data);
438	}
439	}
440
441	// ======================================================================
442	// ======================================================================
443	// ======================================================================
444	if ( in_WRITE_QUEUE_IN_VAL->read() and
445	out_WRITE_QUEUE_IN_ACK->read())
446	{
447	LABEL(" * Accepted WRITE_QUEUE_IN [%d]",nb_request_in);
448	// std::cout << *request [nb_request_in] << std::endl;
449
450	if (request [nb_request_in]->_write_rd)
451	{
452	gpr_val [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = 0;
453	gpr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = 1;
454	gpr [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = request [nb_request_in]->_data_rd;
455	}
456	if (request [nb_request_in]->_write_re)
457	{
458	spr_val [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = 0;
459	spr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = 1;
460	spr [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = request [nb_request_in]->_data_re;
461	}
462	nb_request_in ++;
463	}
464
465	// ======================================================================
466	// ======================================================================
467	// ======================================================================
468	if (out_WRITE_QUEUE_OUT_VAL->read() and
469	in_WRITE_QUEUE_OUT_ACK->read())
470	{
471	Tcontext_t packet;
472	if (_param->_have_port_packet_id)
473	packet = out_WRITE_QUEUE_OUT_PACKET_ID->read();
474	else
475	packet = 0;
476
477	LABEL(" * Accepted WRITE_QUEUE_OUT [%d]",packet);
478	// std::cout << *request [packet] << std::endl;
479
480	if (request [packet]->_write_rd)
481	{
482	TEST(bool, gpr_val [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd], 1);
483	TEST(bool, gpr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd], 1);
484	gpr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd] = 0;
485	}
486	if (request [packet]->_write_re)
487	{
488	TEST(bool, spr_val [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re], 1);
489	TEST(bool, spr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re], 1);
490	spr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re] = 0;
491	}
492
493	if (_param->_have_port_context_id)
494	TEST(Tcontext_t , out_WRITE_QUEUE_OUT_CONTEXT_ID ->read(), request [packet]->_context_id );
495	if (_param->_have_port_front_end_id)
496	TEST(Tcontext_t , out_WRITE_QUEUE_OUT_FRONT_END_ID ->read(), request [packet]->_front_end_id );
497	if (_param->_have_port_ooo_engine_id)
498	TEST(Tcontext_t , out_WRITE_QUEUE_OUT_OOO_ENGINE_ID->read(), request [packet]->_ooo_engine_id);
499
500	//TEST(Toperation_t , out_WRITE_QUEUE_OUT_OPERATION ->read(), request [packet]->_operation );
501	//TEST(Ttype_t , out_WRITE_QUEUE_OUT_TYPE ->read(), request [packet]->_type );
502	TEST(Tcontrol_t , out_WRITE_QUEUE_OUT_FLAGS ->read(), request [packet]->_data_re );
503	TEST(Texception_t , out_WRITE_QUEUE_OUT_EXCEPTION ->read(), request [packet]->_exception );
504	TEST(Tcontrol_t , out_WRITE_QUEUE_OUT_NO_SEQUENCE ->read(), request [packet]->_no_sequence );
505	TEST(Tgeneral_data_t, out_WRITE_QUEUE_OUT_ADDRESS ->read(), request [packet]->_address );
506
507	nb_request_out ++;
508	}
509
510	SC_START(1);
511	}
512
513	for (uint32_t i=0; i<_param->_nb_packet; i++)
514	delete request [i];
515
516	}
517
518	/********************************************************
519	* Simulation - End
520	********************************************************/
521
522	TEST_OK ("End of Simulation");
523	delete _time;
524
525	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
526
527	delete in_CLOCK;
528	delete in_NRESET;
529
530	delete in_WRITE_QUEUE_IN_VAL ;
531	delete out_WRITE_QUEUE_IN_ACK ;
532	delete in_WRITE_QUEUE_IN_CONTEXT_ID ;
533	delete in_WRITE_QUEUE_IN_FRONT_END_ID ;
534	delete in_WRITE_QUEUE_IN_OOO_ENGINE_ID ;
535	delete in_WRITE_QUEUE_IN_PACKET_ID ;
536	//delete in_WRITE_QUEUE_IN_OPERATION ;
537	//delete in_WRITE_QUEUE_IN_TYPE ;
538	delete in_WRITE_QUEUE_IN_WRITE_RD ;
539	delete in_WRITE_QUEUE_IN_NUM_REG_RD ;
540	delete in_WRITE_QUEUE_IN_DATA_RD ;
541	delete in_WRITE_QUEUE_IN_WRITE_RE ;
542	delete in_WRITE_QUEUE_IN_NUM_REG_RE ;
543	delete in_WRITE_QUEUE_IN_DATA_RE ;
544	delete in_WRITE_QUEUE_IN_EXCEPTION ;
545	delete in_WRITE_QUEUE_IN_NO_SEQUENCE ;
546	delete in_WRITE_QUEUE_IN_ADDRESS ;
547	delete out_WRITE_QUEUE_OUT_VAL ;
548	delete in_WRITE_QUEUE_OUT_ACK ;
549	delete out_WRITE_QUEUE_OUT_CONTEXT_ID ;
550	delete out_WRITE_QUEUE_OUT_FRONT_END_ID ;
551	delete out_WRITE_QUEUE_OUT_OOO_ENGINE_ID;
552	delete out_WRITE_QUEUE_OUT_PACKET_ID ;
553	//delete out_WRITE_QUEUE_OUT_OPERATION ;
554	//delete out_WRITE_QUEUE_OUT_TYPE ;
555	delete out_WRITE_QUEUE_OUT_FLAGS ;
556	delete out_WRITE_QUEUE_OUT_EXCEPTION ;
557	delete out_WRITE_QUEUE_OUT_NO_SEQUENCE ;
558	delete out_WRITE_QUEUE_OUT_ADDRESS ;
559	delete [] out_GPR_WRITE_VAL ;
560	delete [] in_GPR_WRITE_ACK ;
561	delete [] out_GPR_WRITE_OOO_ENGINE_ID ;
562	delete [] out_GPR_WRITE_NUM_REG ;
563	delete [] out_GPR_WRITE_DATA ;
564	delete [] out_SPR_WRITE_VAL ;
565	delete [] in_SPR_WRITE_ACK ;
566	delete [] out_SPR_WRITE_OOO_ENGINE_ID ;
567	delete [] out_SPR_WRITE_NUM_REG ;
568	delete [] out_SPR_WRITE_DATA ;
569	delete [] out_BYPASS_WRITE_OOO_ENGINE_ID ;
570	delete [] out_BYPASS_WRITE_GPR_VAL ;
571	delete [] out_BYPASS_WRITE_GPR_NUM_REG ;
572	delete [] out_BYPASS_WRITE_GPR_DATA ;
573	delete [] out_BYPASS_WRITE_SPR_VAL ;
574	delete [] out_BYPASS_WRITE_SPR_NUM_REG ;
575	delete [] out_BYPASS_WRITE_SPR_DATA ;
576
577	#endif
578
579	delete _Write_queue;
580	#ifdef STATISTICS
581	delete _parameters_statistics;
582	#endif
583	}

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