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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/test.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 15 years ago
Almost complete design with Test and test platform
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1	/*
2	* $Id: test.cpp 88 2008-12-10 18:31:39Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 1
10	#define CYCLE_MAX (1024*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Common/include/BitManipulation.h"
15	#include "Behavioural/include/Allocation.h"
16
17	class entry_t
18	{
19	public : Tcontext_t _context_id ;
20	public : Tcontext_t _front_end_id ;
21	public : Tcontext_t _ooo_engine_id;
22	public : Tpacket_t _packet_id ;
23	//public : Toperation_t _operation ;
24	public : Ttype_t _type ;
25	public : Tcontrol_t _write_rd ;
26	public : Tgeneral_address_t _num_reg_rd ;
27	public : Tgeneral_data_t _data_rd ;
28	public : Tcontrol_t _write_re ;
29	public : Tspecial_address_t _num_reg_re ;
30	public : Tspecial_data_t _data_re ;
31	public : Texception_t _exception ;
32	public : Tcontrol_t _no_sequence ;
33	public : Tgeneral_data_t _address ;
34
35	public : entry_t (Tcontext_t context_id ,
36	Tcontext_t front_end_id ,
37	Tcontext_t ooo_engine_id,
38	Tpacket_t packet_id ,
39	//Toperation_t operation ,
40	Ttype_t type ,
41	Tcontrol_t write_rd ,
42	Tgeneral_address_t num_reg_rd ,
43	Tgeneral_data_t data_rd ,
44	Tcontrol_t write_re ,
45	Tspecial_address_t num_reg_re ,
46	Tspecial_data_t data_re ,
47	Texception_t exception ,
48	Tcontrol_t no_sequence ,
49	Tgeneral_data_t address )
50	{
51	_context_id = context_id ;
52	_front_end_id = front_end_id ;
53	_ooo_engine_id = ooo_engine_id;
54	_packet_id = packet_id ;
55	//_operation = operation ;
56	_type = type ;
57	_write_rd = write_rd ;
58	_num_reg_rd = num_reg_rd ;
59	_data_rd = data_rd ;
60	_write_re = write_re ;
61	_num_reg_re = num_reg_re ;
62	_data_re = data_re ;
63	_exception = exception ;
64	_no_sequence = no_sequence ;
65	_address = address ;
66	};
67
68	friend std::ostream& operator<< (std::ostream& output_stream,
69	entry_t & x)
70	{
71	output_stream << " * _context_id : " << toString(x._context_id ) << std::endl
72	<< " * _front_end_id : " << toString(x._front_end_id ) << std::endl
73	<< " * _ooo_engine_id : " << toString(x._ooo_engine_id) << std::endl
74	<< " * _packet_id : " << toString(x._packet_id ) << std::endl
75	//<< " * _operation : " << toString(x._operation ) << std::endl
76	<< " * _type : " << toString(x._type ) << std::endl
77	<< " * _write_rd : " << toString(x._write_rd ) << std::endl
78	<< " * _num_reg_rd : " << toString(x._num_reg_rd ) << std::endl
79	<< " * _data_rd : " << toString(x._data_rd ) << std::endl
80	<< " * _write_re : " << toString(x._write_re ) << std::endl
81	<< " * _num_reg_re : " << toString(x._num_reg_re ) << std::endl
82	<< " * _data_re : " << toString(x._data_re ) << std::endl
83	<< " * _exception : " << toString(x._exception ) << std::endl
84	<< " * _no_sequence : " << toString(x._no_sequence ) << std::endl
85	<< " * _address : " << toString(x._address ) << std::endl;
86
87	return output_stream;
88	}
89	};
90
91	void test (string name,
92	morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Parameters * _param)
93	{
94	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
95
96	#ifdef STATISTICS
97	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
98	#endif
99
100	Tusage_t _usage = USE_ALL;
101
102	// _usage = usage_unset(_usage,USE_SYSTEMC );
103	// _usage = usage_unset(_usage,USE_VHDL );
104	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
105	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
106	// _usage = usage_unset(_usage,USE_POSITION );
107	_usage = usage_unset(_usage,USE_STATISTICS );
108	// _usage = usage_unset(_usage,USE_INFORMATION );
109
110	Write_queue * _Write_queue = new Write_queue
111	(name.c_str(),
112	#ifdef STATISTICS
113	_parameters_statistics,
114	#endif
115	_param,
116	_usage);
117
118	#ifdef SYSTEMC
119	/*********************************************************************
120	* Déclarations des signaux
121	*********************************************************************/
122	string rename;
123
124	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
125	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
126
127	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_VAL ," in_WRITE_QUEUE_IN_VAL" , Tcontrol_t );
128	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_IN_ACK ,"out_WRITE_QUEUE_IN_ACK" , Tcontrol_t );
129	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_CONTEXT_ID ," in_WRITE_QUEUE_IN_CONTEXT_ID" , Tcontext_t );
130	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_FRONT_END_ID ," in_WRITE_QUEUE_IN_FRONT_END_ID" , Tcontext_t );
131	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_OOO_ENGINE_ID ," in_WRITE_QUEUE_IN_OOO_ENGINE_ID" , Tcontext_t );
132	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_PACKET_ID ," in_WRITE_QUEUE_IN_PACKET_ID" , Tpacket_t );
133	//ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_OPERATION ," in_WRITE_QUEUE_IN_OPERATION" , Toperation_t );
134	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_TYPE ," in_WRITE_QUEUE_IN_TYPE" , Ttype_t );
135	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_WRITE_RD ," in_WRITE_QUEUE_IN_WRITE_RD" , Tcontrol_t );
136	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NUM_REG_RD ," in_WRITE_QUEUE_IN_NUM_REG_RD" , Tgeneral_address_t);
137	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_DATA_RD ," in_WRITE_QUEUE_IN_DATA_RD" , Tgeneral_data_t );
138	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_WRITE_RE ," in_WRITE_QUEUE_IN_WRITE_RE" , Tcontrol_t );
139	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NUM_REG_RE ," in_WRITE_QUEUE_IN_NUM_REG_RE" , Tspecial_address_t);
140	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_DATA_RE ," in_WRITE_QUEUE_IN_DATA_RE" , Tspecial_data_t );
141	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_EXCEPTION ," in_WRITE_QUEUE_IN_EXCEPTION" , Texception_t );
142	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NO_SEQUENCE ," in_WRITE_QUEUE_IN_NO_SEQUENCE" , Tcontrol_t );
143	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_ADDRESS ," in_WRITE_QUEUE_IN_ADDRESS" , Tgeneral_data_t );
144	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_VAL ,"out_WRITE_QUEUE_OUT_VAL" , Tcontrol_t );
145	ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_OUT_ACK ," in_WRITE_QUEUE_OUT_ACK" , Tcontrol_t );
146	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_CONTEXT_ID ,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , Tcontext_t );
147	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_FRONT_END_ID ,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , Tcontext_t );
148	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_OOO_ENGINE_ID,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", Tcontext_t );
149	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_PACKET_ID ,"out_WRITE_QUEUE_OUT_PACKET_ID" , Tpacket_t );
150	//ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_OPERATION ,"out_WRITE_QUEUE_OUT_OPERATION" , Toperation_t );
151	//ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_TYPE ,"out_WRITE_QUEUE_OUT_TYPE" , Ttype_t );
152	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_FLAGS ,"out_WRITE_QUEUE_OUT_FLAGS" , Tspecial_data_t );
153	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_EXCEPTION ,"out_WRITE_QUEUE_OUT_EXCEPTION" , Texception_t );
154	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , Tcontrol_t );
155	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_ADDRESS ,"out_WRITE_QUEUE_OUT_ADDRESS" , Tgeneral_data_t );
156	ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_DATA ,"out_WRITE_QUEUE_OUT_DATA" , Tgeneral_data_t );
157	ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write);
158	ALLOC1_SC_SIGNAL( in_GPR_WRITE_ACK ," in_GPR_WRITE_ACK" , Tcontrol_t , _param->_nb_gpr_write);
159	ALLOC1_SC_SIGNAL(out_GPR_WRITE_OOO_ENGINE_ID ,"out_GPR_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_gpr_write);
160	ALLOC1_SC_SIGNAL(out_GPR_WRITE_NUM_REG ,"out_GPR_WRITE_NUM_REG" , Tgeneral_address_t, _param->_nb_gpr_write);
161	ALLOC1_SC_SIGNAL(out_GPR_WRITE_DATA ,"out_GPR_WRITE_DATA" , Tgeneral_data_t , _param->_nb_gpr_write);
162	ALLOC1_SC_SIGNAL(out_SPR_WRITE_VAL ,"out_SPR_WRITE_VAL" , Tcontrol_t , _param->_nb_spr_write);
163	ALLOC1_SC_SIGNAL( in_SPR_WRITE_ACK ," in_SPR_WRITE_ACK" , Tcontrol_t , _param->_nb_spr_write);
164	ALLOC1_SC_SIGNAL(out_SPR_WRITE_OOO_ENGINE_ID ,"out_SPR_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_spr_write);
165	ALLOC1_SC_SIGNAL(out_SPR_WRITE_NUM_REG ,"out_SPR_WRITE_NUM_REG" , Tspecial_address_t, _param->_nb_spr_write);
166	ALLOC1_SC_SIGNAL(out_SPR_WRITE_DATA ,"out_SPR_WRITE_DATA" , Tspecial_data_t , _param->_nb_spr_write);
167	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_OOO_ENGINE_ID ,"out_BYPASS_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_bypass_write);
168	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_VAL ,"out_BYPASS_WRITE_GPR_VAL" , Tcontrol_t , _param->_nb_bypass_write);
169	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_NUM_REG ,"out_BYPASS_WRITE_GPR_NUM_REG" , Tgeneral_address_t, _param->_nb_bypass_write);
170	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_DATA ,"out_BYPASS_WRITE_GPR_DATA" , Tgeneral_data_t , _param->_nb_bypass_write);
171	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_VAL ,"out_BYPASS_WRITE_SPR_VAL" , Tcontrol_t , _param->_nb_bypass_write);
172	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_NUM_REG ,"out_BYPASS_WRITE_SPR_NUM_REG" , Tspecial_address_t, _param->_nb_bypass_write);
173	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_DATA ,"out_BYPASS_WRITE_SPR_DATA" , Tspecial_data_t , _param->_nb_bypass_write);
174
175	/********************************************************
176	* Instanciation
177	********************************************************/
178
179	msg(_("<%s> : Instanciation of _Write_queue.\n"),name.c_str());
180
181	((_Write_queue->in_CLOCK)) ((in_CLOCK));
182	((_Write_queue->in_NRESET)) ((in_NRESET));
183
184	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_VAL );
185	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_IN_ACK );
186	if (_param->_have_port_context_id)
187	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_CONTEXT_ID );
188	if (_param->_have_port_front_end_id)
189	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_FRONT_END_ID );
190	if (_param->_have_port_ooo_engine_id)
191	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_OOO_ENGINE_ID );
192	if (_param->_have_port_rob_ptr )
193	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_PACKET_ID );
194	//INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_OPERATION );
195	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_TYPE );
196	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_WRITE_RD );
197	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_NUM_REG_RD );
198	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_DATA_RD );
199	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_WRITE_RE );
200	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_NUM_REG_RE );
201	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_DATA_RE );
202	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_EXCEPTION );
203	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_NO_SEQUENCE );
204	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_ADDRESS );
205	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_VAL );
206	INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_OUT_ACK );
207	if (_param->_have_port_context_id)
208	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_CONTEXT_ID );
209	if (_param->_have_port_front_end_id)
210	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_FRONT_END_ID );
211	if (_param->_have_port_ooo_engine_id)
212	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_OOO_ENGINE_ID);
213	if (_param->_have_port_rob_ptr )
214	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_PACKET_ID );
215	//INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_OPERATION );
216	//INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_TYPE );
217	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_FLAGS );
218	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_EXCEPTION );
219	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_NO_SEQUENCE );
220	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_ADDRESS );
221	INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_DATA );
222	INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_VAL , _param->_nb_gpr_write);
223	INSTANCE1_SC_SIGNAL(_Write_queue, in_GPR_WRITE_ACK , _param->_nb_gpr_write);
224	if (_param->_have_port_ooo_engine_id)
225	INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_OOO_ENGINE_ID , _param->_nb_gpr_write);
226	INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_NUM_REG , _param->_nb_gpr_write);
227	INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_DATA , _param->_nb_gpr_write);
228	INSTANCE1_SC_SIGNAL(_Write_queue, out_SPR_WRITE_VAL , _param->_nb_spr_write);
229	INSTANCE1_SC_SIGNAL(_Write_queue, in_SPR_WRITE_ACK , _param->_nb_spr_write);
230	if (_param->_have_port_ooo_engine_id)
231	INSTANCE1_SC_SIGNAL(_Write_queue, out_SPR_WRITE_OOO_ENGINE_ID , _param->_nb_spr_write);
232	INSTANCE1_SC_SIGNAL(_Write_queue, out_SPR_WRITE_NUM_REG , _param->_nb_spr_write);
233	INSTANCE1_SC_SIGNAL(_Write_queue, out_SPR_WRITE_DATA , _param->_nb_spr_write);
234	if (_param->_have_port_ooo_engine_id)
235	INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_OOO_ENGINE_ID , _param->_nb_bypass_write);
236	INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_GPR_VAL , _param->_nb_bypass_write);
237	INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_GPR_NUM_REG , _param->_nb_bypass_write);
238	INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_GPR_DATA , _param->_nb_bypass_write);
239	INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_SPR_VAL , _param->_nb_bypass_write);
240	INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_SPR_NUM_REG , _param->_nb_bypass_write);
241	INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_SPR_DATA , _param->_nb_bypass_write);
242
243	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
244
245	Time * _time = new Time();
246
247	/********************************************************
248	* Simulation - Begin
249	********************************************************/
250
251	// Initialisation
252
253	const uint32_t seed = 0;
254	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
255
256	srand(seed);
257
258	const int32_t percent_transaction_write_queue_in = 75;
259	const int32_t percent_transaction_write_queue_out = 75;
260	const int32_t percent_transaction_gpr = 75;
261	const int32_t percent_transaction_spr = 75;
262
263	bool gpr_val [_param->_nb_ooo_engine][_param->_nb_general_register];
264	bool gpr_use [_param->_nb_ooo_engine][_param->_nb_general_register];
265	Tgeneral_data_t gpr [_param->_nb_ooo_engine][_param->_nb_general_register];
266	bool spr_val [_param->_nb_ooo_engine][_param->_nb_special_register];
267	bool spr_use [_param->_nb_ooo_engine][_param->_nb_special_register];
268	Tgeneral_data_t spr [_param->_nb_ooo_engine][_param->_nb_special_register];
269
270	entry_t * request [_param->_nb_packet];
271
272	SC_START(0);
273	LABEL("Initialisation");
274
275	LABEL("Reset");
276	in_NRESET->write(0);
277	SC_START(5);
278	in_NRESET->write(1);
279
280	LABEL("Loop of Test");
281
282	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
283	{
284	LABEL("Iteration %d",iteration);
285
286	for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
287	{
288	for (uint32_t j=0; j<_param->_nb_general_register; j++)
289	{
290	gpr_val [i][j] = 0;
291	gpr_use [i][j] = 0;
292	gpr [i][j] = rand();
293	}
294	for (uint32_t j=0; j<_param->_nb_special_register; j++)
295	{
296	spr_val [i][j] = 0;
297	spr_use [i][j] = 0;
298	spr [i][j] = rand();
299	}
300	}
301
302	for (uint32_t i=0; i<_param->_nb_packet; i++)
303	{
304	request [i] = new entry_t (range<Tcontext_t >(rand(),_param->_size_context_id ),
305	range<Tcontext_t >(rand(),_param->_size_front_end_id ),
306	range<Tcontext_t >(rand(),_param->_size_ooo_engine_id ),
307	i,
308	//range<Toperation_t >(rand(),_param->_size_operation ),
309	range<Ttype_t >(rand(),_param->_size_type ),
310	range<Tcontrol_t >(rand(),1 ),
311	range<Tgeneral_address_t>(rand(),_param->_size_general_register),
312	range<Tgeneral_data_t >(rand(),_param->_size_general_data ),
313	range<Tcontrol_t >(rand(),1 ),
314	range<Tspecial_address_t>(rand(),_param->_size_special_register),
315	range<Tspecial_data_t >(rand(),_param->_size_special_data ),
316	range<Texception_t >(rand(),_param->_size_exception ),
317	range<Tcontrol_t >(rand(),1 ),
318	range<Tgeneral_data_t >(rand(),_param->_size_general_data ));
319	}
320
321	uint32_t nb_request_in = 0;
322	uint32_t nb_request_out = 0;
323
324	while (nb_request_out < _param->_nb_packet)
325	{
326	bool val = (((rand()%100)<percent_transaction_write_queue_in) and
327	(nb_request_in < _param->_nb_packet) and
328	not (request [nb_request_in]->_write_rd and
329	gpr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd]) and
330	not (request [nb_request_in]->_write_re and
331	spr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re]));
332
333	in_WRITE_QUEUE_IN_VAL ->write(val);
334	if (val)
335	{
336	in_WRITE_QUEUE_IN_CONTEXT_ID ->write(request [nb_request_in]->_context_id );
337	in_WRITE_QUEUE_IN_FRONT_END_ID ->write(request [nb_request_in]->_front_end_id );
338	in_WRITE_QUEUE_IN_OOO_ENGINE_ID->write(request [nb_request_in]->_ooo_engine_id);
339	in_WRITE_QUEUE_IN_PACKET_ID ->write(request [nb_request_in]->_packet_id );
340	//in_WRITE_QUEUE_IN_OPERATION ->write(request [nb_request_in]->_operation );
341	in_WRITE_QUEUE_IN_TYPE ->write(request [nb_request_in]->_type );
342	in_WRITE_QUEUE_IN_WRITE_RD ->write(request [nb_request_in]->_write_rd );
343	in_WRITE_QUEUE_IN_NUM_REG_RD ->write(request [nb_request_in]->_num_reg_rd );
344	in_WRITE_QUEUE_IN_DATA_RD ->write(request [nb_request_in]->_data_rd );
345	in_WRITE_QUEUE_IN_WRITE_RE ->write(request [nb_request_in]->_write_re );
346	in_WRITE_QUEUE_IN_NUM_REG_RE ->write(request [nb_request_in]->_num_reg_re );
347	in_WRITE_QUEUE_IN_DATA_RE ->write(request [nb_request_in]->_data_re );
348	in_WRITE_QUEUE_IN_EXCEPTION ->write(request [nb_request_in]->_exception );
349	in_WRITE_QUEUE_IN_NO_SEQUENCE ->write(request [nb_request_in]->_no_sequence );
350	in_WRITE_QUEUE_IN_ADDRESS ->write(request [nb_request_in]->_address );
351	}
352	in_WRITE_QUEUE_OUT_ACK ->write((rand()%100)<percent_transaction_write_queue_out);
353	in_GPR_WRITE_ACK [0] ->write((rand()%100)<percent_transaction_gpr);
354	in_SPR_WRITE_ACK [0] ->write((rand()%100)<percent_transaction_spr);
355
356	SC_START(0);
357
358	// ======================================================================
359	// ======================================================================
360	// ======================================================================
361	if (out_GPR_WRITE_VAL [0]->read() and
362	in_GPR_WRITE_ACK [0]->read())
363	{
364	Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_GPR_WRITE_OOO_ENGINE_ID[0]->read():0;
365	Tgeneral_address_t num_reg = out_GPR_WRITE_NUM_REG [0]->read();
366	Tgeneral_data_t data = out_GPR_WRITE_DATA [0]->read();
367
368	LABEL(" * Accepted GPR_WRITE in register [%d][%d]", ooo_engine_id,num_reg);
369
370	TEST(bool , gpr_val [ooo_engine_id][num_reg], 0);
371	TEST(bool , gpr_use [ooo_engine_id][num_reg], 1);
372	TEST(Tgeneral_data_t, gpr [ooo_engine_id][num_reg], data);
373
374	gpr_val [ooo_engine_id][num_reg] = 1;
375	}
376
377	// ======================================================================
378	// ======================================================================
379	// ======================================================================
380	if (out_SPR_WRITE_VAL [0]->read() and
381	in_SPR_WRITE_ACK [0]->read())
382	{
383	Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_SPR_WRITE_OOO_ENGINE_ID[0]->read():0;
384	Tspecial_address_t num_reg = out_SPR_WRITE_NUM_REG [0]->read();
385	Tspecial_data_t data = out_SPR_WRITE_DATA [0]->read();
386
387	LABEL(" * Accepted SPR_WRITE in register [%d][%d]", ooo_engine_id,num_reg);
388
389	TEST(bool , spr_val [ooo_engine_id][num_reg], 0);
390	TEST(bool , spr_use [ooo_engine_id][num_reg], 1);
391	TEST(Tgeneral_data_t, spr [ooo_engine_id][num_reg], data);
392
393	spr_val [ooo_engine_id][num_reg] = 1;
394	}
395
396	// ======================================================================
397	// ======================================================================
398	// ======================================================================
399	for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
400	{
401	Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_BYPASS_WRITE_OOO_ENGINE_ID[i]->read():0;
402
403	if (out_BYPASS_WRITE_GPR_VAL [i]->read())
404	{
405	Tgeneral_address_t num_reg = out_BYPASS_WRITE_GPR_NUM_REG [i]->read(); // RD
406	Tgeneral_data_t data = out_BYPASS_WRITE_GPR_DATA [i]->read();
407
408	LABEL(" * Accepted BYPASS_WRITE in register [%d][%d] (GPR)", ooo_engine_id,num_reg);
409
410
411	TEST(bool , gpr_use [ooo_engine_id][num_reg], 1);
412	TEST(Tgeneral_data_t, gpr [ooo_engine_id][num_reg], data);
413	}
414	if (out_BYPASS_WRITE_SPR_VAL [i]->read())
415	{
416	Tspecial_address_t num_reg = out_BYPASS_WRITE_SPR_NUM_REG [i]->read(); // RE
417	Tspecial_data_t data = out_BYPASS_WRITE_SPR_DATA [i]->read();
418
419	LABEL(" * Accepted BYPASS_WRITE in register [%d][%d] (SPR)", ooo_engine_id,num_reg);
420
421	TEST(bool , spr_use [ooo_engine_id][num_reg], 1);
422	TEST(Tspecial_data_t, spr [ooo_engine_id][num_reg], data);
423	}
424	}
425
426	// ======================================================================
427	// ======================================================================
428	// ======================================================================
429	if ( in_WRITE_QUEUE_IN_VAL->read() and
430	out_WRITE_QUEUE_IN_ACK->read())
431	{
432	LABEL(" * Accepted WRITE_QUEUE_IN [%d]",nb_request_in);
433	// std::cout << *request [nb_request_in] << std::endl;
434
435	if (request [nb_request_in]->_write_rd)
436	{
437	gpr_val [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = 0;
438	gpr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = 1;
439	gpr [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = request [nb_request_in]->_data_rd;
440	}
441	if (request [nb_request_in]->_write_re)
442	{
443	spr_val [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = 0;
444	spr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = 1;
445	spr [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = request [nb_request_in]->_data_re;
446	}
447	nb_request_in ++;
448	}
449
450	// ======================================================================
451	// ======================================================================
452	// ======================================================================
453	if (out_WRITE_QUEUE_OUT_VAL->read() and
454	in_WRITE_QUEUE_OUT_ACK->read())
455	{
456	Tcontext_t packet;
457	if (_param->_have_port_rob_ptr)
458	packet = out_WRITE_QUEUE_OUT_PACKET_ID->read();
459	else
460	packet = 0;
461
462	LABEL(" * Accepted WRITE_QUEUE_OUT [%d]",packet);
463	// std::cout << *request [packet] << std::endl;
464
465	if (request [packet]->_write_rd)
466	{
467	TEST(bool, gpr_val [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd], 1);
468	TEST(bool, gpr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd], 1);
469	gpr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd] = 0;
470	}
471	if (request [packet]->_write_re)
472	{
473	TEST(bool, spr_val [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re], 1);
474	TEST(bool, spr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re], 1);
475	spr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re] = 0;
476	}
477
478	if (_param->_have_port_context_id)
479	TEST(Tcontext_t , out_WRITE_QUEUE_OUT_CONTEXT_ID ->read(), request [packet]->_context_id );
480	if (_param->_have_port_front_end_id)
481	TEST(Tcontext_t , out_WRITE_QUEUE_OUT_FRONT_END_ID ->read(), request [packet]->_front_end_id );
482	if (_param->_have_port_ooo_engine_id)
483	TEST(Tcontext_t , out_WRITE_QUEUE_OUT_OOO_ENGINE_ID->read(), request [packet]->_ooo_engine_id);
484
485	//TEST(Toperation_t , out_WRITE_QUEUE_OUT_OPERATION ->read(), request [packet]->_operation );
486	//TEST(Ttype_t , out_WRITE_QUEUE_OUT_TYPE ->read(), request [packet]->_type );
487	TEST(Tcontrol_t , out_WRITE_QUEUE_OUT_FLAGS ->read(), request [packet]->_data_re );
488	TEST(Texception_t , out_WRITE_QUEUE_OUT_EXCEPTION ->read(), request [packet]->_exception );
489	TEST(Tcontrol_t , out_WRITE_QUEUE_OUT_NO_SEQUENCE ->read(), request [packet]->_no_sequence );
490	TEST(Tgeneral_data_t, out_WRITE_QUEUE_OUT_ADDRESS ->read(), request [packet]->_address );
491	TEST(Tgeneral_data_t, out_WRITE_QUEUE_OUT_DATA ->read(), request [packet]->_data_rd );
492
493	nb_request_out ++;
494	}
495
496	SC_START(1);
497	}
498
499	for (uint32_t i=0; i<_param->_nb_packet; i++)
500	delete request [i];
501
502	}
503
504	/********************************************************
505	* Simulation - End
506	********************************************************/
507
508	TEST_OK ("End of Simulation");
509	delete _time;
510
511	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
512
513	delete in_CLOCK;
514	delete in_NRESET;
515
516	delete in_WRITE_QUEUE_IN_VAL ;
517	delete out_WRITE_QUEUE_IN_ACK ;
518	delete in_WRITE_QUEUE_IN_CONTEXT_ID ;
519	delete in_WRITE_QUEUE_IN_FRONT_END_ID ;
520	delete in_WRITE_QUEUE_IN_OOO_ENGINE_ID ;
521	delete in_WRITE_QUEUE_IN_PACKET_ID ;
522	//delete in_WRITE_QUEUE_IN_OPERATION ;
523	//delete in_WRITE_QUEUE_IN_TYPE ;
524	delete in_WRITE_QUEUE_IN_WRITE_RD ;
525	delete in_WRITE_QUEUE_IN_NUM_REG_RD ;
526	delete in_WRITE_QUEUE_IN_DATA_RD ;
527	delete in_WRITE_QUEUE_IN_WRITE_RE ;
528	delete in_WRITE_QUEUE_IN_NUM_REG_RE ;
529	delete in_WRITE_QUEUE_IN_DATA_RE ;
530	delete in_WRITE_QUEUE_IN_EXCEPTION ;
531	delete in_WRITE_QUEUE_IN_NO_SEQUENCE ;
532	delete in_WRITE_QUEUE_IN_ADDRESS ;
533	delete out_WRITE_QUEUE_OUT_VAL ;
534	delete in_WRITE_QUEUE_OUT_ACK ;
535	delete out_WRITE_QUEUE_OUT_CONTEXT_ID ;
536	delete out_WRITE_QUEUE_OUT_FRONT_END_ID ;
537	delete out_WRITE_QUEUE_OUT_OOO_ENGINE_ID;
538	delete out_WRITE_QUEUE_OUT_PACKET_ID ;
539	//delete out_WRITE_QUEUE_OUT_OPERATION ;
540	//delete out_WRITE_QUEUE_OUT_TYPE ;
541	delete out_WRITE_QUEUE_OUT_FLAGS ;
542	delete out_WRITE_QUEUE_OUT_EXCEPTION ;
543	delete out_WRITE_QUEUE_OUT_NO_SEQUENCE ;
544	delete out_WRITE_QUEUE_OUT_ADDRESS ;
545	delete out_WRITE_QUEUE_OUT_DATA ;
546	delete [] out_GPR_WRITE_VAL ;
547	delete [] in_GPR_WRITE_ACK ;
548	delete [] out_GPR_WRITE_OOO_ENGINE_ID ;
549	delete [] out_GPR_WRITE_NUM_REG ;
550	delete [] out_GPR_WRITE_DATA ;
551	delete [] out_SPR_WRITE_VAL ;
552	delete [] in_SPR_WRITE_ACK ;
553	delete [] out_SPR_WRITE_OOO_ENGINE_ID ;
554	delete [] out_SPR_WRITE_NUM_REG ;
555	delete [] out_SPR_WRITE_DATA ;
556	delete [] out_BYPASS_WRITE_OOO_ENGINE_ID ;
557	delete [] out_BYPASS_WRITE_GPR_VAL ;
558	delete [] out_BYPASS_WRITE_GPR_NUM_REG ;
559	delete [] out_BYPASS_WRITE_GPR_DATA ;
560	delete [] out_BYPASS_WRITE_SPR_VAL ;
561	delete [] out_BYPASS_WRITE_SPR_NUM_REG ;
562	delete [] out_BYPASS_WRITE_SPR_DATA ;
563
564	#endif
565
566	delete _Write_queue;
567	#ifdef STATISTICS
568	delete _parameters_statistics;
569	#endif
570	}

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