source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_allocation.cpp @ 114

Last change on this file since 114 was 114, checked in by rosiere, 15 years ago

1) Fix bug with previous commit
2) Add test libc
3) Change Dhrystone
  • Property svn:keywords set to Id
File size: 8.9 KB
Line 
1/*
2 * $Id: Write_queue_allocation.cpp 114 2009-04-16 22:35:37Z rosiere $
3 *
4 * [ Description ]
5 *
6 */
7
8#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h"
9#include "Behavioural/include/Allocation.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_execute_loop {
15namespace execute_loop {
16namespace multi_write_unit {
17namespace write_unit {
18namespace write_queue {
19
20
21#undef  FUNCTION
22#define FUNCTION "Write_queue::allocation"
23  void Write_queue::allocation (void)
24  {
25    log_printf(FUNC,Write_queue,FUNCTION,"Begin");
26
27    _component   = new Component (_usage);
28
29    Entity * entity = _component->set_entity (_name       
30                                              ,_param->_type
31#ifdef POSITION
32                                              ,COMBINATORY
33#endif
34                                              );
35
36    _interfaces = entity->set_interfaces();
37
38    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
39
40      Interface * interface = _interfaces->set_interface(""
41#ifdef POSITION
42                                                         ,IN
43                                                         ,SOUTH,
44                                                         "Generalist interface"
45#endif
46                                                         );
47
48     in_CLOCK        = interface->set_signal_clk              ("clock" ,1, CLOCK_VHDL_YES);
49     in_NRESET       = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
50
51    // -----[ Interface "Write_queue_in" ]--------------------------------   
52     {
53       ALLOC0_INTERFACE_BEGIN ("write_queue_in", IN, WEST, "Input of write_queue");
54       
55       ALLOC0_VALACK_IN ( in_WRITE_QUEUE_IN_VAL,VAL);
56       ALLOC0_VALACK_OUT(out_WRITE_QUEUE_IN_ACK,ACK);
57       ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_CONTEXT_ID   ,"context_id"   ,Tcontext_t        ,_param->_size_context_id       );
58       ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t        ,_param->_size_front_end_id     );
59       ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t        ,_param->_size_ooo_engine_id    );
60       ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_PACKET_ID    ,"packet_id"    ,Tpacket_t         ,_param->_size_rob_ptr          );
61//     ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_OPERATION    ,"operation"    ,Toperation_t      ,_param->_size_operation        );
62//     ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_TYPE         ,"type"         ,Ttype_t           ,_param->_size_type             );
63       ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_WRITE_RD     ,"write_rd"     ,Tcontrol_t        ,1                              );
64       ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_NUM_REG_RD   ,"num_reg_rd"   ,Tgeneral_address_t,_param->_size_general_register );
65       ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_DATA_RD      ,"data_rd"      ,Tgeneral_data_t   ,_param->_size_general_data     );
66       ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_WRITE_RE     ,"write_re"     ,Tcontrol_t        ,1                              );
67       ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_NUM_REG_RE   ,"num_reg_re"   ,Tspecial_address_t,_param->_size_special_register );
68       ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_DATA_RE      ,"data_re"      ,Tspecial_data_t   ,_param->_size_special_data     );
69       ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_EXCEPTION    ,"exception"    ,Texception_t      ,_param->_size_exception        );
70       ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_NO_SEQUENCE  ,"no_sequence"  ,Tcontrol_t        ,1                              );
71       ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_ADDRESS      ,"address"      ,Taddress_t        ,_param->_size_instruction_address);
72
73       ALLOC0_INTERFACE_END();
74     }
75
76    // -----[ Interface "Write_queue_out" ]-------------------------------
77     {
78       ALLOC0_INTERFACE_BEGIN("write_queue_out", OUT, EAST, "Output of write_queue");
79       
80       ALLOC0_VALACK_OUT(out_WRITE_QUEUE_OUT_VAL,VAL);
81       ALLOC0_VALACK_IN ( in_WRITE_QUEUE_OUT_ACK,ACK);
82       ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_CONTEXT_ID   ,"context_id"   ,Tcontext_t     ,_param->_size_context_id   );
83       ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t     ,_param->_size_front_end_id );
84       ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t     ,_param->_size_ooo_engine_id);
85       ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_PACKET_ID    ,"packet_id"    ,Tpacket_t      ,_param->_size_rob_ptr      );
86//     ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_OPERATION    ,"operation"    ,Toperation_t   ,_param->_size_operation    );
87//     ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_TYPE         ,"type"         ,Ttype_t        ,_param->_size_type         );
88       ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_FLAGS        ,"flags"        ,Tspecial_data_t,_param->_size_special_data );
89       ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_EXCEPTION    ,"exception"    ,Texception_t   ,_param->_size_exception    );
90       ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_NO_SEQUENCE  ,"no_sequence"  ,Tcontrol_t     ,1                          );
91       ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_ADDRESS      ,"address"      ,Taddress_t     ,_param->_size_instruction_address);
92       ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_DATA         ,"data"         ,Tgeneral_data_t,_param->_size_general_data );
93
94       ALLOC0_INTERFACE_END();
95     }
96
97    // -----[ Interface "gpr_write" ]-------------------------------------
98     {
99       ALLOC1_INTERFACE_BEGIN("gpr_write", OUT, SOUTH ,"Output of write_queue", _param->_nb_gpr_write);
100
101       ALLOC1_VALACK_OUT(out_GPR_WRITE_VAL,VAL);
102       ALLOC1_VALACK_IN ( in_GPR_WRITE_ACK,ACK);
103       ALLOC1_SIGNAL_OUT(out_GPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t        ,_param->_size_ooo_engine_id   );
104       ALLOC1_SIGNAL_OUT(out_GPR_WRITE_NUM_REG      ,"num_reg"      ,Tgeneral_address_t,_param->_size_general_register);
105       ALLOC1_SIGNAL_OUT(out_GPR_WRITE_DATA         ,"data"         ,Tgeneral_data_t   ,_param->_size_general_data    );
106
107       ALLOC1_INTERFACE_END(_param->_nb_gpr_write);
108     }
109
110    // -----[ Interface "spr_write" ]-------------------------------------
111     {
112       ALLOC1_INTERFACE_BEGIN("spr_write", OUT, SOUTH ,"Output of write_queue", _param->_nb_spr_write);
113
114       ALLOC1_VALACK_OUT(out_SPR_WRITE_VAL,VAL);
115       ALLOC1_VALACK_IN ( in_SPR_WRITE_ACK,ACK);
116       ALLOC1_SIGNAL_OUT(out_SPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t        ,_param->_size_ooo_engine_id   );
117       ALLOC1_SIGNAL_OUT(out_SPR_WRITE_NUM_REG      ,"num_reg"      ,Tspecial_address_t,_param->_size_special_register);
118       ALLOC1_SIGNAL_OUT(out_SPR_WRITE_DATA         ,"data"         ,Tspecial_data_t   ,_param->_size_special_data    );
119
120       ALLOC1_INTERFACE_END(_param->_nb_spr_write);
121     }
122
123    // -----[ Interface "bypass_write" ]----------------------------------
124     {
125       ALLOC1_INTERFACE_BEGIN("bypass_write", OUT, NORTH ,"Output of internal write_queue", _param->_nb_bypass_write);
126       
127       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t        ,_param->_size_ooo_engine_id   );
128       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_VAL      ,"gpr_val"      ,Tcontrol_t        ,1                             );
129       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_NUM_REG  ,"gpr_num_reg"  ,Tgeneral_address_t,_param->_size_general_register);
130       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_DATA     ,"gpr_data"     ,Tgeneral_data_t   ,_param->_size_general_data    );
131       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_VAL      ,"spr_val"      ,Tcontrol_t        ,1                             );
132       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_NUM_REG  ,"spr_num_reg"  ,Tspecial_address_t,_param->_size_special_register);
133       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_DATA     ,"spr_data"     ,Tspecial_data_t   ,_param->_size_special_data    );
134
135       ALLOC1_INTERFACE_END(_param->_nb_bypass_write);
136     }
137
138    // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
139
140     _queue = new std::list<write_queue_entry_t *>;
141
142    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
143#ifdef VHDL
144     if (usage_is_set(_usage,USE_VHDL))
145       {
146         _param_queue = new morpheo::behavioural::generic::queue::Parameters
147           (_param->_size_queue,
148            _param->_size_internal_queue,
149            _param->_nb_bypass_write,
150            false,
151            false
152            );
153         
154         std::string queue_name = _name + "_queue";
155         _component_queue = new morpheo::behavioural::generic::queue::Queue
156           (queue_name.c_str()
157#ifdef STATISTICS
158            ,NULL
159#endif
160            ,_param_queue
161            ,USE_VHDL);
162         
163         _component->set_component(_component_queue->_component
164#ifdef POSITION
165                                   , 50, 50, 50, 50
166#endif
167                                   , INSTANCE_LIBRARY
168                                   );
169       }
170#endif
171
172#ifdef POSITION
173     if (usage_is_set(_usage,USE_POSITION))
174       _component->generate_file();
175#endif
176
177    log_printf(FUNC,Write_queue,FUNCTION,"End");
178  };
179
180}; // end namespace write_queue
181}; // end namespace write_unit
182}; // end namespace multi_write_unit
183}; // end namespace execute_loop
184}; // end namespace multi_execute_loop
185}; // end namespace core
186
187}; // end namespace behavioural
188}; // end namespace morpheo             
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