source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp @ 133

Last change on this file since 133 was 133, checked in by rosiere, 15 years ago

1) Write_queue : fix multi write bug
  • Property svn:keywords set to Id
File size: 5.9 KB
Line 
1#ifdef SYSTEMC
2/*
3 * $Id: Write_queue_genMoore.cpp 133 2009-07-13 15:19:10Z rosiere $
4 *
5 * [ Description ]
6 *
7 */
8
9#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_execute_loop {
15namespace execute_loop {
16namespace multi_write_unit {
17namespace write_unit {
18namespace write_queue {
19
20
21#undef  FUNCTION
22#define FUNCTION "Write_queue::genMoore"
23  void Write_queue::genMoore (void)
24  {
25    log_begin(Write_queue,FUNCTION);
26    log_function(Write_queue,FUNCTION,_name.c_str());
27   
28    if (PORT_READ(in_NRESET))
29      {
30    // -----[ Interface "bypass_write" ]----------------------------------
31    {
32      std::list<write_queue_entry_t *>::iterator it = _queue->begin();
33
34      // first bypass is the write_queue_in
35      uint32_t first_index = ((_param->_bypass_write_scheme == BYPASS_WRITE_FROM_ALU)?1:0);
36      for (uint32_t i=first_index; i<_param->_nb_bypass_write; i++)
37        {
38          // before because first slot is on {GPR|SPR}_WRITE. Also, take next
39          if (it != _queue->end())
40            it++;
41
42          uint32_t index = i;
43//        bool val = (i+1) < _queue->size();
44          bool val = (it != _queue->end());
45
46          if (val)
47            {
48              if (_param->_have_port_ooo_engine_id)
49              PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [index], (*it)->_ooo_engine_id);
50              PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG   [index], (*it)->_num_reg_rd);
51              PORT_WRITE(out_BYPASS_WRITE_GPR_DATA      [index], (*it)->_data_rd   );
52              PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG   [index], (*it)->_num_reg_re);
53              PORT_WRITE(out_BYPASS_WRITE_SPR_DATA      [index], (*it)->_data_re   );
54            }
55#ifdef SYSTEMC_VHDL_COMPATIBILITY
56          else
57            {
58              if (_param->_have_port_ooo_engine_id)
59              PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [index], 0);
60              PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG   [index], 0);
61              PORT_WRITE(out_BYPASS_WRITE_GPR_DATA      [index], 0);
62              PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG   [index], 0);
63              PORT_WRITE(out_BYPASS_WRITE_SPR_DATA      [index], 0);
64            }
65#endif
66
67          PORT_WRITE(out_BYPASS_WRITE_GPR_VAL       [index], val and (*it)->_write_rd  );
68          PORT_WRITE(out_BYPASS_WRITE_SPR_VAL       [index], val and (*it)->_write_re  );
69        }
70    }
71
72    // -----[ Interface "Write_queue_in" ]--------------------------------
73    {
74      internal_WRITE_QUEUE_IN_ACK = _queue->size() < _param->_size_queue;
75    }
76
77    if (_param->_queue_scheme == WRITE_QUEUE_SCHEME_MOORE)
78      {
79    // -----[ Interface "gpr_write" ]-------------------------------------
80    // -----[ Interface "spr_write" ]-------------------------------------
81    {
82      bool val = not _queue->empty();
83
84      internal_GPR_WRITE_VAL = val and _queue->front()->_write_rd;
85      internal_SPR_WRITE_VAL = val and _queue->front()->_write_re;
86     
87      if (val)
88        {
89          if (_param->_have_port_ooo_engine_id)
90          {
91          PORT_WRITE(out_GPR_WRITE_OOO_ENGINE_ID [0], _queue->front()->_ooo_engine_id);
92          PORT_WRITE(out_SPR_WRITE_OOO_ENGINE_ID [0], _queue->front()->_ooo_engine_id);
93          }
94          PORT_WRITE(out_GPR_WRITE_NUM_REG       [0], _queue->front()->_num_reg_rd);
95          PORT_WRITE(out_GPR_WRITE_DATA          [0], _queue->front()->_data_rd   );
96          PORT_WRITE(out_SPR_WRITE_NUM_REG       [0], _queue->front()->_num_reg_re);
97          PORT_WRITE(out_SPR_WRITE_DATA          [0], _queue->front()->_data_re   );
98        }
99    }
100
101    // -----[ Interface "Write_queue_out" ]--------------------------------
102    {
103      internal_WRITE_QUEUE_OUT_VAL = ((not _queue->empty()           ) and
104                                      (not _queue->front()->_write_rd) and
105                                      (not _queue->front()->_write_re) and
106                                      (_queue->front()->_exception != EXCEPTION_MEMORY_LOAD_SPECULATIVE)
107                                      );
108     
109      if (internal_WRITE_QUEUE_OUT_VAL)
110        {
111          if (_param->_have_port_context_id)
112          PORT_WRITE(out_WRITE_QUEUE_OUT_CONTEXT_ID   , _queue->front()->_context_id   );
113          if (_param->_have_port_front_end_id)
114          PORT_WRITE(out_WRITE_QUEUE_OUT_FRONT_END_ID , _queue->front()->_front_end_id );
115          if (_param->_have_port_ooo_engine_id)
116          PORT_WRITE(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID, _queue->front()->_ooo_engine_id);
117          if (_param->_have_port_rob_ptr  )
118          PORT_WRITE(out_WRITE_QUEUE_OUT_PACKET_ID    , _queue->front()->_packet_id    );
119//        PORT_WRITE(out_WRITE_QUEUE_OUT_OPERATION    , _queue->front()->_operation    );
120//        PORT_WRITE(out_WRITE_QUEUE_OUT_TYPE         , _queue->front()->_type         );
121          PORT_WRITE(out_WRITE_QUEUE_OUT_FLAGS        , _queue->front()->_data_re      );
122          PORT_WRITE(out_WRITE_QUEUE_OUT_EXCEPTION    , _queue->front()->_exception    );
123          PORT_WRITE(out_WRITE_QUEUE_OUT_NO_SEQUENCE  , _queue->front()->_no_sequence  );
124          PORT_WRITE(out_WRITE_QUEUE_OUT_ADDRESS      , _queue->front()->_address      );
125          PORT_WRITE(out_WRITE_QUEUE_OUT_DATA         , _queue->front()->_data_rd      );
126        }
127    }
128
129      } // end WRITE_QUEUE_SCHEME_MOORE
130      }
131    else
132      {
133        // Reset
134        internal_WRITE_QUEUE_IN_ACK  = 0;
135        if (_param->_queue_scheme == WRITE_QUEUE_SCHEME_MOORE)
136          {
137        internal_WRITE_QUEUE_OUT_VAL = 0;
138        internal_GPR_WRITE_VAL = 0;
139        internal_SPR_WRITE_VAL = 0;
140          }
141      }
142
143    // Write output
144    PORT_WRITE(out_WRITE_QUEUE_IN_ACK , internal_WRITE_QUEUE_IN_ACK);
145
146    if (_param->_queue_scheme == WRITE_QUEUE_SCHEME_MOORE)
147      {
148    PORT_WRITE(out_WRITE_QUEUE_OUT_VAL, internal_WRITE_QUEUE_OUT_VAL);
149    PORT_WRITE(out_GPR_WRITE_VAL [0]  , internal_GPR_WRITE_VAL);
150    PORT_WRITE(out_SPR_WRITE_VAL [0]  , internal_SPR_WRITE_VAL);
151      }
152
153    log_end(Write_queue,FUNCTION);
154  };
155
156}; // end namespace write_queue
157}; // end namespace write_unit
158}; // end namespace multi_write_unit
159}; // end namespace execute_loop
160}; // end namespace multi_execute_loop
161}; // end namespace core
162
163}; // end namespace behavioural
164}; // end namespace morpheo             
165#endif
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