source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_allocation.cpp @ 75

Last change on this file since 75 was 75, checked in by rosiere, 16 years ago

Update all component (except front_end) to :

  • new statistics model
  • no namespace std
File size: 22.1 KB
Line 
1/*
2 * $Id$
3 *
4 * [ Description ]
5 *
6 */
7
8#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Write_unit.h"
9#include "Behavioural/include/Allocation.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_execute_loop {
15namespace execute_loop {
16namespace multi_write_unit {
17namespace write_unit {
18
19
20
21#undef  FUNCTION
22#define FUNCTION "Write_unit::allocation"
23  void Write_unit::allocation (
24#ifdef STATISTICS
25                               morpheo::behavioural::Parameters_Statistics * param_statistics
26#else
27                               void
28#endif
29                               )
30  {
31    log_printf(FUNC,Write_unit,FUNCTION,"Begin");
32
33    _component   = new Component (_usage);
34
35    Entity * entity = _component->set_entity (_name       
36                                              ,"Write_unit"
37#ifdef POSITION
38                                              ,COMBINATORY
39#endif
40                                              );
41
42    _interfaces = entity->set_interfaces();
43
44    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
45
46      Interface * interface = _interfaces->set_interface(""
47#ifdef POSITION
48                                                         ,IN
49                                                         ,SOUTH,
50                                                         "Generalist interface"
51#endif
52                                                         );
53
54     in_CLOCK        = interface->set_signal_clk              ("clock" ,1, CLOCK_VHDL_YES);
55     in_NRESET       = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
56
57    // -----[ Interface "write_unit_in" ]--------------------------------   
58     {
59       ALLOC_INTERFACE ("write_unit_in", IN, WEST, "Input of write_unit");
60       
61       ALLOC_VAL_IN    ( in_WRITE_UNIT_IN_VAL);
62       ALLOC_ACK_OUT   (out_WRITE_UNIT_IN_ACK);
63       if(_param->_have_port_context_id)
64       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_CONTEXT_ID   ,"context_id"   ,Tcontext_t        ,_param->_size_context_id       );
65       if(_param->_have_port_front_end_id)
66       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t        ,_param->_size_front_end_id     );
67       if(_param->_have_port_ooo_engine_id)
68       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t        ,_param->_size_ooo_engine_id    );
69       if(_param->_have_port_packet_id)
70       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_PACKET_ID    ,"packet_id"    ,Tpacket_t         ,_param->_size_packet_id        );
71//     ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_OPERATION    ,"operation"    ,Toperation_t      ,_param->_size_operation        );
72//     ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_TYPE         ,"type"         ,Ttype_t           ,_param->_size_type             );
73       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RD     ,"write_rd"     ,Tcontrol_t        ,1                              );
74       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RD   ,"num_reg_rd"   ,Tgeneral_address_t,_param->_size_general_register );
75       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_DATA_RD      ,"data_rd"      ,Tgeneral_data_t   ,_param->_size_general_data     );
76       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RE     ,"write_re"     ,Tcontrol_t        ,1                              );
77       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RE   ,"num_reg_re"   ,Tspecial_address_t,_param->_size_special_register );
78       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_DATA_RE      ,"data_re"      ,Tspecial_data_t   ,_param->_size_special_data     );
79       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_EXCEPTION    ,"exception"    ,Texception_t      ,_param->_size_exception        );
80       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NO_SEQUENCE  ,"no_sequence"  ,Tcontrol_t        ,1                              );
81       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_ADDRESS      ,"address"      ,Tgeneral_data_t   ,_param->_size_general_data     );
82     }
83
84    // -----[ Interface "write_unit_out" ]-------------------------------
85     {
86       ALLOC_INTERFACE ("write_unit_out", OUT, EAST, "Output of write_unit");
87       
88       ALLOC_VAL_OUT   (out_WRITE_UNIT_OUT_VAL);
89       ALLOC_ACK_IN    ( in_WRITE_UNIT_OUT_ACK);
90       if(_param->_have_port_context_id)
91       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_CONTEXT_ID   ,"context_id"   ,Tcontext_t     ,_param->_size_context_id   );
92       if(_param->_have_port_front_end_id)
93       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t     ,_param->_size_front_end_id );
94       if(_param->_have_port_ooo_engine_id)
95       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t     ,_param->_size_ooo_engine_id);
96       if(_param->_have_port_packet_id)
97       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_PACKET_ID    ,"packet_id"    ,Tpacket_t      ,_param->_size_packet_id    );
98//     ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_OPERATION    ,"operation"    ,Toperation_t   ,_param->_size_operation    );
99//     ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_TYPE         ,"type"         ,Ttype_t        ,_param->_size_type         );
100       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_FLAGS        ,"flags"        ,Tspecial_data_t,_param->_size_special_data );
101       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_EXCEPTION    ,"exception"    ,Texception_t   ,_param->_size_exception    );
102       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_NO_SEQUENCE  ,"no_sequence"  ,Tcontrol_t     ,1                          );
103       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_ADDRESS      ,"address"      ,Tgeneral_data_t,_param->_size_general_data );
104     }
105
106    // -----[ Interface "gpr_write" ]-------------------------------------
107     {
108       ALLOC1_INTERFACE("gpr_write", OUT, SOUTH ,"Output of write_unit", _param->_nb_gpr_write);
109
110       ALLOC1_VAL_OUT   (out_GPR_WRITE_VAL          ,_param->_nb_gpr_write);
111       ALLOC1_ACK_IN    ( in_GPR_WRITE_ACK          ,_param->_nb_gpr_write);
112       if(_param->_have_port_ooo_engine_id)
113       ALLOC1_SIGNAL_OUT(out_GPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t        ,_param->_size_ooo_engine_id   ,_param->_nb_gpr_write);
114       ALLOC1_SIGNAL_OUT(out_GPR_WRITE_NUM_REG      ,"num_reg"      ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_gpr_write);
115       ALLOC1_SIGNAL_OUT(out_GPR_WRITE_DATA         ,"data"         ,Tgeneral_data_t   ,_param->_size_general_data    ,_param->_nb_gpr_write);
116     }
117
118    // -----[ Interface "spr_write" ]-------------------------------------
119     {
120       ALLOC1_INTERFACE("spr_write", OUT, SOUTH ,"Output of write_unit", _param->_nb_spr_write);
121
122       ALLOC1_VAL_OUT   (out_SPR_WRITE_VAL          ,_param->_nb_spr_write);
123       ALLOC1_ACK_IN    ( in_SPR_WRITE_ACK          ,_param->_nb_spr_write);
124       if(_param->_have_port_ooo_engine_id)
125       ALLOC1_SIGNAL_OUT(out_SPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t        ,_param->_size_ooo_engine_id   ,_param->_nb_spr_write);
126       ALLOC1_SIGNAL_OUT(out_SPR_WRITE_NUM_REG      ,"num_reg"      ,Tspecial_address_t,_param->_size_special_register,_param->_nb_spr_write);
127       ALLOC1_SIGNAL_OUT(out_SPR_WRITE_DATA         ,"data"         ,Tspecial_data_t   ,_param->_size_special_data    ,_param->_nb_spr_write);
128     }
129
130    // -----[ Interface "bypass_write" ]----------------------------------
131     {
132       ALLOC1_INTERFACE("bypass_write", OUT, NORTH ,"Output of internal write_unit", _param->_nb_bypass_write);
133       
134       if(_param->_have_port_ooo_engine_id)
135       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t        ,_param->_size_ooo_engine_id   , _param->_nb_bypass_write);
136       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_VAL      ,"gpr_val"      ,Tcontrol_t        ,1                             , _param->_nb_bypass_write);
137       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_NUM_REG  ,"gpr_num_reg"  ,Tgeneral_address_t,_param->_size_general_register, _param->_nb_bypass_write);
138       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_DATA     ,"gpr_data"     ,Tgeneral_data_t   ,_param->_size_general_data    , _param->_nb_bypass_write);
139       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_VAL      ,"spr_val"      ,Tcontrol_t        ,1                             , _param->_nb_bypass_write);
140       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_NUM_REG  ,"spr_num_reg"  ,Tspecial_address_t,_param->_size_special_register, _param->_nb_bypass_write);
141       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_DATA     ,"spr_data"     ,Tspecial_data_t   ,_param->_size_special_data    , _param->_nb_bypass_write);
142     }
143
144
145    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
146
147     std::string name;
148
149     {
150       name = _name+"_write_queue";
151       
152       component_write_queue  = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Write_queue (name.c_str()
153#ifdef STATISTICS
154                                                                                                                                                          ,param_statistics
155#endif
156                                                                                                                                                          ,_param->_param_write_queue);
157       
158       _component->set_component (component_write_queue->_component
159#ifdef POSITION
160                                  , 50, 50, 10, 10
161#endif
162                                  );
163     }
164
165     if (_param->_have_component_execute_queue)
166     {
167       name = _name+"_execute_queue";
168       
169       component_execute_queue  = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::execute_queue::Execute_queue (name.c_str()
170#ifdef STATISTICS
171                                                                                                                                                                ,param_statistics
172#endif
173                                                                                                                                                                ,_param->_param_execute_queue);
174       
175       _component->set_component (component_execute_queue->_component
176#ifdef POSITION
177                                  , 50, 50, 10, 10
178#endif
179                                  );
180     }
181
182    // ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
183
184     {
185       name = _name+"_write_queue";
186       std::cout << "Instance : " << name << std::endl;
187       
188#ifdef POSITION
189       _component->interface_map (name ,"",
190                                  _name,"");
191#endif
192
193       _component->port_map(name,"in_CLOCK" , _name, "in_CLOCK");
194       _component->port_map(name,"in_NRESET", _name, "in_NRESET");
195
196
197#ifdef POSITION
198       _component->interface_map (name ,"write_queue_in",
199                                  _name,"write_unit_in");
200#endif
201
202       _component->port_map(name, "in_WRITE_QUEUE_IN_VAL"          , _name, "in_WRITE_UNIT_IN_VAL"          );
203       _component->port_map(name,"out_WRITE_QUEUE_IN_ACK"          , _name,"out_WRITE_UNIT_IN_ACK"          );
204       if (_param->_have_port_context_id)
205       _component->port_map(name, "in_WRITE_QUEUE_IN_CONTEXT_ID"   , _name, "in_WRITE_UNIT_IN_CONTEXT_ID"   );
206       if (_param->_have_port_front_end_id)
207       _component->port_map(name, "in_WRITE_QUEUE_IN_FRONT_END_ID" , _name, "in_WRITE_UNIT_IN_FRONT_END_ID" );
208       if (_param->_have_port_ooo_engine_id)
209       _component->port_map(name, "in_WRITE_QUEUE_IN_OOO_ENGINE_ID", _name, "in_WRITE_UNIT_IN_OOO_ENGINE_ID");
210       if (_param->_have_port_packet_id)
211       _component->port_map(name, "in_WRITE_QUEUE_IN_PACKET_ID"    , _name, "in_WRITE_UNIT_IN_PACKET_ID"    );
212     //_component->port_map(name, "in_WRITE_QUEUE_IN_OPERATION"    , _name, "in_WRITE_UNIT_IN_OPERATION"    );
213     //_component->port_map(name, "in_WRITE_QUEUE_IN_TYPE"         , _name, "in_WRITE_UNIT_IN_TYPE"         );
214       _component->port_map(name, "in_WRITE_QUEUE_IN_WRITE_RD"     , _name, "in_WRITE_UNIT_IN_WRITE_RD"     );
215       _component->port_map(name, "in_WRITE_QUEUE_IN_NUM_REG_RD"   , _name, "in_WRITE_UNIT_IN_NUM_REG_RD"   );
216       _component->port_map(name, "in_WRITE_QUEUE_IN_DATA_RD"      , _name, "in_WRITE_UNIT_IN_DATA_RD"      );
217       _component->port_map(name, "in_WRITE_QUEUE_IN_WRITE_RE"     , _name, "in_WRITE_UNIT_IN_WRITE_RE"     );
218       _component->port_map(name, "in_WRITE_QUEUE_IN_NUM_REG_RE"   , _name, "in_WRITE_UNIT_IN_NUM_REG_RE"   );
219       _component->port_map(name, "in_WRITE_QUEUE_IN_DATA_RE"      , _name, "in_WRITE_UNIT_IN_DATA_RE"      );
220       _component->port_map(name, "in_WRITE_QUEUE_IN_EXCEPTION"    , _name, "in_WRITE_UNIT_IN_EXCEPTION"    );
221       _component->port_map(name, "in_WRITE_QUEUE_IN_NO_SEQUENCE"  , _name, "in_WRITE_UNIT_IN_NO_SEQUENCE"  );
222       _component->port_map(name, "in_WRITE_QUEUE_IN_ADDRESS"      , _name, "in_WRITE_UNIT_IN_ADDRESS"      );
223
224
225       if (_param->_have_component_execute_queue)
226         {
227#ifdef POSITION
228           _component->interface_map (name ,"write_queue_out",
229                                      _name+"_execute_queue", "execute_queue_in");
230#endif
231
232           _component->port_map(name,"out_WRITE_QUEUE_OUT_VAL"          , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_VAL"          );
233           _component->port_map(name, "in_WRITE_QUEUE_OUT_ACK"          , _name+"_execute_queue","out_EXECUTE_QUEUE_IN_ACK"          );
234           if (_param->_have_port_context_id)
235           _component->port_map(name,"out_WRITE_QUEUE_OUT_CONTEXT_ID"   , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_CONTEXT_ID"   );
236           if (_param->_have_port_front_end_id)
237           _component->port_map(name,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_FRONT_END_ID" );
238           if (_param->_have_port_ooo_engine_id)
239           _component->port_map(name,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID");
240           if (_param->_have_port_packet_id)
241           _component->port_map(name,"out_WRITE_QUEUE_OUT_PACKET_ID"    , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_PACKET_ID"    );
242         //_component->port_map(name,"out_WRITE_QUEUE_OUT_OPERATION"    , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_OPERATION"    );
243         //_component->port_map(name,"out_WRITE_QUEUE_OUT_TYPE"         , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_TYPE"         );
244           _component->port_map(name,"out_WRITE_QUEUE_OUT_FLAGS"        , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_FLAGS"        );
245           _component->port_map(name,"out_WRITE_QUEUE_OUT_EXCEPTION"    , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_EXCEPTION"    );
246           _component->port_map(name,"out_WRITE_QUEUE_OUT_NO_SEQUENCE"  , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_NO_SEQUENCE"  );
247           _component->port_map(name,"out_WRITE_QUEUE_OUT_ADDRESS"      , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_ADDRESS"      );
248         }
249       else
250         {
251#ifdef POSITION
252           _component->interface_map (name ,"write_queue_out",
253                                      _name,"write_unit_out");
254#endif
255
256           _component->port_map(name,"out_WRITE_QUEUE_OUT_VAL"          , _name,"out_WRITE_UNIT_OUT_VAL"          );
257           _component->port_map(name, "in_WRITE_QUEUE_OUT_ACK"          , _name, "in_WRITE_UNIT_OUT_ACK"          );
258           if (_param->_have_port_context_id)
259           _component->port_map(name,"out_WRITE_QUEUE_OUT_CONTEXT_ID"   , _name,"out_WRITE_UNIT_OUT_CONTEXT_ID"   );
260           if (_param->_have_port_front_end_id)
261           _component->port_map(name,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , _name,"out_WRITE_UNIT_OUT_FRONT_END_ID" );
262           if (_param->_have_port_ooo_engine_id)
263           _component->port_map(name,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", _name,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID");
264           if (_param->_have_port_packet_id)
265           _component->port_map(name,"out_WRITE_QUEUE_OUT_PACKET_ID"    , _name,"out_WRITE_UNIT_OUT_PACKET_ID"    );
266         //_component->port_map(name,"out_WRITE_QUEUE_OUT_OPERATION"    , _name,"out_WRITE_UNIT_OUT_OPERATION"    );
267         //_component->port_map(name,"out_WRITE_QUEUE_OUT_TYPE"         , _name,"out_WRITE_UNIT_OUT_TYPE"         );
268           _component->port_map(name,"out_WRITE_QUEUE_OUT_FLAGS"        , _name,"out_WRITE_UNIT_OUT_FLAGS"        );
269           _component->port_map(name,"out_WRITE_QUEUE_OUT_EXCEPTION"    , _name,"out_WRITE_UNIT_OUT_EXCEPTION"    );
270           _component->port_map(name,"out_WRITE_QUEUE_OUT_NO_SEQUENCE"  , _name,"out_WRITE_UNIT_OUT_NO_SEQUENCE"  );
271           _component->port_map(name,"out_WRITE_QUEUE_OUT_ADDRESS"      , _name,"out_WRITE_UNIT_OUT_ADDRESS"      );
272         }       
273
274       for (uint32_t i=0; i<_param->_nb_gpr_write; i++)
275         {
276#ifdef POSITION
277           _component->interface_map (name ,"gpr_write_"+toString(i),
278                                      _name,"gpr_write_"+toString(i));
279#endif     
280           
281           _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_VAL"          ,_name,"out_GPR_WRITE_"+toString(i)+"_VAL"          );
282           _component->port_map(name, "in_GPR_WRITE_"+toString(i)+"_ACK"          ,_name, "in_GPR_WRITE_"+toString(i)+"_ACK"          );
283           if (_param->_have_port_ooo_engine_id)
284           _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
285           _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_NUM_REG"      ,_name,"out_GPR_WRITE_"+toString(i)+"_NUM_REG"      );
286           _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_DATA"         ,_name,"out_GPR_WRITE_"+toString(i)+"_DATA"         );
287         }
288
289       for (uint32_t i=0; i<_param->_nb_spr_write; i++)
290         {
291#ifdef POSITION
292           _component->interface_map (name ,"spr_write_"+toString(i),
293                                      _name,"spr_write_"+toString(i));
294#endif     
295           
296           _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_VAL"          ,_name,"out_SPR_WRITE_"+toString(i)+"_VAL"          );
297           _component->port_map(name, "in_SPR_WRITE_"+toString(i)+"_ACK"          ,_name, "in_SPR_WRITE_"+toString(i)+"_ACK"          );
298           if (_param->_have_port_ooo_engine_id)
299           _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
300           _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_NUM_REG"      ,_name,"out_SPR_WRITE_"+toString(i)+"_NUM_REG"      );
301           _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_DATA"         ,_name,"out_SPR_WRITE_"+toString(i)+"_DATA"         );
302         }
303
304
305       for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
306         {
307#ifdef POSITION
308           _component->interface_map (name ,"bypass_write_"+toString(i),
309                                      _name,"bypass_write_"+toString(i));
310#endif     
311
312           if (_param->_have_port_ooo_engine_id)
313           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
314           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL"      ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL"      );
315           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG"  ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG"  );
316           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA"     ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA"     );
317           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL"      ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL"      );
318           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG"  ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG"  );
319           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA"     ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA"     );
320         }
321     }
322
323     if (_param->_have_component_execute_queue)
324       {
325         name = _name+"_execute_queue";
326         std::cout << "Instance : " << name << std::endl;
327         
328#ifdef POSITION
329         _component->interface_map (name ,"",
330                                    _name,"");
331#endif
332         
333         _component->port_map(name,"in_CLOCK" , _name, "in_CLOCK");
334         _component->port_map(name,"in_NRESET", _name, "in_NRESET");
335         
336
337#ifdef POSITION
338         _component->interface_map (name ,"execute_queue_in",
339                                    _name+"_write_queue","write_queue_in");
340#endif
341
342         _component->port_map(name, "in_EXECUTE_QUEUE_IN_VAL"          , _name+"_write_queue","out_WRITE_QUEUE_OUT_VAL"          );
343         _component->port_map(name,"out_EXECUTE_QUEUE_IN_ACK"          , _name+"_write_queue", "in_WRITE_QUEUE_OUT_ACK"          );
344         if (_param->_have_port_context_id)
345         _component->port_map(name, "in_EXECUTE_QUEUE_IN_CONTEXT_ID"   , _name+"_write_queue","out_WRITE_QUEUE_OUT_CONTEXT_ID"   );
346         if (_param->_have_port_front_end_id)
347         _component->port_map(name, "in_EXECUTE_QUEUE_IN_FRONT_END_ID" , _name+"_write_queue","out_WRITE_QUEUE_OUT_FRONT_END_ID" );
348         if (_param->_have_port_ooo_engine_id)
349         _component->port_map(name, "in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID", _name+"_write_queue","out_WRITE_QUEUE_OUT_OOO_ENGINE_ID");
350         if (_param->_have_port_packet_id)
351         _component->port_map(name, "in_EXECUTE_QUEUE_IN_PACKET_ID"    , _name+"_write_queue","out_WRITE_QUEUE_OUT_PACKET_ID"    );
352       //_component->port_map(name, "in_EXECUTE_QUEUE_IN_OPERATION"    , _name+"_write_queue","out_WRITE_QUEUE_OUT_OPERATION"    );
353       //_component->port_map(name, "in_EXECUTE_QUEUE_IN_TYPE"         , _name+"_write_queue","out_WRITE_QUEUE_OUT_TYPE"         );
354         _component->port_map(name, "in_EXECUTE_QUEUE_IN_FLAGS"        , _name+"_write_queue","out_WRITE_QUEUE_OUT_FLAGS"        );
355         _component->port_map(name, "in_EXECUTE_QUEUE_IN_EXCEPTION"    , _name+"_write_queue","out_WRITE_QUEUE_OUT_EXCEPTION"    );
356         _component->port_map(name, "in_EXECUTE_QUEUE_IN_NO_SEQUENCE"  , _name+"_write_queue","out_WRITE_QUEUE_OUT_NO_SEQUENCE"  );
357         _component->port_map(name, "in_EXECUTE_QUEUE_IN_ADDRESS"      , _name+"_write_queue","out_WRITE_QUEUE_OUT_ADDRESS"      );
358
359#ifdef POSITION
360           _component->interface_map (name ,"execute_queue_out",
361                                      _name,"write_unit_out");
362#endif
363
364           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_VAL"          , _name,"out_WRITE_UNIT_OUT_VAL"          );
365           _component->port_map(name, "in_EXECUTE_QUEUE_OUT_ACK"          , _name, "in_WRITE_UNIT_OUT_ACK"          );
366           if (_param->_have_port_context_id)
367           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_CONTEXT_ID"   , _name,"out_WRITE_UNIT_OUT_CONTEXT_ID"   );
368           if (_param->_have_port_front_end_id)
369           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_FRONT_END_ID" , _name,"out_WRITE_UNIT_OUT_FRONT_END_ID" );
370           if (_param->_have_port_ooo_engine_id)
371           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID", _name,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID");
372           if (_param->_have_port_packet_id)
373           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_PACKET_ID"    , _name,"out_WRITE_UNIT_OUT_PACKET_ID"    );
374         //_component->port_map(name,"out_EXECUTE_QUEUE_OUT_OPERATION"    , _name,"out_WRITE_UNIT_OUT_OPERATION"    );
375         //_component->port_map(name,"out_EXECUTE_QUEUE_OUT_TYPE"         , _name,"out_WRITE_UNIT_OUT_TYPE"         );
376           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_FLAGS"        , _name,"out_WRITE_UNIT_OUT_FLAGS"        );
377           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_EXCEPTION"    , _name,"out_WRITE_UNIT_OUT_EXCEPTION"    );
378           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE"  , _name,"out_WRITE_UNIT_OUT_NO_SEQUENCE"  );
379           _component->port_map(name,"out_EXECUTE_QUEUE_OUT_ADDRESS"      , _name,"out_WRITE_UNIT_OUT_ADDRESS"      );
380       }
381
382#ifdef POSITION
383    _component->generate_file();
384#endif
385
386    log_printf(FUNC,Write_unit,FUNCTION,"End");
387  };
388
389}; // end namespace write_unit
390}; // end namespace multi_write_unit
391}; // end namespace execute_loop
392}; // end namespace multi_execute_loop
393}; // end namespace core
394
395}; // end namespace behavioural
396}; // end namespace morpheo             
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