source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_allocation.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 15 years ago

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1/*
2 * $Id: Write_unit_allocation.cpp 88 2008-12-10 18:31:39Z rosiere $
3 *
4 * [ Description ]
5 *
6 */
7
8#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Write_unit.h"
9#include "Behavioural/include/Allocation.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_execute_loop {
15namespace execute_loop {
16namespace multi_write_unit {
17namespace write_unit {
18
19
20
21#undef  FUNCTION
22#define FUNCTION "Write_unit::allocation"
23  void Write_unit::allocation (
24#ifdef STATISTICS
25                               morpheo::behavioural::Parameters_Statistics * param_statistics
26#else
27                               void
28#endif
29                               )
30  {
31    log_printf(FUNC,Write_unit,FUNCTION,"Begin");
32
33    _component   = new Component (_usage);
34
35    Entity * entity = _component->set_entity (_name       
36                                              ,"Write_unit"
37#ifdef POSITION
38                                              ,COMBINATORY
39#endif
40                                              );
41
42    _interfaces = entity->set_interfaces();
43
44    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
45
46      Interface * interface = _interfaces->set_interface(""
47#ifdef POSITION
48                                                         ,IN
49                                                         ,SOUTH,
50                                                         "Generalist interface"
51#endif
52                                                         );
53
54     in_CLOCK        = interface->set_signal_clk              ("clock" ,1, CLOCK_VHDL_YES);
55     in_NRESET       = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
56
57    // -----[ Interface "write_unit_in" ]--------------------------------   
58     {
59       ALLOC_INTERFACE ("write_unit_in", IN, WEST, "Input of write_unit");
60       
61       ALLOC_VALACK_IN ( in_WRITE_UNIT_IN_VAL,VAL);
62       ALLOC_VALACK_OUT(out_WRITE_UNIT_IN_ACK,ACK);
63       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_CONTEXT_ID   ,"context_id"   ,Tcontext_t        ,_param->_size_context_id       );
64       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t        ,_param->_size_front_end_id     );
65       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t        ,_param->_size_ooo_engine_id    );
66       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_PACKET_ID    ,"packet_id"    ,Tpacket_t         ,_param->_size_rob_ptr          );
67//     ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_OPERATION    ,"operation"    ,Toperation_t      ,_param->_size_operation        );
68       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_TYPE         ,"type"         ,Ttype_t           ,_param->_size_type             );
69       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RD     ,"write_rd"     ,Tcontrol_t        ,1                              );
70       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RD   ,"num_reg_rd"   ,Tgeneral_address_t,_param->_size_general_register );
71       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_DATA_RD      ,"data_rd"      ,Tgeneral_data_t   ,_param->_size_general_data     );
72       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RE     ,"write_re"     ,Tcontrol_t        ,1                              );
73       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RE   ,"num_reg_re"   ,Tspecial_address_t,_param->_size_special_register );
74       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_DATA_RE      ,"data_re"      ,Tspecial_data_t   ,_param->_size_special_data     );
75       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_EXCEPTION    ,"exception"    ,Texception_t      ,_param->_size_exception        );
76       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NO_SEQUENCE  ,"no_sequence"  ,Tcontrol_t        ,1                              );
77       ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_ADDRESS      ,"address"      ,Tgeneral_data_t   ,_param->_size_general_data     );
78     }
79
80    // -----[ Interface "write_unit_out" ]-------------------------------
81     {
82       ALLOC_INTERFACE ("write_unit_out", OUT, EAST, "Output of write_unit");
83       
84       ALLOC_VALACK_OUT(out_WRITE_UNIT_OUT_VAL,VAL);
85       ALLOC_VALACK_IN ( in_WRITE_UNIT_OUT_ACK,ACK);
86       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_CONTEXT_ID   ,"context_id"   ,Tcontext_t     ,_param->_size_context_id   );
87       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t     ,_param->_size_front_end_id );
88       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t     ,_param->_size_ooo_engine_id);
89       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_PACKET_ID    ,"packet_id"    ,Tpacket_t      ,_param->_size_rob_ptr      );
90//     ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_OPERATION    ,"operation"    ,Toperation_t   ,_param->_size_operation    );
91//     ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_TYPE         ,"type"         ,Ttype_t        ,_param->_size_type         );
92       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_FLAGS        ,"flags"        ,Tspecial_data_t,_param->_size_special_data );
93       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_EXCEPTION    ,"exception"    ,Texception_t   ,_param->_size_exception    );
94       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_NO_SEQUENCE  ,"no_sequence"  ,Tcontrol_t     ,1                          );
95       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_ADDRESS      ,"address"      ,Tgeneral_data_t,_param->_size_general_data );
96       ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_DATA         ,"data"         ,Tgeneral_data_t,_param->_size_general_data );
97     }
98
99    // -----[ Interface "gpr_write" ]-------------------------------------
100     {
101       ALLOC1_INTERFACE("gpr_write", OUT, SOUTH ,"Output of write_unit", _param->_nb_gpr_write);
102
103       ALLOC1_VALACK_OUT(out_GPR_WRITE_VAL,VAL);
104       ALLOC1_VALACK_IN ( in_GPR_WRITE_ACK,ACK);
105       ALLOC1_SIGNAL_OUT(out_GPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t        ,_param->_size_ooo_engine_id   );
106       ALLOC1_SIGNAL_OUT(out_GPR_WRITE_NUM_REG      ,"num_reg"      ,Tgeneral_address_t,_param->_size_general_register);
107       ALLOC1_SIGNAL_OUT(out_GPR_WRITE_DATA         ,"data"         ,Tgeneral_data_t   ,_param->_size_general_data    );
108     }
109
110    // -----[ Interface "spr_write" ]-------------------------------------
111     {
112       ALLOC1_INTERFACE("spr_write", OUT, SOUTH ,"Output of write_unit", _param->_nb_spr_write);
113
114       ALLOC1_VALACK_OUT(out_SPR_WRITE_VAL,VAL);
115       ALLOC1_VALACK_IN ( in_SPR_WRITE_ACK,ACK);
116       ALLOC1_SIGNAL_OUT(out_SPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t        ,_param->_size_ooo_engine_id   );
117       ALLOC1_SIGNAL_OUT(out_SPR_WRITE_NUM_REG      ,"num_reg"      ,Tspecial_address_t,_param->_size_special_register);
118       ALLOC1_SIGNAL_OUT(out_SPR_WRITE_DATA         ,"data"         ,Tspecial_data_t   ,_param->_size_special_data    );
119     }
120
121    // -----[ Interface "bypass_write" ]----------------------------------
122     {
123       ALLOC1_INTERFACE("bypass_write", OUT, NORTH ,"Output of internal write_unit", _param->_nb_bypass_write);
124       
125       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t        ,_param->_size_ooo_engine_id   );
126       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_VAL      ,"gpr_val"      ,Tcontrol_t        ,1                             );
127       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_NUM_REG  ,"gpr_num_reg"  ,Tgeneral_address_t,_param->_size_general_register);
128       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_DATA     ,"gpr_data"     ,Tgeneral_data_t   ,_param->_size_general_data    );
129       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_VAL      ,"spr_val"      ,Tcontrol_t        ,1                             );
130       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_NUM_REG  ,"spr_num_reg"  ,Tspecial_address_t,_param->_size_special_register);
131       ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_DATA     ,"spr_data"     ,Tspecial_data_t   ,_param->_size_special_data    );
132     }
133
134
135    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
136
137     std::string name;
138
139     {
140       name = _name+"_write_queue";
141       log_printf(INFO,Core,FUNCTION,_("Create   : %s"),name.c_str());     
142
143       component_write_queue  = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Write_queue
144         (name.c_str()
145#ifdef STATISTICS
146          ,param_statistics
147#endif
148          ,_param->_param_write_queue
149          ,_usage);
150       
151       _component->set_component (component_write_queue->_component
152#ifdef POSITION
153                                  , 50, 50, 10, 10
154#endif
155                                  );
156     }
157
158     if (_param->_have_component_execute_queue)
159     {
160       name = _name+"_execute_queue";
161       log_printf(INFO,Core,FUNCTION,_("Create   : %s"),name.c_str());     
162       
163       component_execute_queue  = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::execute_queue::Execute_queue
164         (name.c_str()
165#ifdef STATISTICS
166          ,param_statistics
167#endif
168          ,_param->_param_execute_queue
169          ,_usage);
170       
171       _component->set_component (component_execute_queue->_component
172#ifdef POSITION
173                                  , 50, 50, 10, 10
174#endif
175                                  );
176     }
177
178    // ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
179     {
180       name = _name+"_write_queue";
181       log_printf(INFO,Core,FUNCTION,_("Instance : %s"),name.c_str());
182       
183#ifdef POSITION
184       _component->interface_map (name ,"",
185                                  _name,"");
186#endif
187
188       _component->port_map(name,"in_CLOCK" , _name, "in_CLOCK");
189       _component->port_map(name,"in_NRESET", _name, "in_NRESET");
190
191
192#ifdef POSITION
193       _component->interface_map (name ,"write_queue_in",
194                                  _name,"write_unit_in");
195#endif
196
197       _component->port_map(name, "in_WRITE_QUEUE_IN_VAL"          , _name, "in_WRITE_UNIT_IN_VAL"          );
198       _component->port_map(name,"out_WRITE_QUEUE_IN_ACK"          , _name,"out_WRITE_UNIT_IN_ACK"          );
199       if (_param->_have_port_context_id)
200       _component->port_map(name, "in_WRITE_QUEUE_IN_CONTEXT_ID"   , _name, "in_WRITE_UNIT_IN_CONTEXT_ID"   );
201       if (_param->_have_port_front_end_id)
202       _component->port_map(name, "in_WRITE_QUEUE_IN_FRONT_END_ID" , _name, "in_WRITE_UNIT_IN_FRONT_END_ID" );
203       if (_param->_have_port_ooo_engine_id)
204       _component->port_map(name, "in_WRITE_QUEUE_IN_OOO_ENGINE_ID", _name, "in_WRITE_UNIT_IN_OOO_ENGINE_ID");
205       if (_param->_have_port_rob_ptr)
206       _component->port_map(name, "in_WRITE_QUEUE_IN_PACKET_ID"    , _name, "in_WRITE_UNIT_IN_PACKET_ID"    );
207     //_component->port_map(name, "in_WRITE_QUEUE_IN_OPERATION"    , _name, "in_WRITE_UNIT_IN_OPERATION"    );
208       _component->port_map(name, "in_WRITE_QUEUE_IN_TYPE"         , _name, "in_WRITE_UNIT_IN_TYPE"         );
209       _component->port_map(name, "in_WRITE_QUEUE_IN_WRITE_RD"     , _name, "in_WRITE_UNIT_IN_WRITE_RD"     );
210       _component->port_map(name, "in_WRITE_QUEUE_IN_NUM_REG_RD"   , _name, "in_WRITE_UNIT_IN_NUM_REG_RD"   );
211       _component->port_map(name, "in_WRITE_QUEUE_IN_DATA_RD"      , _name, "in_WRITE_UNIT_IN_DATA_RD"      );
212       _component->port_map(name, "in_WRITE_QUEUE_IN_WRITE_RE"     , _name, "in_WRITE_UNIT_IN_WRITE_RE"     );
213       _component->port_map(name, "in_WRITE_QUEUE_IN_NUM_REG_RE"   , _name, "in_WRITE_UNIT_IN_NUM_REG_RE"   );
214       _component->port_map(name, "in_WRITE_QUEUE_IN_DATA_RE"      , _name, "in_WRITE_UNIT_IN_DATA_RE"      );
215       _component->port_map(name, "in_WRITE_QUEUE_IN_EXCEPTION"    , _name, "in_WRITE_UNIT_IN_EXCEPTION"    );
216       _component->port_map(name, "in_WRITE_QUEUE_IN_NO_SEQUENCE"  , _name, "in_WRITE_UNIT_IN_NO_SEQUENCE"  );
217       _component->port_map(name, "in_WRITE_QUEUE_IN_ADDRESS"      , _name, "in_WRITE_UNIT_IN_ADDRESS"      );
218
219
220       if (_param->_have_component_execute_queue)
221         {
222#ifdef POSITION
223           _component->interface_map (name ,"write_queue_out",
224                                      _name+"_execute_queue", "execute_queue_in");
225#endif
226
227           _component->port_map(name,"out_WRITE_QUEUE_OUT_VAL"          , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_VAL"          );
228           _component->port_map(name, "in_WRITE_QUEUE_OUT_ACK"          , _name+"_execute_queue","out_EXECUTE_QUEUE_IN_ACK"          );
229           if (_param->_have_port_context_id)
230           _component->port_map(name,"out_WRITE_QUEUE_OUT_CONTEXT_ID"   , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_CONTEXT_ID"   );
231           if (_param->_have_port_front_end_id)
232           _component->port_map(name,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_FRONT_END_ID" );
233           if (_param->_have_port_ooo_engine_id)
234           _component->port_map(name,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID");
235           if (_param->_have_port_rob_ptr)
236           _component->port_map(name,"out_WRITE_QUEUE_OUT_PACKET_ID"    , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_PACKET_ID"    );
237         //_component->port_map(name,"out_WRITE_QUEUE_OUT_OPERATION"    , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_OPERATION"    );
238         //_component->port_map(name,"out_WRITE_QUEUE_OUT_TYPE"         , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_TYPE"         );
239           _component->port_map(name,"out_WRITE_QUEUE_OUT_FLAGS"        , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_FLAGS"        );
240           _component->port_map(name,"out_WRITE_QUEUE_OUT_EXCEPTION"    , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_EXCEPTION"    );
241           _component->port_map(name,"out_WRITE_QUEUE_OUT_NO_SEQUENCE"  , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_NO_SEQUENCE"  );
242           _component->port_map(name,"out_WRITE_QUEUE_OUT_ADDRESS"      , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_ADDRESS"      );
243           _component->port_map(name,"out_WRITE_QUEUE_OUT_DATA"         , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_DATA"         );
244         }
245       else
246         {
247#ifdef POSITION
248           _component->interface_map (name ,"write_queue_out",
249                                      _name,"write_unit_out");
250#endif
251
252           _component->port_map(name,"out_WRITE_QUEUE_OUT_VAL"          , _name,"out_WRITE_UNIT_OUT_VAL"          );
253           _component->port_map(name, "in_WRITE_QUEUE_OUT_ACK"          , _name, "in_WRITE_UNIT_OUT_ACK"          );
254           if (_param->_have_port_context_id)
255           _component->port_map(name,"out_WRITE_QUEUE_OUT_CONTEXT_ID"   , _name,"out_WRITE_UNIT_OUT_CONTEXT_ID"   );
256           if (_param->_have_port_front_end_id)
257           _component->port_map(name,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , _name,"out_WRITE_UNIT_OUT_FRONT_END_ID" );
258           if (_param->_have_port_ooo_engine_id)
259           _component->port_map(name,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", _name,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID");
260           if (_param->_have_port_rob_ptr)
261           _component->port_map(name,"out_WRITE_QUEUE_OUT_PACKET_ID"    , _name,"out_WRITE_UNIT_OUT_PACKET_ID"    );
262         //_component->port_map(name,"out_WRITE_QUEUE_OUT_OPERATION"    , _name,"out_WRITE_UNIT_OUT_OPERATION"    );
263         //_component->port_map(name,"out_WRITE_QUEUE_OUT_TYPE"         , _name,"out_WRITE_UNIT_OUT_TYPE"         );
264           _component->port_map(name,"out_WRITE_QUEUE_OUT_FLAGS"        , _name,"out_WRITE_UNIT_OUT_FLAGS"        );
265           _component->port_map(name,"out_WRITE_QUEUE_OUT_EXCEPTION"    , _name,"out_WRITE_UNIT_OUT_EXCEPTION"    );
266           _component->port_map(name,"out_WRITE_QUEUE_OUT_NO_SEQUENCE"  , _name,"out_WRITE_UNIT_OUT_NO_SEQUENCE"  );
267           _component->port_map(name,"out_WRITE_QUEUE_OUT_ADDRESS"      , _name,"out_WRITE_UNIT_OUT_ADDRESS"      );
268           _component->port_map(name,"out_WRITE_QUEUE_OUT_DATA"         , _name,"out_WRITE_UNIT_OUT_DATA"         );
269         }       
270
271       for (uint32_t i=0; i<_param->_nb_gpr_write; i++)
272         {
273#ifdef POSITION
274           _component->interface_map (name ,"gpr_write_"+toString(i),
275                                      _name,"gpr_write_"+toString(i));
276#endif     
277           
278           _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_VAL"          ,_name,"out_GPR_WRITE_"+toString(i)+"_VAL"          );
279           _component->port_map(name, "in_GPR_WRITE_"+toString(i)+"_ACK"          ,_name, "in_GPR_WRITE_"+toString(i)+"_ACK"          );
280           if (_param->_have_port_ooo_engine_id)
281           _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
282           _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_NUM_REG"      ,_name,"out_GPR_WRITE_"+toString(i)+"_NUM_REG"      );
283           _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_DATA"         ,_name,"out_GPR_WRITE_"+toString(i)+"_DATA"         );
284         }
285
286       for (uint32_t i=0; i<_param->_nb_spr_write; i++)
287         {
288#ifdef POSITION
289           _component->interface_map (name ,"spr_write_"+toString(i),
290                                      _name,"spr_write_"+toString(i));
291#endif     
292           
293           _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_VAL"          ,_name,"out_SPR_WRITE_"+toString(i)+"_VAL"          );
294           _component->port_map(name, "in_SPR_WRITE_"+toString(i)+"_ACK"          ,_name, "in_SPR_WRITE_"+toString(i)+"_ACK"          );
295           if (_param->_have_port_ooo_engine_id)
296           _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
297           _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_NUM_REG"      ,_name,"out_SPR_WRITE_"+toString(i)+"_NUM_REG"      );
298           _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_DATA"         ,_name,"out_SPR_WRITE_"+toString(i)+"_DATA"         );
299         }
300
301
302       for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
303         {
304#ifdef POSITION
305           _component->interface_map (name ,"bypass_write_"+toString(i),
306                                      _name,"bypass_write_"+toString(i));
307#endif     
308
309           if (_param->_have_port_ooo_engine_id)
310           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
311           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL"      ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL"      );
312           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG"  ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG"  );
313           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA"     ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA"     );
314           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL"      ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL"      );
315           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG"  ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG"  );
316           _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA"     ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA"     );
317         }
318     }
319
320     if (_param->_have_component_execute_queue)
321       {
322         name = _name+"_execute_queue";
323         log_printf(INFO,Core,FUNCTION,_("Instance : %s"),name.c_str());
324         
325#ifdef POSITION
326         _component->interface_map (name ,"",
327                                    _name,"");
328#endif
329         
330         _component->port_map(name,"in_CLOCK" , _name, "in_CLOCK");
331         _component->port_map(name,"in_NRESET", _name, "in_NRESET");
332         
333
334#ifdef POSITION
335         _component->interface_map (name ,"execute_queue_in",
336                                    _name+"_write_queue","write_queue_in");
337#endif
338
339         _component->port_map(name, "in_EXECUTE_QUEUE_IN_VAL"          , _name+"_write_queue","out_WRITE_QUEUE_OUT_VAL"          );
340         _component->port_map(name,"out_EXECUTE_QUEUE_IN_ACK"          , _name+"_write_queue", "in_WRITE_QUEUE_OUT_ACK"          );
341         if (_param->_have_port_context_id)
342         _component->port_map(name, "in_EXECUTE_QUEUE_IN_CONTEXT_ID"   , _name+"_write_queue","out_WRITE_QUEUE_OUT_CONTEXT_ID"   );
343         if (_param->_have_port_front_end_id)
344         _component->port_map(name, "in_EXECUTE_QUEUE_IN_FRONT_END_ID" , _name+"_write_queue","out_WRITE_QUEUE_OUT_FRONT_END_ID" );
345         if (_param->_have_port_ooo_engine_id)
346         _component->port_map(name, "in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID", _name+"_write_queue","out_WRITE_QUEUE_OUT_OOO_ENGINE_ID");
347         if (_param->_have_port_rob_ptr)
348         _component->port_map(name, "in_EXECUTE_QUEUE_IN_PACKET_ID"    , _name+"_write_queue","out_WRITE_QUEUE_OUT_PACKET_ID"    );
349       //_component->port_map(name, "in_EXECUTE_QUEUE_IN_OPERATION"    , _name+"_write_queue","out_WRITE_QUEUE_OUT_OPERATION"    );
350       //_component->port_map(name, "in_EXECUTE_QUEUE_IN_TYPE"         , _name+"_write_queue","out_WRITE_QUEUE_OUT_TYPE"         );
351         _component->port_map(name, "in_EXECUTE_QUEUE_IN_FLAGS"        , _name+"_write_queue","out_WRITE_QUEUE_OUT_FLAGS"        );
352         _component->port_map(name, "in_EXECUTE_QUEUE_IN_EXCEPTION"    , _name+"_write_queue","out_WRITE_QUEUE_OUT_EXCEPTION"    );
353         _component->port_map(name, "in_EXECUTE_QUEUE_IN_NO_SEQUENCE"  , _name+"_write_queue","out_WRITE_QUEUE_OUT_NO_SEQUENCE"  );
354         _component->port_map(name, "in_EXECUTE_QUEUE_IN_ADDRESS"      , _name+"_write_queue","out_WRITE_QUEUE_OUT_ADDRESS"      );
355         _component->port_map(name, "in_EXECUTE_QUEUE_IN_DATA"         , _name+"_write_queue","out_WRITE_QUEUE_OUT_DATA"         );
356
357#ifdef POSITION
358         _component->interface_map (name ,"execute_queue_out",
359                                    _name,"write_unit_out");
360#endif
361
362         _component->port_map(name,"out_EXECUTE_QUEUE_OUT_VAL"          , _name,"out_WRITE_UNIT_OUT_VAL"          );
363         _component->port_map(name, "in_EXECUTE_QUEUE_OUT_ACK"          , _name, "in_WRITE_UNIT_OUT_ACK"          );
364         if (_param->_have_port_context_id)
365         _component->port_map(name,"out_EXECUTE_QUEUE_OUT_CONTEXT_ID"   , _name,"out_WRITE_UNIT_OUT_CONTEXT_ID"   );
366         if (_param->_have_port_front_end_id)
367         _component->port_map(name,"out_EXECUTE_QUEUE_OUT_FRONT_END_ID" , _name,"out_WRITE_UNIT_OUT_FRONT_END_ID" );
368         if (_param->_have_port_ooo_engine_id)
369         _component->port_map(name,"out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID", _name,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID");
370         if (_param->_have_port_rob_ptr)
371         _component->port_map(name,"out_EXECUTE_QUEUE_OUT_PACKET_ID"    , _name,"out_WRITE_UNIT_OUT_PACKET_ID"    );
372       //_component->port_map(name,"out_EXECUTE_QUEUE_OUT_OPERATION"    , _name,"out_WRITE_UNIT_OUT_OPERATION"    );
373       //_component->port_map(name,"out_EXECUTE_QUEUE_OUT_TYPE"         , _name,"out_WRITE_UNIT_OUT_TYPE"         );
374         _component->port_map(name,"out_EXECUTE_QUEUE_OUT_FLAGS"        , _name,"out_WRITE_UNIT_OUT_FLAGS"        );
375         _component->port_map(name,"out_EXECUTE_QUEUE_OUT_EXCEPTION"    , _name,"out_WRITE_UNIT_OUT_EXCEPTION"    );
376         _component->port_map(name,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE"  , _name,"out_WRITE_UNIT_OUT_NO_SEQUENCE"  );
377         _component->port_map(name,"out_EXECUTE_QUEUE_OUT_ADDRESS"      , _name,"out_WRITE_UNIT_OUT_ADDRESS"      );
378         _component->port_map(name,"out_EXECUTE_QUEUE_OUT_DATA"         , _name,"out_WRITE_UNIT_OUT_DATA"         );
379       }
380
381#ifdef POSITION
382    if (usage_is_set(_usage,USE_POSITION))
383      _component->generate_file();
384#endif
385
386    log_printf(FUNC,Write_unit,FUNCTION,"End");
387  };
388
389}; // end namespace write_unit
390}; // end namespace multi_write_unit
391}; // end namespace execute_loop
392}; // end namespace multi_execute_loop
393}; // end namespace core
394
395}; // end namespace behavioural
396}; // end namespace morpheo             
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