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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp @ 101

Last change on this file since 101 was 101, checked in by rosiere, 15 years ago
1) Add soc test 2) fix bug (Pc management, Decod and execute, Update prediction ...)
Property svn:keywords set to `Id`
File size: 52.1 KB

Line
1	/*
2	* $Id: test.cpp 101 2009-01-15 17:19:08Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/include/test.h"
10	#include "Behavioural/include/Allocation.h"
11
12	void test (string name,
13	morpheo::behavioural::core::multi_front_end::front_end::context_state::Parameters * _param)
14	{
15	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
16
17	#ifdef STATISTICS
18	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
19	#endif
20
21	Tusage_t _usage = USE_ALL;
22
23	// _usage = usage_unset(_usage,USE_SYSTEMC );
24	// _usage = usage_unset(_usage,USE_VHDL );
25	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
26	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
27	// _usage = usage_unset(_usage,USE_POSITION );
28	// _usage = usage_unset(_usage,USE_STATISTICS );
29	// _usage = usage_unset(_usage,USE_INFORMATION );
30
31	Context_State * _Context_State = new Context_State
32	(name.c_str(),
33	#ifdef STATISTICS
34	_parameters_statistics,
35	#endif
36	_param,
37	_usage);
38
39	#ifdef SYSTEMC
40	if (usage_is_set(_usage,USE_SYSTEMC))
41	{
42	/*********************************************************************
43	* Déclarations des signaux
44	*********************************************************************/
45	string rename;
46
47	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
48	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
49
50	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_VAL ," in_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
51	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,"out_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
52	//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ," in_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
53	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
54	//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ," in_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context);
55	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ," in_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
56	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST_VAL ," in_BRANCH_EVENT_ADDRESS_DEST_VAL ",Tcontrol_t ,_param->_nb_context);
57	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ," in_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
58
59	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_VAL ," in_DECOD_EVENT_VAL ",Tcontrol_t ,_param->_nb_decod_unit);
60	ALLOC1_SC_SIGNAL(out_DECOD_EVENT_ACK ,"out_DECOD_EVENT_ACK ",Tcontrol_t ,_param->_nb_decod_unit);
61	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_CONTEXT_ID ," in_DECOD_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_decod_unit);
62	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_DEPTH ," in_DECOD_EVENT_DEPTH ",Tdepth_t ,_param->_nb_decod_unit);
63	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_TYPE ," in_DECOD_EVENT_TYPE ",Tevent_type_t,_param->_nb_decod_unit);
64	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_IS_DELAY_SLOT ," in_DECOD_EVENT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_decod_unit);
65	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ," in_DECOD_EVENT_ADDRESS ",Taddress_t ,_param->_nb_decod_unit);
66	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ," in_DECOD_EVENT_ADDRESS_EPCR ",Taddress_t ,_param->_nb_decod_unit);
67
68	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t );
69	ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t );
70	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t );
71	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t );
72	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t);
73	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t );
74	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t );
75	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t );
76	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t );
77	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t);
78
79	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
80	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
81	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
82	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
83	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION," in_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
84	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_TAKE ," in_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
85	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ," in_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
86	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ," in_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
87
88
89	ALLOC1_SC_SIGNAL( in_NB_INST_DECOD_ALL ," in_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context );
90	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_context );
91	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_context );
92
93	ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context );
94	ALLOC1_SC_SIGNAL( in_EVENT_ACK ," in_EVENT_ACK ",Tcontrol_t ,_param->_nb_context );
95	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS ,"out_EVENT_ADDRESS ",Taddress_t ,_param->_nb_context );
96	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,"out_EVENT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_context );
97	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,"out_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ,_param->_nb_context );
98	ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context );
99	ALLOC1_SC_SIGNAL(out_EVENT_TYPE ,"out_EVENT_TYPE ",Tevent_type_t,_param->_nb_context );
100	ALLOC1_SC_SIGNAL(out_EVENT_DEPTH ,"out_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context );
101
102	ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL ,"out_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_context );
103	ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK ," in_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_context );
104	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EPCR ,"out_SPR_EVENT_EPCR ",Taddress_t ,_param->_nb_context );
105	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR ,"out_SPR_EVENT_EEAR ",Taddress_t ,_param->_nb_context );
106	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,"out_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_context );
107	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,"out_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_context );
108	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,"out_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_context );
109
110	ALLOC1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,"out_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context );
111
112	ALLOC1_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_context );
113
114	ALLOC1_SC_SIGNAL( in_SPR_SR_IEE ," in_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_context );
115	ALLOC1_SC_SIGNAL( in_SPR_SR_EPH ," in_SPR_SR_EPH ",Tcontrol_t ,_param->_nb_context );
116
117	ALLOC1_SC_SIGNAL( in_INTERRUPT_ENABLE ," in_INTERRUPT_ENABLE ",Tcontrol_t ,_param->_nb_context );
118
119	/********************************************************
120	* Instanciation
121	********************************************************/
122
123	msg(_("<%s> : Instanciation of _Context_State.\n"),name.c_str());
124
125	((_Context_State->in_CLOCK)) ((in_CLOCK));
126	((_Context_State->in_NRESET)) ((in_NRESET));
127
128	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_VAL ,_param->_nb_context);
129	INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_EVENT_ACK ,_param->_nb_context);
130	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
131	if (_param->_have_port_depth)
132	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_DEPTH ,_param->_nb_context);
133	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context);
134	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
135	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context);
136	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
137	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_VAL ,_param->_nb_decod_unit);
138	INSTANCE1_SC_SIGNAL(_Context_State,out_DECOD_EVENT_ACK ,_param->_nb_decod_unit);
139	if (_param->_have_port_context_id)
140	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit);
141	if (_param->_have_port_depth)
142	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit);
143	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit);
144	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_IS_DELAY_SLOT ,_param->_nb_decod_unit);
145	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit);
146	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit);
147
148	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_VAL );
149	INSTANCE_SC_SIGNAL (_Context_State,out_COMMIT_EVENT_ACK );
150	if (_param->_have_port_context_id)
151	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_CONTEXT_ID );
152	if (_param->_have_port_depth)
153	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_DEPTH );
154	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_TYPE );
155	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_IS_DELAY_SLOT );
156	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS );
157	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR );
158	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
159	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR );
160
161	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
162	INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
163	if (_param->_have_port_context_id)
164	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
165	if (_param->_have_port_depth)
166	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
167	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
168	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
169	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
170	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
171
172	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_DECOD_ALL ,_param->_nb_context );
173	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_ALL ,_param->_nb_context );
174	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_MEM ,_param->_nb_context );
175
176	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_VAL ,_param->_nb_context );
177	INSTANCE1_SC_SIGNAL(_Context_State, in_EVENT_ACK ,_param->_nb_context );
178	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS ,_param->_nb_context );
179	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT ,_param->_nb_context );
180	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context );
181	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_IS_DS_TAKE ,_param->_nb_context );
182	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_TYPE ,_param->_nb_context );
183	if (_param->_have_port_depth)
184	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_DEPTH ,_param->_nb_context );
185
186	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_VAL ,_param->_nb_context );
187	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_EVENT_ACK ,_param->_nb_context );
188	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EPCR ,_param->_nb_context );
189	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EEAR ,_param->_nb_context );
190	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EEAR_WEN ,_param->_nb_context );
191	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_SR_DSX ,_param->_nb_context );
192	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context );
193
194	INSTANCE1_SC_SIGNAL(_Context_State,out_CONTEXT_DECOD_ENABLE ,_param->_nb_context );
195
196	for (uint32_t i=0; i<_param->_nb_context; i++)
197	if (_param->_have_port_depth)
198	INSTANCE_SC_SIGNAL(_Context_State, in_DEPTH_MIN [i]);
199
200	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_IEE ,_param->_nb_context );
201	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_EPH ,_param->_nb_context );
202
203	INSTANCE1_SC_SIGNAL(_Context_State, in_INTERRUPT_ENABLE ,_param->_nb_context );
204
205	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
206
207	Time * _time = new Time();
208
209	/********************************************************
210	* Simulation - Begin
211	********************************************************/
212
213	// Initialisation
214
215	const bool test1 = true;
216	const bool test2 = true;
217	const bool test3 = true;
218	const bool test4 = true;
219	const bool test5 = true;
220	const bool test6 = true;
221	const bool test7 = true;
222	const bool test8 = true;
223	const bool test9 = true;
224	const bool test10 = true;
225	const bool test11 = true;
226	const bool test12 = true;
227
228	const uint32_t seed = 0;
229	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
230
231	srand(seed);
232
233	const int32_t percent_transaction_branch_event = 75;
234	const int32_t percent_transaction_decod_event = 75;
235	const int32_t percent_transaction_commit_event = 75;
236	//const int32_t percent_transaction_branch_complete = 75;
237	const int32_t percent_transaction_event = 75;
238	const int32_t percent_transaction_spr = 75;
239
240	SC_START(0);
241	LABEL("Initialisation");
242
243	LABEL("Reset");
244	in_NRESET->write(0);
245	SC_START(5);
246	in_NRESET->write(1);
247
248	LABEL("Loop of Test");
249
250	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
251	{
252	LABEL("Iteration %d",iteration);
253	for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
254	in_DECOD_EVENT_VAL [i]->write(0);
255	in_COMMIT_EVENT_VAL ->write(0);
256	// for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
257	// in_BRANCH_COMPLETE_VAL [i]->write(0);
258	for (uint32_t i=0; i<_param->_nb_context; i++)
259	in_BRANCH_EVENT_VAL [i]->write(0);
260
261	for (uint32_t i=0; i<_param->_nb_context; i++)
262	{
263	in_BRANCH_EVENT_VAL [i]->write(0);
264	in_EVENT_ACK [i]->write(0);
265	in_SPR_EVENT_ACK [i]->write(0);
266	in_SPR_SR_IEE [i]->write(0);
267	in_SPR_SR_EPH [i]->write(0);
268	in_INTERRUPT_ENABLE [i]->write(0);
269
270	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[i]->read(), 1);
271	}
272
273	for (uint32_t i=0; i<_param->_nb_context; i++)
274	if (_param->_have_port_depth)
275	in_DEPTH_MIN [i]->write((_param->_array_size_depth[i]==0)?0:(i%_param->_array_size_depth[i]));
276
277	uint32_t context = rand()%_param->_nb_context;
278
279	if (test1)
280	{
281	SC_START(3);
282
283	LABEL("msync (begin)");
284	in_NB_INST_DECOD_ALL [context]->write(1);
285	in_NB_INST_COMMIT_ALL [context]->write(1);
286	in_NB_INST_COMMIT_MEM [context]->write(1);
287
288	uint32_t port = rand()%_param->_nb_decod_unit;
289
290	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
291	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
292	in_DECOD_EVENT_ADDRESS [port]->write(0x100);
293	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef);
294	if (_param->_have_port_depth)
295	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
296	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_MSYNC);
297
298	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
299
300	in_DECOD_EVENT_VAL [port]->write(1);
301
302	SC_START(0);
303	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
304	TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 0);
305
306	SC_START(1);
307
308	in_NB_INST_DECOD_ALL [context]->write(0);
309	in_NB_INST_COMMIT_ALL [context]->write(0);
310	in_NB_INST_COMMIT_MEM [context]->write(0);
311
312	LABEL("msync (send decod)");
313	SC_START(0);
314	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
315	TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 1);
316
317	SC_START(1);
318
319	in_DECOD_EVENT_VAL [port]->write(0);
320	in_NB_INST_COMMIT_ALL [context]->write(1);
321
322	LABEL("msync (wait end)");
323	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
324
325	SC_START(3);
326
327	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
328	in_NB_INST_COMMIT_ALL [context]->write(0);
329
330	SC_START(1);
331	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
332	}
333
334	if (test2)
335	{
336	SC_START(3);
337
338	LABEL("psync (begin)");
339	in_NB_INST_DECOD_ALL [context]->write(1);
340	in_NB_INST_COMMIT_ALL [context]->write(1);
341	in_NB_INST_COMMIT_MEM [context]->write(1);
342
343	uint32_t port = rand()%_param->_nb_decod_unit;
344
345	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
346	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
347	in_DECOD_EVENT_ADDRESS [port]->write(0x200);
348	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe);
349	if (_param->_have_port_depth)
350	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
351	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_PSYNC);
352
353	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
354
355	in_DECOD_EVENT_VAL [port]->write(1);
356
357	SC_START(0);
358	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
359	TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 0);
360
361	SC_START(1);
362
363	in_NB_INST_DECOD_ALL [context]->write(0);
364	in_NB_INST_COMMIT_ALL [context]->write(0);
365	in_NB_INST_COMMIT_MEM [context]->write(0);
366
367	LABEL("psync (send decod)");
368	SC_START(0);
369	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
370	TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 1);
371
372	SC_START(1);
373
374	in_DECOD_EVENT_VAL [port]->write(0);
375	in_NB_INST_COMMIT_ALL [context]->write(1);
376
377	LABEL("psync (wait end)");
378	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
379
380	SC_START(3);
381
382	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
383	in_NB_INST_COMMIT_ALL [context]->write(0);
384
385	SC_START(1);
386
387	bool find = false;
388	do
389	{
390	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
391
392	SC_START(0);
393
394	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
395	{
396	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x201);
397	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdeadbebe);
398	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
399	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
400
401	find = true;
402	}
403
404	SC_START(1);
405	}
406	while (not find);
407
408	in_EVENT_ACK [context]->write(0);
409	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
410	}
411
412	if (test3)
413	{
414	SC_START(3);
415
416	LABEL("csync (begin)");
417	in_NB_INST_DECOD_ALL [context]->write(1);
418	in_NB_INST_COMMIT_ALL [context]->write(1);
419	in_NB_INST_COMMIT_MEM [context]->write(1);
420
421	uint32_t port = rand()%_param->_nb_decod_unit;
422
423	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
424	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
425	in_DECOD_EVENT_ADDRESS [port]->write(0x300);
426	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdead0300);
427	if (_param->_have_port_depth)
428	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
429	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_CSYNC);
430
431	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
432
433	in_DECOD_EVENT_VAL [port]->write(1);
434
435	SC_START(0);
436	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
437	TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 0);
438
439	SC_START(1);
440
441	in_NB_INST_DECOD_ALL [context]->write(0);
442	in_NB_INST_COMMIT_ALL [context]->write(0);
443	in_NB_INST_COMMIT_MEM [context]->write(0);
444
445	LABEL("csync (send decod)");
446	SC_START(0);
447	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
448	TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 1);
449
450	SC_START(1);
451
452	in_DECOD_EVENT_VAL [port]->write(0);
453	in_NB_INST_COMMIT_ALL [context]->write(1);
454
455	LABEL("csync (wait end)");
456	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
457
458	SC_START(3);
459
460	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
461	in_NB_INST_COMMIT_ALL [context]->write(0);
462
463	SC_START(1);
464
465	bool find = false;
466	do
467	{
468	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
469
470	SC_START(0);
471
472	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
473	{
474	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x301);
475	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdead0300);
476	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
477	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
478
479	find = true;
480	}
481
482	SC_START(1);
483	}
484	while (not find);
485
486	in_EVENT_ACK [context]->write(0);
487	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
488
489	}
490
491	if (test4)
492	{
493	SC_START(3);
494
495	LABEL("spr_access (begin)");
496	in_NB_INST_DECOD_ALL [context]->write(1);
497	in_NB_INST_COMMIT_ALL [context]->write(1);
498	in_NB_INST_COMMIT_MEM [context]->write(1);
499
500	uint32_t port = rand()%_param->_nb_decod_unit;
501
502	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
503	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
504	in_DECOD_EVENT_ADDRESS [port]->write(0x400);
505	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdead0400);
506	if (_param->_have_port_depth)
507	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
508	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_SPR_ACCESS);
509
510	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
511
512	in_DECOD_EVENT_VAL [port]->write(1);
513
514	SC_START(0);
515	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
516	TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 0);
517
518	SC_START(1);
519
520	in_NB_INST_DECOD_ALL [context]->write(0);
521	in_NB_INST_COMMIT_ALL [context]->write(0);
522	in_NB_INST_COMMIT_MEM [context]->write(0);
523
524	LABEL("spr_access (send decod)");
525	SC_START(0);
526	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
527	TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 1);
528
529	SC_START(1);
530
531	in_DECOD_EVENT_VAL [port]->write(0);
532	in_NB_INST_COMMIT_ALL [context]->write(1);
533
534	LABEL("spr_access (wait end)");
535	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
536
537	SC_START(3);
538
539	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
540	in_NB_INST_COMMIT_ALL [context]->write(0);
541
542	SC_START(1);
543	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
544	}
545
546	if (test5)
547	{
548	SC_START(3);
549
550	LABEL("miss (begin)");
551	in_NB_INST_DECOD_ALL [context]->write(1);
552	in_NB_INST_COMMIT_ALL [context]->write(1);
553	in_NB_INST_COMMIT_MEM [context]->write(1);
554
555	// uint32_t port = rand()%_param->_nb_inst_branch_complete;
556
557	// in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context);
558	// if (_param->_have_port_depth)
559	// in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
560	// in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400);
561	// in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500);
562	// in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1);
563	// in_BRANCH_COMPLETE_TAKE [port]->write(0);
564
565	// TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
566
567	// do
568	// {
569	// in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
570
571	// SC_START(1);
572	// }
573	// while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
574	// out_BRANCH_COMPLETE_ACK [port]->read()));
575	// in_BRANCH_COMPLETE_VAL [port]->write(0);
576
577	uint32_t port = context;
578
579	if (_param->_have_port_depth)
580	in_BRANCH_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
581	in_BRANCH_EVENT_ADDRESS_SRC [port]->write(0x400);
582	in_BRANCH_EVENT_ADDRESS_DEST [port]->write(0x500);
583	in_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->write(0);
584
585	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
586
587	do
588	{
589	in_BRANCH_EVENT_VAL [port]->write(rand()%percent_transaction_branch_event);
590
591	SC_START(1);
592	}
593	while (not ( in_BRANCH_EVENT_VAL [port]->read() and
594	out_BRANCH_EVENT_ACK [port]->read()));
595	in_BRANCH_EVENT_VAL [port]->write(0);
596
597	LABEL("miss (wait end)");
598	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
599
600	SC_START(3);
601
602	in_NB_INST_DECOD_ALL [context]->write(0);
603	in_NB_INST_COMMIT_ALL [context]->write(0);
604	in_NB_INST_COMMIT_MEM [context]->write(0);
605
606	SC_START(1);
607
608	LABEL("miss (wait event)");
609
610
611	bool find = false;
612	do
613	{
614	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
615
616	SC_START(0);
617
618	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
619	{
620	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x401);
621	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x500);
622	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
623	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
624
625	find = true;
626	}
627
628	SC_START(1);
629	}
630	while (not find);
631
632	in_EVENT_ACK [context]->write(0);
633
634	}
635
636	if (test6)
637	{
638	SC_START(3);
639
640	LABEL("miss (begin)");
641	in_NB_INST_DECOD_ALL [context]->write(1);
642	in_NB_INST_COMMIT_ALL [context]->write(1);
643	in_NB_INST_COMMIT_MEM [context]->write(1);
644
645	// uint32_t port = rand()%_param->_nb_inst_branch_complete;
646
647	// in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context);
648	// if (_param->_have_port_depth)
649	// in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
650	// in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600);
651	// in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700);
652	// in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1);
653	// in_BRANCH_COMPLETE_TAKE [port]->write(1);
654
655	// TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
656
657	// do
658	// {
659	// in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
660
661	// SC_START(1);
662	// }
663	// while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
664	// out_BRANCH_COMPLETE_ACK [port]->read()));
665	// in_BRANCH_COMPLETE_VAL [port]->write(0);
666
667	uint32_t port = context;
668
669	in_BRANCH_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
670	in_BRANCH_EVENT_ADDRESS_SRC [port]->write(0x600);
671	in_BRANCH_EVENT_ADDRESS_DEST [port]->write(0x700);
672	in_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->write(1);
673
674	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
675
676	do
677	{
678	in_BRANCH_EVENT_VAL [port]->write(rand()%percent_transaction_branch_event);
679
680	SC_START(1);
681	}
682	while (not ( in_BRANCH_EVENT_VAL [port]->read() and
683	out_BRANCH_EVENT_ACK [port]->read()));
684	in_BRANCH_EVENT_VAL [port]->write(0);
685
686	LABEL("miss (wait end)");
687	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
688
689	SC_START(3);
690
691	in_NB_INST_DECOD_ALL [context]->write(0);
692	in_NB_INST_COMMIT_ALL [context]->write(0);
693	in_NB_INST_COMMIT_MEM [context]->write(0);
694
695	SC_START(1);
696
697	LABEL("miss (wait event)");
698
699	bool find = false;
700	do
701	{
702	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
703
704	SC_START(0);
705
706	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
707	{
708	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x601);
709	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x700);
710	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),1);
711	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),1);
712
713	find = true;
714	}
715
716	SC_START(1);
717	}
718	while (not find);
719
720	in_EVENT_ACK [context]->write(0);
721	}
722
723	if (test7)
724	{
725	SC_START(3);
726
727	LABEL("exception (begin)");
728	in_NB_INST_DECOD_ALL [context]->write(1);
729	in_NB_INST_COMMIT_ALL [context]->write(1);
730	in_NB_INST_COMMIT_MEM [context]->write(1);
731
732	uint32_t port = rand()%_param->_nb_decod_unit;
733
734	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
735	if (_param->_have_port_depth)
736	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
737	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
738	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
739	in_DECOD_EVENT_ADDRESS [port]->write(0x800);
740	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0x900);
741
742	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
743
744	do
745	{
746	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
747
748	SC_START(1);
749	}
750	while (not ( in_DECOD_EVENT_VAL [port]->read() and
751	out_DECOD_EVENT_ACK [port]->read()));
752	in_DECOD_EVENT_VAL [port]->write(0);
753
754	LABEL("exception (wait end)");
755	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
756
757	SC_START(3);
758
759	in_NB_INST_DECOD_ALL [context]->write(0);
760	in_NB_INST_COMMIT_ALL [context]->write(0);
761	in_NB_INST_COMMIT_MEM [context]->write(0);
762
763	SC_START(1);
764
765	LABEL("exception (wait event)");
766
767	bool find = false;
768	do
769	{
770	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
771
772	SC_START(0);
773
774	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
775	{
776	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x800);
777	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x900);
778	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
779	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
780
781	find = true;
782	}
783
784	SC_START(1);
785	}
786	while (not find);
787
788	in_EVENT_ACK [context]->write(0);
789
790	LABEL("exception (wait spr)");
791
792	find = false;
793	do
794	{
795	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
796
797	SC_START(0);
798
799	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
800	{
801	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0x900);
802	//TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),);
803	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
804	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
805	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
806
807	find = true;
808	}
809
810	SC_START(1);
811	}
812	while (not find);
813
814	in_SPR_EVENT_ACK [context]->write(0);
815	}
816
817	if (test8)
818	{
819	SC_START(3);
820
821	LABEL("exception (begin)");
822	in_NB_INST_DECOD_ALL [context]->write(1);
823	in_NB_INST_COMMIT_ALL [context]->write(1);
824	in_NB_INST_COMMIT_MEM [context]->write(1);
825
826	uint32_t port = rand()%_param->_nb_decod_unit;
827
828	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
829	if (_param->_have_port_depth)
830	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
831	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
832	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(1);
833	in_DECOD_EVENT_ADDRESS [port]->write(0x800);
834	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0x900);
835
836	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
837
838	do
839	{
840	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
841
842	SC_START(1);
843	}
844	while (not ( in_DECOD_EVENT_VAL [port]->read() and
845	out_DECOD_EVENT_ACK [port]->read()));
846	in_DECOD_EVENT_VAL [port]->write(0);
847
848	LABEL("exception (wait end)");
849	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
850
851	SC_START(3);
852
853	in_NB_INST_DECOD_ALL [context]->write(0);
854	in_NB_INST_COMMIT_ALL [context]->write(0);
855	in_NB_INST_COMMIT_MEM [context]->write(0);
856
857	SC_START(1);
858
859	LABEL("exception (wait event)");
860
861	bool find = false;
862	do
863	{
864	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
865
866	SC_START(0);
867
868	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
869	{
870	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x800);
871	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x900);
872	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
873	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
874
875	find = true;
876	}
877
878	SC_START(1);
879	}
880	while (not find);
881
882	in_EVENT_ACK [context]->write(0);
883
884	LABEL("exception (wait spr)");
885
886	find = false;
887	do
888	{
889	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
890
891	SC_START(0);
892
893	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
894	{
895	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0x900);
896	//TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),);
897	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
898	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
899	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
900
901	find = true;
902	}
903
904	SC_START(1);
905	}
906	while (not find);
907
908	in_SPR_EVENT_ACK [context]->write(0);
909	}
910
911	if (test9)
912	{
913	SC_START(3);
914
915	LABEL("exception (begin)");
916	in_NB_INST_DECOD_ALL [context]->write(1);
917	in_NB_INST_COMMIT_ALL [context]->write(1);
918	in_NB_INST_COMMIT_MEM [context]->write(1);
919
920	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
921	if (_param->_have_port_depth)
922	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
923	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
924	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0);
925	in_COMMIT_EVENT_ADDRESS ->write(0xa00);
926	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00);
927	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00);
928	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0);
929
930	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
931
932	do
933	{
934	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
935
936	SC_START(1);
937	}
938	while (not ( in_COMMIT_EVENT_VAL ->read() and
939	out_COMMIT_EVENT_ACK ->read()));
940	in_COMMIT_EVENT_VAL ->write(0);
941
942	LABEL("exception (wait end)");
943	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
944
945	SC_START(3);
946
947	in_NB_INST_DECOD_ALL [context]->write(0);
948	in_NB_INST_COMMIT_ALL [context]->write(0);
949	in_NB_INST_COMMIT_MEM [context]->write(0);
950
951	SC_START(1);
952
953	LABEL("exception (wait event)");
954
955	bool find = false;
956	do
957	{
958	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
959
960	SC_START(0);
961
962	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
963	{
964	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xa00);
965	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xb00);
966	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
967	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
968
969	find = true;
970	}
971
972	SC_START(1);
973	}
974	while (not find);
975
976	in_EVENT_ACK [context]->write(0);
977
978	LABEL("exception (wait spr)");
979
980	find = false;
981	do
982	{
983	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
984
985	SC_START(0);
986
987	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
988	{
989	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xb00);
990	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xc00);
991	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
992	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
993	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
994
995	find = true;
996	}
997
998	SC_START(1);
999	}
1000	while (not find);
1001
1002	in_SPR_EVENT_ACK [context]->write(0);
1003	}
1004
1005	if (test10)
1006	{
1007	SC_START(3);
1008
1009	LABEL("exception (begin)");
1010	in_NB_INST_DECOD_ALL [context]->write(1);
1011	in_NB_INST_COMMIT_ALL [context]->write(1);
1012	in_NB_INST_COMMIT_MEM [context]->write(1);
1013
1014	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
1015	if (_param->_have_port_depth)
1016	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
1017	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
1018	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1);
1019	in_COMMIT_EVENT_ADDRESS ->write(0xd00);
1020	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00);
1021	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00);
1022	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0);
1023
1024	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1025
1026	do
1027	{
1028	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
1029
1030	SC_START(1);
1031	}
1032	while (not ( in_COMMIT_EVENT_VAL ->read() and
1033	out_COMMIT_EVENT_ACK ->read()));
1034	in_COMMIT_EVENT_VAL ->write(0);
1035
1036	LABEL("exception (wait end)");
1037	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1038
1039	SC_START(3);
1040
1041	in_NB_INST_DECOD_ALL [context]->write(0);
1042	in_NB_INST_COMMIT_ALL [context]->write(0);
1043	in_NB_INST_COMMIT_MEM [context]->write(0);
1044
1045	SC_START(1);
1046
1047	LABEL("exception (wait event)");
1048
1049	bool find = false;
1050	do
1051	{
1052	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1053
1054	SC_START(0);
1055
1056	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1057	{
1058	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xd00);
1059	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xe00);
1060	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1061	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1062
1063	find = true;
1064	}
1065
1066	SC_START(1);
1067	}
1068	while (not find);
1069
1070	in_EVENT_ACK [context]->write(0);
1071
1072	LABEL("exception (wait spr)");
1073
1074	find = false;
1075	do
1076	{
1077	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1078
1079	SC_START(0);
1080
1081	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1082	{
1083	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xe00);
1084	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xf00);
1085	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
1086	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
1087	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1088
1089	find = true;
1090	}
1091
1092	SC_START(1);
1093	}
1094	while (not find);
1095
1096	in_SPR_EVENT_ACK [context]->write(0);
1097	}
1098
1099	if (test11)
1100	{
1101	SC_START(3);
1102
1103	LABEL("exception (begin)");
1104	in_NB_INST_DECOD_ALL [context]->write(1);
1105	in_NB_INST_COMMIT_ALL [context]->write(1);
1106	in_NB_INST_COMMIT_MEM [context]->write(1);
1107
1108	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
1109	if (_param->_have_port_depth)
1110	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
1111	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
1112	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0);
1113	in_COMMIT_EVENT_ADDRESS ->write(0xa00);
1114	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00);
1115	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00);
1116	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1);
1117
1118	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1119
1120	do
1121	{
1122	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
1123
1124	SC_START(1);
1125	}
1126	while (not ( in_COMMIT_EVENT_VAL ->read() and
1127	out_COMMIT_EVENT_ACK ->read()));
1128	in_COMMIT_EVENT_VAL ->write(0);
1129
1130	LABEL("exception (wait end)");
1131	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1132
1133	SC_START(3);
1134
1135	in_NB_INST_DECOD_ALL [context]->write(0);
1136	in_NB_INST_COMMIT_ALL [context]->write(0);
1137	in_NB_INST_COMMIT_MEM [context]->write(0);
1138
1139	SC_START(1);
1140
1141	LABEL("exception (wait event)");
1142
1143	bool find = false;
1144	do
1145	{
1146	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1147
1148	SC_START(0);
1149
1150	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1151	{
1152	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xa00);
1153	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xb00);
1154	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1155	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1156
1157	find = true;
1158	}
1159
1160	SC_START(1);
1161	}
1162	while (not find);
1163
1164	in_EVENT_ACK [context]->write(0);
1165
1166	LABEL("exception (wait spr)");
1167
1168	find = false;
1169	do
1170	{
1171	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1172
1173	SC_START(0);
1174
1175	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1176	{
1177	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xb00);
1178	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xc00);
1179	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),1);
1180	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
1181	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1182
1183	find = true;
1184	}
1185
1186	SC_START(1);
1187	}
1188	while (not find);
1189
1190	in_SPR_EVENT_ACK [context]->write(0);
1191	}
1192
1193	if (test12)
1194	{
1195	SC_START(3);
1196
1197	LABEL("exception (begin)");
1198	in_NB_INST_DECOD_ALL [context]->write(1);
1199	in_NB_INST_COMMIT_ALL [context]->write(1);
1200	in_NB_INST_COMMIT_MEM [context]->write(1);
1201
1202	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
1203	if (_param->_have_port_depth)
1204	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
1205	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
1206	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1);
1207	in_COMMIT_EVENT_ADDRESS ->write(0xd00);
1208	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00);
1209	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00);
1210	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1);
1211
1212	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1213
1214	do
1215	{
1216	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
1217
1218	SC_START(1);
1219	}
1220	while (not ( in_COMMIT_EVENT_VAL ->read() and
1221	out_COMMIT_EVENT_ACK ->read()));
1222	in_COMMIT_EVENT_VAL ->write(0);
1223
1224	LABEL("exception (wait end)");
1225	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1226
1227	SC_START(3);
1228
1229	in_NB_INST_DECOD_ALL [context]->write(0);
1230	in_NB_INST_COMMIT_ALL [context]->write(0);
1231	in_NB_INST_COMMIT_MEM [context]->write(0);
1232
1233	SC_START(1);
1234
1235	LABEL("exception (wait event)");
1236
1237	bool find = false;
1238	do
1239	{
1240	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1241
1242	SC_START(0);
1243
1244	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1245	{
1246	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xd00);
1247	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xe00);
1248	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1249	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1250
1251	find = true;
1252	}
1253
1254	SC_START(1);
1255	}
1256	while (not find);
1257
1258	in_EVENT_ACK [context]->write(0);
1259
1260	LABEL("exception (wait spr)");
1261
1262	find = false;
1263	do
1264	{
1265	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1266
1267	SC_START(0);
1268
1269	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1270	{
1271	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xe00);
1272	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xf00);
1273	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),1);
1274	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
1275	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1276
1277	find = true;
1278	}
1279
1280	SC_START(1);
1281	}
1282	while (not find);
1283
1284	in_SPR_EVENT_ACK [context]->write(0);
1285	}
1286
1287
1288	SC_START(1);
1289	}
1290
1291
1292	/********************************************************
1293	* Simulation - End
1294	********************************************************/
1295
1296	TEST_OK ("End of Simulation");
1297	delete _time;
1298
1299	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
1300
1301	delete in_CLOCK;
1302	delete in_NRESET;
1303
1304	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_VAL ,_param->_nb_context);
1305	DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,_param->_nb_context);
1306	//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
1307	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context);
1308	//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context);
1309	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
1310	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context);
1311	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
1312	DELETE1_SC_SIGNAL( in_DECOD_EVENT_VAL ,_param->_nb_decod_unit);
1313	DELETE1_SC_SIGNAL(out_DECOD_EVENT_ACK ,_param->_nb_decod_unit);
1314	DELETE1_SC_SIGNAL( in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit);
1315	DELETE1_SC_SIGNAL( in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit);
1316	DELETE1_SC_SIGNAL( in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit);
1317	DELETE1_SC_SIGNAL( in_DECOD_EVENT_IS_DELAY_SLOT ,_param->_nb_decod_unit);
1318	DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit);
1319	DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit);
1320	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_VAL );
1321	DELETE_SC_SIGNAL (out_COMMIT_EVENT_ACK );
1322	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID );
1323	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_DEPTH );
1324	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_TYPE );
1325	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT );
1326	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS );
1327	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR );
1328	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
1329	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR );
1330	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
1331	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
1332	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
1333	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
1334	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
1335	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
1336	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
1337	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
1338	DELETE1_SC_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_context );
1339	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context );
1340	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context );
1341	DELETE1_SC_SIGNAL(out_EVENT_VAL ,_param->_nb_context );
1342	DELETE1_SC_SIGNAL( in_EVENT_ACK ,_param->_nb_context );
1343	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context );
1344	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context );
1345	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context );
1346	DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context );
1347	DELETE1_SC_SIGNAL(out_EVENT_TYPE ,_param->_nb_context );
1348	DELETE1_SC_SIGNAL(out_EVENT_DEPTH ,_param->_nb_context );
1349	DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context );
1350	DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context );
1351	DELETE1_SC_SIGNAL(out_SPR_EVENT_EPCR ,_param->_nb_context );
1352	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR ,_param->_nb_context );
1353	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,_param->_nb_context );
1354	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,_param->_nb_context );
1355	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context );
1356	DELETE1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,_param->_nb_context );
1357	DELETE1_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_context );
1358	DELETE1_SC_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context );
1359	DELETE1_SC_SIGNAL( in_SPR_SR_EPH ,_param->_nb_context );
1360
1361	DELETE1_SC_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_context );
1362	}
1363	#endif
1364
1365	delete _Context_State;
1366	#ifdef STATISTICS
1367	delete _parameters_statistics;
1368	#endif
1369	}

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