Context Navigation

test.cpp @ 119

Last change on this file since 119 was 119, checked in by rosiere, 15 years ago
1) Prediction unit : static prediction not blocking
Property svn:keywords set to `Id`
File size: 54.5 KB

Line
1	/*
2	* $Id: test.cpp 119 2009-05-25 17:40:26Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/include/test.h"
10	#include "Behavioural/include/Allocation.h"
11
12	void test (string name,
13	morpheo::behavioural::core::multi_front_end::front_end::context_state::Parameters * _param)
14	{
15	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
16
17	#ifdef STATISTICS
18	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
19	#endif
20
21	Tusage_t _usage = USE_ALL;
22
23	// _usage = usage_unset(_usage,USE_SYSTEMC );
24	// _usage = usage_unset(_usage,USE_VHDL );
25	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
26	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
27	// _usage = usage_unset(_usage,USE_POSITION );
28	// _usage = usage_unset(_usage,USE_STATISTICS );
29	// _usage = usage_unset(_usage,USE_INFORMATION );
30
31	Context_State * _Context_State = new Context_State
32	(name.c_str(),
33	#ifdef STATISTICS
34	_parameters_statistics,
35	#endif
36	_param,
37	_usage);
38
39	#ifdef SYSTEMC
40	if (usage_is_set(_usage,USE_SYSTEMC))
41	{
42	/*********************************************************************
43	* Déclarations des signaux
44	*********************************************************************/
45	string rename;
46
47	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
48	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
49
50	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_VAL ," in_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
51	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,"out_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
52	//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ," in_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
53	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
54	//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ," in_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context);
55	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ," in_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
56	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST_VAL ," in_BRANCH_EVENT_ADDRESS_DEST_VAL ",Tcontrol_t ,_param->_nb_context);
57	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ," in_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
58	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CAN_CONTINUE ," in_BRANCH_EVENT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_context);
59
60	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_VAL ," in_DECOD_EVENT_VAL ",Tcontrol_t ,_param->_nb_decod_unit);
61	ALLOC1_SC_SIGNAL(out_DECOD_EVENT_ACK ,"out_DECOD_EVENT_ACK ",Tcontrol_t ,_param->_nb_decod_unit);
62	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_CONTEXT_ID ," in_DECOD_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_decod_unit);
63	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_DEPTH ," in_DECOD_EVENT_DEPTH ",Tdepth_t ,_param->_nb_decod_unit);
64	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_TYPE ," in_DECOD_EVENT_TYPE ",Tevent_type_t,_param->_nb_decod_unit);
65	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_IS_DELAY_SLOT ," in_DECOD_EVENT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_decod_unit);
66	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ," in_DECOD_EVENT_ADDRESS ",Taddress_t ,_param->_nb_decod_unit);
67	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ," in_DECOD_EVENT_ADDRESS_EPCR ",Taddress_t ,_param->_nb_decod_unit);
68
69	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t );
70	ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t );
71	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t );
72	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t );
73	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t);
74	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t );
75	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t );
76	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ," in_COMMIT_EVENT_ADDRESS_EPCR_VAL ",Tcontrol_t );
77	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t );
78	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t );
79	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t);
80
81	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
82	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
83	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
84	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
85	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION," in_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
86	//ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_TAKE ," in_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
87	//ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ," in_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
88	//ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ," in_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
89
90
91	ALLOC1_SC_SIGNAL( in_NB_INST_DECOD_ALL ," in_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context );
92	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_context );
93	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_context );
94
95	ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context );
96	ALLOC1_SC_SIGNAL( in_EVENT_ACK ," in_EVENT_ACK ",Tcontrol_t ,_param->_nb_context );
97	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS ,"out_EVENT_ADDRESS ",Taddress_t ,_param->_nb_context );
98	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,"out_EVENT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_context );
99	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,"out_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ,_param->_nb_context );
100	ALLOC1_SC_SIGNAL(out_EVENT_FLUSH_ONLY ,"out_EVENT_FLUSH_ONLY ",Tcontrol_t ,_param->_nb_context );
101	ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context );
102	ALLOC1_SC_SIGNAL(out_EVENT_TYPE ,"out_EVENT_TYPE ",Tevent_type_t,_param->_nb_context );
103	ALLOC1_SC_SIGNAL(out_EVENT_DEPTH ,"out_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context );
104	ALLOC1_SC_SIGNAL(out_EVENT_FLUSH_ONLY ,"out_EVENT_FLUSH_ONLY ",Tcontrol_t ,_param->_nb_context );
105
106	ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL ,"out_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_context );
107	ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK ," in_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_context );
108	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EPCR ,"out_SPR_EVENT_EPCR ",Taddress_t ,_param->_nb_context );
109	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR ,"out_SPR_EVENT_EEAR ",Taddress_t ,_param->_nb_context );
110	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,"out_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_context );
111	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,"out_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_context );
112	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,"out_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_context );
113
114	ALLOC1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,"out_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context );
115
116	ALLOC1_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_context );
117
118	ALLOC1_SC_SIGNAL( in_SPR_SR_IEE ," in_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_context );
119	ALLOC1_SC_SIGNAL( in_SPR_SR_EPH ," in_SPR_SR_EPH ",Tcontrol_t ,_param->_nb_context );
120
121	ALLOC1_SC_SIGNAL( in_INTERRUPT_ENABLE ," in_INTERRUPT_ENABLE ",Tcontrol_t ,_param->_nb_context );
122
123	/********************************************************
124	* Instanciation
125	********************************************************/
126
127	msg(_("<%s> : Instanciation of _Context_State.\n"),name.c_str());
128
129	((_Context_State->in_CLOCK)) ((in_CLOCK));
130	((_Context_State->in_NRESET)) ((in_NRESET));
131
132	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_VAL ,_param->_nb_context);
133	INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_EVENT_ACK ,_param->_nb_context);
134	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
135	if (_param->_have_port_depth)
136	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_DEPTH ,_param->_nb_context);
137	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context);
138	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
139	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context);
140	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
141	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_CAN_CONTINUE ,_param->_nb_context);
142
143	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_VAL ,_param->_nb_decod_unit);
144	INSTANCE1_SC_SIGNAL(_Context_State,out_DECOD_EVENT_ACK ,_param->_nb_decod_unit);
145	if (_param->_have_port_context_id)
146	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit);
147	if (_param->_have_port_depth)
148	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit);
149	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit);
150	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_IS_DELAY_SLOT ,_param->_nb_decod_unit);
151	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit);
152	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit);
153
154	INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_VAL );
155	INSTANCE0_SC_SIGNAL(_Context_State,out_COMMIT_EVENT_ACK );
156	if (_param->_have_port_context_id)
157	INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_CONTEXT_ID );
158	if (_param->_have_port_depth)
159	INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_DEPTH );
160	INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_TYPE );
161	INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_IS_DELAY_SLOT );
162	INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS );
163	INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR_VAL );
164	INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR );
165	INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
166	INSTANCE0_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR );
167
168	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
169	INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
170	if (_param->_have_port_context_id)
171	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
172	if (_param->_have_port_depth)
173	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
174	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
175	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
176	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
177	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
178
179	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_DECOD_ALL ,_param->_nb_context );
180	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_ALL ,_param->_nb_context );
181	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_MEM ,_param->_nb_context );
182
183	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_VAL ,_param->_nb_context );
184	INSTANCE1_SC_SIGNAL(_Context_State, in_EVENT_ACK ,_param->_nb_context );
185	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS ,_param->_nb_context );
186	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT ,_param->_nb_context );
187	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context );
188	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_IS_DS_TAKE ,_param->_nb_context );
189	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_TYPE ,_param->_nb_context );
190	if (_param->_have_port_depth)
191	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_DEPTH ,_param->_nb_context );
192	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_FLUSH_ONLY ,_param->_nb_context );
193
194	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_VAL ,_param->_nb_context );
195	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_EVENT_ACK ,_param->_nb_context );
196	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EPCR ,_param->_nb_context );
197	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EEAR ,_param->_nb_context );
198	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EEAR_WEN ,_param->_nb_context );
199	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_SR_DSX ,_param->_nb_context );
200	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context );
201
202	INSTANCE1_SC_SIGNAL(_Context_State,out_CONTEXT_DECOD_ENABLE ,_param->_nb_context );
203
204	if (_param->_have_port_depth)
205	INSTANCE1_SC_SIGNAL(_Context_State, in_DEPTH_MIN ,_param->_nb_context );
206
207	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_IEE ,_param->_nb_context );
208	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_EPH ,_param->_nb_context );
209
210	INSTANCE1_SC_SIGNAL(_Context_State, in_INTERRUPT_ENABLE ,_param->_nb_context );
211
212	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
213
214	Time * _time = new Time();
215
216	/********************************************************
217	* Simulation - Begin
218	********************************************************/
219
220	// Initialisation
221
222	const bool test1 = true;
223	const bool test2 = false;
224	const bool test3 = true;
225	const bool test4 = true;
226	const bool test5 = true;
227	const bool test6 = true;
228	const bool test7 = true;
229	const bool test8 = true;
230	const bool test9 = true;
231	const bool test10 = true;
232	const bool test11 = true;
233	const bool test12 = true;
234
235	const uint32_t seed = 0;
236	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
237
238	srand(seed);
239
240	const int32_t percent_transaction_branch_event = 75;
241	const int32_t percent_transaction_decod_event = 75;
242	const int32_t percent_transaction_commit_event = 75;
243	//const int32_t percent_transaction_branch_complete = 75;
244	const int32_t percent_transaction_event = 75;
245	const int32_t percent_transaction_spr = 75;
246
247	SC_START(0);
248	LABEL("Initialisation");
249
250	LABEL("Reset");
251	in_NRESET->write(0);
252	SC_START(5);
253	in_NRESET->write(1);
254
255	LABEL("Loop of Test");
256
257	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
258	{
259	LABEL("Iteration %d",iteration);
260	for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
261	in_DECOD_EVENT_VAL [i]->write(0);
262	in_COMMIT_EVENT_VAL ->write(0);
263	// for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
264	// in_BRANCH_COMPLETE_VAL [i]->write(0);
265	for (uint32_t i=0; i<_param->_nb_context; i++)
266	in_BRANCH_EVENT_VAL [i]->write(0);
267
268	for (uint32_t i=0; i<_param->_nb_context; i++)
269	{
270	in_BRANCH_EVENT_VAL [i]->write(0);
271	in_EVENT_ACK [i]->write(0);
272	in_SPR_EVENT_ACK [i]->write(0);
273	in_SPR_SR_IEE [i]->write(0);
274	in_SPR_SR_EPH [i]->write(0);
275	in_INTERRUPT_ENABLE [i]->write(0);
276
277	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[i]->read(), 1);
278	}
279
280	for (uint32_t i=0; i<_param->_nb_context; i++)
281	if (_param->_have_port_depth)
282	in_DEPTH_MIN [i]->write((log2(_param->_nb_inst_branch_speculated[i])==0)?0:(i%log2(_param->_nb_inst_branch_speculated[i])));
283
284	uint32_t context = rand()%_param->_nb_context;
285
286	if (test1)
287	{
288	SC_START(3);
289
290	LABEL("msync (begin)");
291	in_NB_INST_DECOD_ALL [context]->write(1);
292	in_NB_INST_COMMIT_ALL [context]->write(1);
293	in_NB_INST_COMMIT_MEM [context]->write(1);
294
295	uint32_t port = rand()%_param->_nb_decod_unit;
296
297	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
298	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
299	in_DECOD_EVENT_ADDRESS [port]->write(0x100);
300	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef);
301	if (_param->_have_port_depth)
302	in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context])));
303	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_MSYNC);
304
305	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
306
307	in_DECOD_EVENT_VAL [port]->write(1);
308
309	SC_START(0);
310	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
311	TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 0);
312
313	SC_START(1);
314
315	in_NB_INST_DECOD_ALL [context]->write(0);
316	in_NB_INST_COMMIT_ALL [context]->write(0);
317	in_NB_INST_COMMIT_MEM [context]->write(0);
318
319	LABEL("msync (send decod)");
320	SC_START(0);
321	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
322	TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 1);
323
324	SC_START(1);
325
326	in_DECOD_EVENT_VAL [port]->write(0);
327	in_NB_INST_COMMIT_ALL [context]->write(1);
328
329	LABEL("msync (wait end)");
330	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
331
332	SC_START(3);
333
334	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
335	in_NB_INST_COMMIT_ALL [context]->write(0);
336
337	SC_START(1);
338	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
339	}
340
341	if (test2)
342	{
343	SC_START(3);
344
345	LABEL("psync (begin)");
346	in_NB_INST_DECOD_ALL [context]->write(1);
347	in_NB_INST_COMMIT_ALL [context]->write(1);
348	in_NB_INST_COMMIT_MEM [context]->write(1);
349
350	uint32_t port = rand()%_param->_nb_decod_unit;
351
352	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
353	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
354	in_DECOD_EVENT_ADDRESS [port]->write(0x200);
355	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe);
356	if (_param->_have_port_depth)
357	in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context])));
358	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_PSYNC);
359
360	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
361
362	in_DECOD_EVENT_VAL [port]->write(1);
363
364	SC_START(0);
365	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
366	TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 0);
367
368	SC_START(1);
369
370	in_NB_INST_DECOD_ALL [context]->write(0);
371	in_NB_INST_COMMIT_ALL [context]->write(0);
372	in_NB_INST_COMMIT_MEM [context]->write(0);
373
374	LABEL("psync (send decod)");
375	SC_START(0);
376	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
377	TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 1);
378
379	SC_START(1);
380
381	in_DECOD_EVENT_VAL [port]->write(0);
382	in_NB_INST_COMMIT_ALL [context]->write(1);
383
384	LABEL("psync (wait end)");
385	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
386
387	SC_START(3);
388
389	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
390	in_NB_INST_COMMIT_ALL [context]->write(0);
391
392	SC_START(1);
393
394	bool find = false;
395	do
396	{
397	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
398
399	SC_START(0);
400
401	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
402	{
403	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x201);
404	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdeadbebe);
405	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
406	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
407	TEST(Tcontrol_t,out_EVENT_FLUSH_ONLY [context]->read(),0);
408
409	find = true;
410	}
411
412	SC_START(1);
413	}
414	while (not find);
415
416	in_EVENT_ACK [context]->write(0);
417	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
418	}
419
420	if (test3)
421	{
422	SC_START(3);
423
424	LABEL("csync (begin)");
425	in_NB_INST_DECOD_ALL [context]->write(1);
426	in_NB_INST_COMMIT_ALL [context]->write(1);
427	in_NB_INST_COMMIT_MEM [context]->write(1);
428
429	uint32_t port = rand()%_param->_nb_decod_unit;
430
431	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
432	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
433	in_DECOD_EVENT_ADDRESS [port]->write(0x300);
434	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdead0300);
435	if (_param->_have_port_depth)
436	in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context])));
437	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_CSYNC);
438
439	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
440
441	in_DECOD_EVENT_VAL [port]->write(1);
442
443	SC_START(0);
444	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
445	TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 0);
446
447	SC_START(1);
448
449	in_NB_INST_DECOD_ALL [context]->write(0);
450	in_NB_INST_COMMIT_ALL [context]->write(0);
451	in_NB_INST_COMMIT_MEM [context]->write(0);
452
453	LABEL("csync (send decod)");
454	SC_START(0);
455	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
456	TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 1);
457
458	SC_START(1);
459
460	in_DECOD_EVENT_VAL [port]->write(0);
461	in_NB_INST_COMMIT_ALL [context]->write(1);
462
463	LABEL("csync (wait end)");
464	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
465
466	SC_START(3);
467
468	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
469	in_NB_INST_COMMIT_ALL [context]->write(0);
470
471	SC_START(1);
472
473	bool find = false;
474	do
475	{
476	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
477
478	SC_START(0);
479
480	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
481	{
482	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x301);
483	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdead0300);
484	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
485	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
486	TEST(Tcontrol_t,out_EVENT_FLUSH_ONLY [context]->read(),0);
487
488	find = true;
489	}
490
491	SC_START(1);
492	}
493	while (not find);
494
495	in_EVENT_ACK [context]->write(0);
496	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
497
498	}
499
500	if (test4)
501	{
502	SC_START(3);
503
504	LABEL("spr_access (begin)");
505	in_NB_INST_DECOD_ALL [context]->write(1);
506	in_NB_INST_COMMIT_ALL [context]->write(1);
507	in_NB_INST_COMMIT_MEM [context]->write(1);
508
509	uint32_t port = rand()%_param->_nb_decod_unit;
510
511	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
512	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
513	in_DECOD_EVENT_ADDRESS [port]->write(0x400);
514	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdead0400);
515	if (_param->_have_port_depth)
516	in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context])));
517	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_SPR_ACCESS);
518
519	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
520
521	in_DECOD_EVENT_VAL [port]->write(1);
522
523	SC_START(0);
524	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
525	TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 0);
526
527	SC_START(1);
528
529	in_NB_INST_DECOD_ALL [context]->write(0);
530	in_NB_INST_COMMIT_ALL [context]->write(0);
531	in_NB_INST_COMMIT_MEM [context]->write(0);
532
533	LABEL("spr_access (send decod)");
534	SC_START(0);
535	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
536	TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 1);
537
538	SC_START(1);
539
540	in_DECOD_EVENT_VAL [port]->write(0);
541	in_NB_INST_COMMIT_ALL [context]->write(1);
542
543	LABEL("spr_access (wait end)");
544	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
545
546	SC_START(3);
547
548	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
549	in_NB_INST_COMMIT_ALL [context]->write(0);
550
551	SC_START(1);
552	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
553	}
554
555	if (test5)
556	{
557	SC_START(3);
558
559	LABEL("miss (begin)");
560	in_NB_INST_DECOD_ALL [context]->write(1);
561	in_NB_INST_COMMIT_ALL [context]->write(1);
562	in_NB_INST_COMMIT_MEM [context]->write(1);
563
564	// uint32_t port = rand()%_param->_nb_inst_branch_complete;
565
566	// in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context);
567	// if (_param->_have_port_depth)
568	// in_BRANCH_COMPLETE_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context])));
569	// in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400);
570	// in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500);
571	// in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1);
572	// in_BRANCH_COMPLETE_TAKE [port]->write(0);
573
574	// TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
575
576	// do
577	// {
578	// in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
579
580	// SC_START(1);
581	// }
582	// while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
583	// out_BRANCH_COMPLETE_ACK [port]->read()));
584	// in_BRANCH_COMPLETE_VAL [port]->write(0);
585
586	uint32_t port = context;
587
588	if (_param->_have_port_depth)
589	in_BRANCH_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context])));
590	in_BRANCH_EVENT_ADDRESS_SRC [port]->write(0x400);
591	in_BRANCH_EVENT_ADDRESS_DEST [port]->write(0x500);
592	in_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->write(0);
593	in_BRANCH_EVENT_CAN_CONTINUE [port]->write(0);
594
595	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
596
597	do
598	{
599	in_BRANCH_EVENT_VAL [port]->write(rand()%percent_transaction_branch_event);
600
601	SC_START(1);
602	}
603	while (not ( in_BRANCH_EVENT_VAL [port]->read() and
604	out_BRANCH_EVENT_ACK [port]->read()));
605	in_BRANCH_EVENT_VAL [port]->write(0);
606
607	LABEL("miss (wait end)");
608	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
609
610	SC_START(3);
611
612	in_NB_INST_DECOD_ALL [context]->write(0);
613	in_NB_INST_COMMIT_ALL [context]->write(0);
614	in_NB_INST_COMMIT_MEM [context]->write(0);
615
616	SC_START(1);
617
618	LABEL("miss (wait event)");
619
620
621	bool find = false;
622	do
623	{
624	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
625
626	SC_START(0);
627
628	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
629	{
630	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x401);
631	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x500);
632	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
633	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
634	TEST(Tcontrol_t,out_EVENT_FLUSH_ONLY [context]->read(),0);
635
636	find = true;
637	}
638
639	SC_START(1);
640	}
641	while (not find);
642
643	in_EVENT_ACK [context]->write(0);
644
645	}
646
647	if (test6)
648	{
649	SC_START(3);
650
651	LABEL("miss (begin)");
652	in_NB_INST_DECOD_ALL [context]->write(1);
653	in_NB_INST_COMMIT_ALL [context]->write(1);
654	in_NB_INST_COMMIT_MEM [context]->write(1);
655
656	// uint32_t port = rand()%_param->_nb_inst_branch_complete;
657
658	// in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context);
659	// if (_param->_have_port_depth)
660	// in_BRANCH_COMPLETE_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context])));
661	// in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600);
662	// in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700);
663	// in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1);
664	// in_BRANCH_COMPLETE_TAKE [port]->write(1);
665
666	// TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
667
668	// do
669	// {
670	// in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
671
672	// SC_START(1);
673	// }
674	// while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
675	// out_BRANCH_COMPLETE_ACK [port]->read()));
676	// in_BRANCH_COMPLETE_VAL [port]->write(0);
677
678	uint32_t port = context;
679
680	in_BRANCH_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context])));
681	in_BRANCH_EVENT_ADDRESS_SRC [port]->write(0x600);
682	in_BRANCH_EVENT_ADDRESS_DEST [port]->write(0x700);
683	in_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->write(1);
684	in_BRANCH_EVENT_CAN_CONTINUE [port]->write(0);
685
686	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
687
688	do
689	{
690	in_BRANCH_EVENT_VAL [port]->write(rand()%percent_transaction_branch_event);
691
692	SC_START(1);
693	}
694	while (not ( in_BRANCH_EVENT_VAL [port]->read() and
695	out_BRANCH_EVENT_ACK [port]->read()));
696	in_BRANCH_EVENT_VAL [port]->write(0);
697
698	LABEL("miss (wait end)");
699	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
700
701	SC_START(3);
702
703	in_NB_INST_DECOD_ALL [context]->write(0);
704	in_NB_INST_COMMIT_ALL [context]->write(0);
705	in_NB_INST_COMMIT_MEM [context]->write(0);
706
707	SC_START(1);
708
709	LABEL("miss (wait event)");
710
711	bool find = false;
712	do
713	{
714	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
715
716	SC_START(0);
717
718	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
719	{
720	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x601);
721	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x700);
722	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),1);
723	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),1);
724	TEST(Tcontrol_t,out_EVENT_FLUSH_ONLY [context]->read(),0);
725
726	find = true;
727	}
728
729	SC_START(1);
730	}
731	while (not find);
732
733	in_EVENT_ACK [context]->write(0);
734	}
735
736	if (test7)
737	{
738	SC_START(3);
739
740	LABEL("exception (begin)");
741	in_NB_INST_DECOD_ALL [context]->write(1);
742	in_NB_INST_COMMIT_ALL [context]->write(1);
743	in_NB_INST_COMMIT_MEM [context]->write(1);
744
745	uint32_t port = rand()%_param->_nb_decod_unit;
746
747	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
748	if (_param->_have_port_depth)
749	in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context])));
750	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
751	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
752	in_DECOD_EVENT_ADDRESS [port]->write(0x800);
753	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0x900);
754
755	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
756
757	do
758	{
759	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
760
761	SC_START(1);
762	}
763	while (not ( in_DECOD_EVENT_VAL [port]->read() and
764	out_DECOD_EVENT_ACK [port]->read()));
765	in_DECOD_EVENT_VAL [port]->write(0);
766
767	LABEL("exception (wait end)");
768	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
769
770	SC_START(3);
771
772	in_NB_INST_DECOD_ALL [context]->write(0);
773	in_NB_INST_COMMIT_ALL [context]->write(0);
774	in_NB_INST_COMMIT_MEM [context]->write(0);
775
776	SC_START(1);
777
778	LABEL("exception (wait event)");
779
780	bool find = false;
781	do
782	{
783	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
784
785	SC_START(0);
786
787	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
788	{
789	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x800);
790	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x900);
791	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
792	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
793	TEST(Tcontrol_t,out_EVENT_FLUSH_ONLY [context]->read(),0);
794
795	find = true;
796	}
797
798	SC_START(1);
799	}
800	while (not find);
801
802	in_EVENT_ACK [context]->write(0);
803
804	LABEL("exception (wait spr)");
805
806	find = false;
807	do
808	{
809	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
810
811	SC_START(0);
812
813	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
814	{
815	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0x900);
816	//TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),);
817	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
818	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
819	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
820
821	find = true;
822	}
823
824	SC_START(1);
825	}
826	while (not find);
827
828	in_SPR_EVENT_ACK [context]->write(0);
829	}
830
831	if (test8)
832	{
833	SC_START(3);
834
835	LABEL("exception (begin)");
836	in_NB_INST_DECOD_ALL [context]->write(1);
837	in_NB_INST_COMMIT_ALL [context]->write(1);
838	in_NB_INST_COMMIT_MEM [context]->write(1);
839
840	uint32_t port = rand()%_param->_nb_decod_unit;
841
842	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
843	if (_param->_have_port_depth)
844	in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context])));
845	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
846	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(1);
847	in_DECOD_EVENT_ADDRESS [port]->write(0x800);
848	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0x900);
849
850	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
851
852	do
853	{
854	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
855
856	SC_START(1);
857	}
858	while (not ( in_DECOD_EVENT_VAL [port]->read() and
859	out_DECOD_EVENT_ACK [port]->read()));
860	in_DECOD_EVENT_VAL [port]->write(0);
861
862	LABEL("exception (wait end)");
863	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
864
865	SC_START(3);
866
867	in_NB_INST_DECOD_ALL [context]->write(0);
868	in_NB_INST_COMMIT_ALL [context]->write(0);
869	in_NB_INST_COMMIT_MEM [context]->write(0);
870
871	SC_START(1);
872
873	LABEL("exception (wait event)");
874
875	bool find = false;
876	do
877	{
878	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
879
880	SC_START(0);
881
882	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
883	{
884	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x800);
885	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x900);
886	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
887	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
888	TEST(Tcontrol_t,out_EVENT_FLUSH_ONLY [context]->read(),0);
889
890	find = true;
891	}
892
893	SC_START(1);
894	}
895	while (not find);
896
897	in_EVENT_ACK [context]->write(0);
898
899	LABEL("exception (wait spr)");
900
901	find = false;
902	do
903	{
904	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
905
906	SC_START(0);
907
908	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
909	{
910	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0x900);
911	//TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),);
912	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
913	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
914	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
915
916	find = true;
917	}
918
919	SC_START(1);
920	}
921	while (not find);
922
923	in_SPR_EVENT_ACK [context]->write(0);
924	}
925
926	if (test9)
927	{
928	SC_START(3);
929
930	LABEL("exception (begin)");
931	in_NB_INST_DECOD_ALL [context]->write(1);
932	in_NB_INST_COMMIT_ALL [context]->write(1);
933	in_NB_INST_COMMIT_MEM [context]->write(1);
934
935	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
936	if (_param->_have_port_depth)
937	in_COMMIT_EVENT_DEPTH ->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context])));
938	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
939	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0);
940	in_COMMIT_EVENT_ADDRESS ->write(0xa00);
941	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00);
942	in_COMMIT_EVENT_ADDRESS_EPCR_VAL ->write(0);
943	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00);
944	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0);
945
946	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
947
948	do
949	{
950	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
951
952	SC_START(1);
953	}
954	while (not ( in_COMMIT_EVENT_VAL ->read() and
955	out_COMMIT_EVENT_ACK ->read()));
956	in_COMMIT_EVENT_VAL ->write(0);
957
958	LABEL("exception (wait end)");
959	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
960
961	SC_START(3);
962
963	in_NB_INST_DECOD_ALL [context]->write(0);
964	in_NB_INST_COMMIT_ALL [context]->write(0);
965	in_NB_INST_COMMIT_MEM [context]->write(0);
966
967	SC_START(1);
968
969	LABEL("exception (wait event)");
970
971	bool find = false;
972	do
973	{
974	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
975
976	SC_START(0);
977
978	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
979	{
980	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xa00);
981	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xb00);
982	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
983	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
984	TEST(Tcontrol_t,out_EVENT_FLUSH_ONLY [context]->read(),0);
985
986	find = true;
987	}
988
989	SC_START(1);
990	}
991	while (not find);
992
993	in_EVENT_ACK [context]->write(0);
994
995	LABEL("exception (wait spr)");
996
997	find = false;
998	do
999	{
1000	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1001
1002	SC_START(0);
1003
1004	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1005	{
1006	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xb00);
1007	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xc00);
1008	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
1009	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
1010	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1011
1012	find = true;
1013	}
1014
1015	SC_START(1);
1016	}
1017	while (not find);
1018
1019	in_SPR_EVENT_ACK [context]->write(0);
1020	}
1021
1022	if (test10)
1023	{
1024	SC_START(3);
1025
1026	LABEL("exception (begin)");
1027	in_NB_INST_DECOD_ALL [context]->write(1);
1028	in_NB_INST_COMMIT_ALL [context]->write(1);
1029	in_NB_INST_COMMIT_MEM [context]->write(1);
1030
1031	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
1032	if (_param->_have_port_depth)
1033	in_COMMIT_EVENT_DEPTH ->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context])));
1034	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
1035	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1);
1036	in_COMMIT_EVENT_ADDRESS ->write(0xd00);
1037	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00);
1038	in_COMMIT_EVENT_ADDRESS_EPCR_VAL ->write(0);
1039	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00);
1040	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0);
1041
1042	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1043
1044	do
1045	{
1046	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
1047
1048	SC_START(1);
1049	}
1050	while (not ( in_COMMIT_EVENT_VAL ->read() and
1051	out_COMMIT_EVENT_ACK ->read()));
1052	in_COMMIT_EVENT_VAL ->write(0);
1053
1054	LABEL("exception (wait end)");
1055	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1056
1057	SC_START(3);
1058
1059	in_NB_INST_DECOD_ALL [context]->write(0);
1060	in_NB_INST_COMMIT_ALL [context]->write(0);
1061	in_NB_INST_COMMIT_MEM [context]->write(0);
1062
1063	SC_START(1);
1064
1065	LABEL("exception (wait event)");
1066
1067	bool find = false;
1068	do
1069	{
1070	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1071
1072	SC_START(0);
1073
1074	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1075	{
1076	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xd00);
1077	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xe00);
1078	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1079	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1080	TEST(Tcontrol_t,out_EVENT_FLUSH_ONLY [context]->read(),0);
1081
1082	find = true;
1083	}
1084
1085	SC_START(1);
1086	}
1087	while (not find);
1088
1089	in_EVENT_ACK [context]->write(0);
1090
1091	LABEL("exception (wait spr)");
1092
1093	find = false;
1094	do
1095	{
1096	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1097
1098	SC_START(0);
1099
1100	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1101	{
1102	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xe00);
1103	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xf00);
1104	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
1105	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
1106	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1107
1108	find = true;
1109	}
1110
1111	SC_START(1);
1112	}
1113	while (not find);
1114
1115	in_SPR_EVENT_ACK [context]->write(0);
1116	}
1117
1118	if (test11)
1119	{
1120	SC_START(3);
1121
1122	LABEL("exception (begin)");
1123	in_NB_INST_DECOD_ALL [context]->write(1);
1124	in_NB_INST_COMMIT_ALL [context]->write(1);
1125	in_NB_INST_COMMIT_MEM [context]->write(1);
1126
1127	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
1128	if (_param->_have_port_depth)
1129	in_COMMIT_EVENT_DEPTH ->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context])));
1130	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
1131	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0);
1132	in_COMMIT_EVENT_ADDRESS ->write(0xa00);
1133	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00);
1134	in_COMMIT_EVENT_ADDRESS_EPCR_VAL ->write(1);
1135	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00);
1136	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1);
1137
1138	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1139
1140	do
1141	{
1142	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
1143
1144	SC_START(1);
1145	}
1146	while (not ( in_COMMIT_EVENT_VAL ->read() and
1147	out_COMMIT_EVENT_ACK ->read()));
1148	in_COMMIT_EVENT_VAL ->write(0);
1149
1150	LABEL("exception (wait end)");
1151	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1152
1153	SC_START(3);
1154
1155	in_NB_INST_DECOD_ALL [context]->write(0);
1156	in_NB_INST_COMMIT_ALL [context]->write(0);
1157	in_NB_INST_COMMIT_MEM [context]->write(0);
1158
1159	SC_START(1);
1160
1161	LABEL("exception (wait event)");
1162
1163	bool find = false;
1164	do
1165	{
1166	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1167
1168	SC_START(0);
1169
1170	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1171	{
1172	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xa00);
1173	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xb00);
1174	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1175	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1176	TEST(Tcontrol_t,out_EVENT_FLUSH_ONLY [context]->read(),0);
1177
1178	find = true;
1179	}
1180
1181	SC_START(1);
1182	}
1183	while (not find);
1184
1185	in_EVENT_ACK [context]->write(0);
1186
1187	LABEL("exception (wait spr)");
1188
1189	find = false;
1190	do
1191	{
1192	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1193
1194	SC_START(0);
1195
1196	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1197	{
1198	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xb00);
1199	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xc00);
1200	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),1);
1201	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
1202	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1203
1204	find = true;
1205	}
1206
1207	SC_START(1);
1208	}
1209	while (not find);
1210
1211	in_SPR_EVENT_ACK [context]->write(0);
1212	}
1213
1214	if (test12)
1215	{
1216	SC_START(3);
1217
1218	LABEL("exception (begin)");
1219	in_NB_INST_DECOD_ALL [context]->write(1);
1220	in_NB_INST_COMMIT_ALL [context]->write(1);
1221	in_NB_INST_COMMIT_MEM [context]->write(1);
1222
1223	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
1224	if (_param->_have_port_depth)
1225	in_COMMIT_EVENT_DEPTH ->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context])));
1226	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
1227	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1);
1228	in_COMMIT_EVENT_ADDRESS ->write(0xd00);
1229	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00);
1230	in_COMMIT_EVENT_ADDRESS_EPCR_VAL ->write(1);
1231	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00);
1232	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1);
1233
1234	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1235
1236	do
1237	{
1238	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
1239
1240	SC_START(1);
1241	}
1242	while (not ( in_COMMIT_EVENT_VAL ->read() and
1243	out_COMMIT_EVENT_ACK ->read()));
1244	in_COMMIT_EVENT_VAL ->write(0);
1245
1246	LABEL("exception (wait end)");
1247	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1248
1249	SC_START(3);
1250
1251	in_NB_INST_DECOD_ALL [context]->write(0);
1252	in_NB_INST_COMMIT_ALL [context]->write(0);
1253	in_NB_INST_COMMIT_MEM [context]->write(0);
1254
1255	SC_START(1);
1256
1257	LABEL("exception (wait event)");
1258
1259	bool find = false;
1260	do
1261	{
1262	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1263
1264	SC_START(0);
1265
1266	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1267	{
1268	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xd00);
1269	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xe00);
1270	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1271	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1272	TEST(Tcontrol_t,out_EVENT_FLUSH_ONLY [context]->read(),0);
1273
1274	find = true;
1275	}
1276
1277	SC_START(1);
1278	}
1279	while (not find);
1280
1281	in_EVENT_ACK [context]->write(0);
1282
1283	LABEL("exception (wait spr)");
1284
1285	find = false;
1286	do
1287	{
1288	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1289
1290	SC_START(0);
1291
1292	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1293	{
1294	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xe00);
1295	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xf00);
1296	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),1);
1297	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
1298	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1299
1300	find = true;
1301	}
1302
1303	SC_START(1);
1304	}
1305	while (not find);
1306
1307	in_SPR_EVENT_ACK [context]->write(0);
1308	}
1309
1310
1311	SC_START(1);
1312	}
1313
1314
1315	/********************************************************
1316	* Simulation - End
1317	********************************************************/
1318
1319	TEST_OK ("End of Simulation");
1320	delete _time;
1321
1322	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
1323
1324	delete in_CLOCK;
1325	delete in_NRESET;
1326
1327	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_VAL ,_param->_nb_context);
1328	DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,_param->_nb_context);
1329	//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
1330	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context);
1331	//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context);
1332	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
1333	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context);
1334	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
1335	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_CAN_CONTINUE ,_param->_nb_context);
1336
1337	DELETE1_SC_SIGNAL( in_DECOD_EVENT_VAL ,_param->_nb_decod_unit);
1338	DELETE1_SC_SIGNAL(out_DECOD_EVENT_ACK ,_param->_nb_decod_unit);
1339	DELETE1_SC_SIGNAL( in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit);
1340	DELETE1_SC_SIGNAL( in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit);
1341	DELETE1_SC_SIGNAL( in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit);
1342	DELETE1_SC_SIGNAL( in_DECOD_EVENT_IS_DELAY_SLOT ,_param->_nb_decod_unit);
1343	DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit);
1344	DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit);
1345	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_VAL );
1346	DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ACK );
1347	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID );
1348	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_DEPTH );
1349	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_TYPE );
1350	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT );
1351	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS );
1352	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR_VAL );
1353	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR );
1354	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
1355	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR );
1356	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
1357	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
1358	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
1359	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
1360	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
1361	//DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
1362	//DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
1363	//DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
1364	DELETE1_SC_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_context );
1365	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context );
1366	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context );
1367	DELETE1_SC_SIGNAL(out_EVENT_VAL ,_param->_nb_context );
1368	DELETE1_SC_SIGNAL( in_EVENT_ACK ,_param->_nb_context );
1369	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context );
1370	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context );
1371	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context );
1372	DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context );
1373	DELETE1_SC_SIGNAL(out_EVENT_TYPE ,_param->_nb_context );
1374	DELETE1_SC_SIGNAL(out_EVENT_DEPTH ,_param->_nb_context );
1375	DELETE1_SC_SIGNAL(out_EVENT_FLUSH_ONLY ,_param->_nb_context );
1376	DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context );
1377	DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context );
1378	DELETE1_SC_SIGNAL(out_SPR_EVENT_EPCR ,_param->_nb_context );
1379	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR ,_param->_nb_context );
1380	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,_param->_nb_context );
1381	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,_param->_nb_context );
1382	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context );
1383	DELETE1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,_param->_nb_context );
1384	DELETE1_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_context );
1385	DELETE1_SC_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context );
1386	DELETE1_SC_SIGNAL( in_SPR_SR_EPH ,_param->_nb_context );
1387
1388	DELETE1_SC_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_context );
1389	}
1390	#endif
1391
1392	delete _Context_State;
1393	#ifdef STATISTICS
1394	delete _parameters_statistics;
1395	#endif
1396	}

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp @ 119

Download in other formats: