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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp @ 97

Last change on this file since 97 was 97, checked in by rosiere, 15 years ago
1) Update Prediction Table : statistics 2) Size instruction address on 30 bits 3) Change Log File 4) Add debug_level in simulation configuration file
Property svn:keywords set to `Id`
File size: 49.3 KB

Line
1	/*
2	* $Id: test.cpp 97 2008-12-19 15:34:00Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/include/test.h"
10	#include "Behavioural/include/Allocation.h"
11
12	void test (string name,
13	morpheo::behavioural::core::multi_front_end::front_end::context_state::Parameters * _param)
14	{
15	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
16
17	#ifdef STATISTICS
18	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
19	#endif
20
21	Tusage_t _usage = USE_ALL;
22
23	// _usage = usage_unset(_usage,USE_SYSTEMC );
24	// _usage = usage_unset(_usage,USE_VHDL );
25	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
26	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
27	// _usage = usage_unset(_usage,USE_POSITION );
28	// _usage = usage_unset(_usage,USE_STATISTICS );
29	// _usage = usage_unset(_usage,USE_INFORMATION );
30
31	Context_State * _Context_State = new Context_State
32	(name.c_str(),
33	#ifdef STATISTICS
34	_parameters_statistics,
35	#endif
36	_param,
37	_usage);
38
39	#ifdef SYSTEMC
40	if (usage_is_set(_usage,USE_SYSTEMC))
41	{
42	/*********************************************************************
43	* Déclarations des signaux
44	*********************************************************************/
45	string rename;
46
47	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
48	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
49
50	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_VAL ," in_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
51	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,"out_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
52	//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ," in_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
53	//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
54	//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ," in_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context);
55	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ," in_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
56	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST_VAL ," in_BRANCH_EVENT_ADDRESS_DEST_VAL ",Tcontrol_t ,_param->_nb_context);
57	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ," in_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
58
59	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_VAL ," in_DECOD_EVENT_VAL ",Tcontrol_t ,_param->_nb_decod_unit);
60	ALLOC1_SC_SIGNAL(out_DECOD_EVENT_ACK ,"out_DECOD_EVENT_ACK ",Tcontrol_t ,_param->_nb_decod_unit);
61	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_CONTEXT_ID ," in_DECOD_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_decod_unit);
62	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_DEPTH ," in_DECOD_EVENT_DEPTH ",Tdepth_t ,_param->_nb_decod_unit);
63	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_TYPE ," in_DECOD_EVENT_TYPE ",Tevent_type_t,_param->_nb_decod_unit);
64	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_IS_DELAY_SLOT ," in_DECOD_EVENT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_decod_unit);
65	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ," in_DECOD_EVENT_ADDRESS ",Taddress_t ,_param->_nb_decod_unit);
66	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ," in_DECOD_EVENT_ADDRESS_EPCR ",Taddress_t ,_param->_nb_decod_unit);
67
68	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t );
69	ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t );
70	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t );
71	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t );
72	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t);
73	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t );
74	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t );
75	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t );
76	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t );
77	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t);
78
79	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
80	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
81	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
82	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
83	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION," in_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
84	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_TAKE ," in_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
85	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ," in_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
86	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ," in_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
87
88
89	ALLOC1_SC_SIGNAL( in_NB_INST_DECOD_ALL ," in_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context );
90	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_context );
91	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_context );
92
93	ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context );
94	ALLOC1_SC_SIGNAL( in_EVENT_ACK ," in_EVENT_ACK ",Tcontrol_t ,_param->_nb_context );
95	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS ,"out_EVENT_ADDRESS ",Taddress_t ,_param->_nb_context );
96	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,"out_EVENT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_context );
97	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,"out_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ,_param->_nb_context );
98	ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context );
99	ALLOC1_SC_SIGNAL(out_EVENT_TYPE ,"out_EVENT_TYPE ",Tevent_type_t,_param->_nb_context );
100	ALLOC1_SC_SIGNAL(out_EVENT_DEPTH ,"out_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context );
101
102	ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL ,"out_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_context );
103	ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK ," in_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_context );
104	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EPCR ,"out_SPR_EVENT_EPCR ",Taddress_t ,_param->_nb_context );
105	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR ,"out_SPR_EVENT_EEAR ",Taddress_t ,_param->_nb_context );
106	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,"out_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_context );
107	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,"out_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_context );
108	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,"out_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_context );
109
110	ALLOC1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,"out_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context );
111
112	ALLOC1_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_context );
113
114	ALLOC1_SC_SIGNAL( in_SPR_SR_IEE ," in_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_context );
115	ALLOC1_SC_SIGNAL( in_SPR_SR_EPH ," in_SPR_SR_EPH ",Tcontrol_t ,_param->_nb_context );
116
117	ALLOC1_SC_SIGNAL( in_INTERRUPT_ENABLE ," in_INTERRUPT_ENABLE ",Tcontrol_t ,_param->_nb_context );
118
119	/********************************************************
120	* Instanciation
121	********************************************************/
122
123	msg(_("<%s> : Instanciation of _Context_State.\n"),name.c_str());
124
125	((_Context_State->in_CLOCK)) ((in_CLOCK));
126	((_Context_State->in_NRESET)) ((in_NRESET));
127
128	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_VAL ,_param->_nb_context);
129	INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_EVENT_ACK ,_param->_nb_context);
130	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
131	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_DEPTH ,_param->_nb_context);
132	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context);
133	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
134	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context);
135	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
136	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_VAL ,_param->_nb_decod_unit);
137	INSTANCE1_SC_SIGNAL(_Context_State,out_DECOD_EVENT_ACK ,_param->_nb_decod_unit);
138	if (_param->_have_port_context_id)
139	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit);
140	if (_param->_have_port_depth)
141	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit);
142	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit);
143	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_IS_DELAY_SLOT ,_param->_nb_decod_unit);
144	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit);
145	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit);
146
147	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_VAL );
148	INSTANCE_SC_SIGNAL (_Context_State,out_COMMIT_EVENT_ACK );
149	if (_param->_have_port_context_id)
150	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_CONTEXT_ID );
151	if (_param->_have_port_depth)
152	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_DEPTH );
153	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_TYPE );
154	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_IS_DELAY_SLOT );
155	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS );
156	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR );
157	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
158	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR );
159
160	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
161	INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
162	if (_param->_have_port_context_id)
163	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
164	if (_param->_have_port_depth)
165	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
166	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
167	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
168	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
169	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
170
171	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_DECOD_ALL ,_param->_nb_context );
172	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_ALL ,_param->_nb_context );
173	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_MEM ,_param->_nb_context );
174
175	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_VAL ,_param->_nb_context );
176	INSTANCE1_SC_SIGNAL(_Context_State, in_EVENT_ACK ,_param->_nb_context );
177	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS ,_param->_nb_context );
178	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT ,_param->_nb_context );
179	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context );
180	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_IS_DS_TAKE ,_param->_nb_context );
181	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_TYPE ,_param->_nb_context );
182	if (_param->_have_port_depth)
183	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_DEPTH ,_param->_nb_context );
184
185	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_VAL ,_param->_nb_context );
186	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_EVENT_ACK ,_param->_nb_context );
187	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EPCR ,_param->_nb_context );
188	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EEAR ,_param->_nb_context );
189	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EEAR_WEN ,_param->_nb_context );
190	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_SR_DSX ,_param->_nb_context );
191	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context );
192
193	INSTANCE1_SC_SIGNAL(_Context_State,out_CONTEXT_DECOD_ENABLE ,_param->_nb_context );
194
195	for (uint32_t i=0; i<_param->_nb_context; i++)
196	if (_param->_have_port_depth)
197	INSTANCE_SC_SIGNAL(_Context_State, in_DEPTH_MIN [i]);
198
199	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_IEE ,_param->_nb_context );
200	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_EPH ,_param->_nb_context );
201
202	INSTANCE1_SC_SIGNAL(_Context_State, in_INTERRUPT_ENABLE ,_param->_nb_context );
203
204	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
205
206	Time * _time = new Time();
207
208	/********************************************************
209	* Simulation - Begin
210	********************************************************/
211
212	// Initialisation
213
214	const uint32_t seed = 0;
215	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
216
217	srand(seed);
218
219	const int32_t percent_transaction_decod_event = 75;
220	const int32_t percent_transaction_commit_event = 75;
221	const int32_t percent_transaction_branch_complete = 75;
222	const int32_t percent_transaction_event = 75;
223	const int32_t percent_transaction_spr = 75;
224
225	SC_START(0);
226	LABEL("Initialisation");
227
228	LABEL("Reset");
229	in_NRESET->write(0);
230	SC_START(5);
231	in_NRESET->write(1);
232
233	LABEL("Loop of Test");
234
235	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
236	{
237	LABEL("Iteration %d",iteration);
238	for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
239	in_DECOD_EVENT_VAL [i]->write(0);
240	in_COMMIT_EVENT_VAL ->write(0);
241	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
242	in_BRANCH_COMPLETE_VAL [i]->write(0);
243
244	for (uint32_t i=0; i<_param->_nb_context; i++)
245	{
246	in_BRANCH_EVENT_VAL [i]->write(0);
247	in_EVENT_ACK [i]->write(0);
248	in_SPR_EVENT_ACK [i]->write(0);
249	in_SPR_SR_IEE [i]->write(0);
250	in_SPR_SR_EPH [i]->write(0);
251	in_INTERRUPT_ENABLE [i]->write(0);
252
253	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[i]->read(), 1);
254	}
255
256	for (uint32_t i=0; i<_param->_nb_context; i++)
257	if (_param->_have_port_depth)
258	in_DEPTH_MIN [i]->write((_param->_array_size_depth[i]==0)?0:(i%_param->_array_size_depth[i]));
259
260	uint32_t context = rand()%_param->_nb_context;
261
262	if (1)
263	{
264	SC_START(3);
265
266	LABEL("msync (begin)");
267	in_NB_INST_DECOD_ALL [context]->write(1);
268	in_NB_INST_COMMIT_ALL [context]->write(1);
269	in_NB_INST_COMMIT_MEM [context]->write(1);
270
271	uint32_t port = rand()%_param->_nb_decod_unit;
272
273	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
274	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
275	in_DECOD_EVENT_ADDRESS [port]->write(0x100);
276	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef);
277	if (_param->_have_port_depth)
278	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
279	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_MSYNC);
280
281	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
282
283	do
284	{
285	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
286
287	SC_START(1);
288	}
289	while (not ( in_DECOD_EVENT_VAL [port]->read() and
290	out_DECOD_EVENT_ACK [port]->read()));
291	in_DECOD_EVENT_VAL [port]->write(0);
292
293	LABEL("msync (wait end)");
294	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
295
296	SC_START(3);
297
298	in_NB_INST_DECOD_ALL [context]->write(0);
299	in_NB_INST_COMMIT_ALL [context]->write(1);
300	in_NB_INST_COMMIT_MEM [context]->write(0);
301
302	SC_START(1);
303
304	LABEL("msync (send decod)");
305	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
306
307	SC_START(3);
308
309	in_NB_INST_DECOD_ALL [context]->write(1);
310	SC_START(1);
311
312	LABEL("msync (wait end)");
313	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
314	in_NB_INST_DECOD_ALL [context]->write(0);
315	in_NB_INST_COMMIT_MEM [context]->write(1);
316
317	SC_START(3);
318
319	in_NB_INST_COMMIT_MEM [context]->write(0);
320	SC_START(1);
321	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
322	}
323
324	if (1)
325	{
326	SC_START(3);
327
328	LABEL("psync (begin)");
329	in_NB_INST_DECOD_ALL [context]->write(1);
330	in_NB_INST_COMMIT_ALL [context]->write(1);
331	in_NB_INST_COMMIT_MEM [context]->write(1);
332
333	uint32_t port = rand()%_param->_nb_decod_unit;
334
335	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
336	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
337	in_DECOD_EVENT_ADDRESS [port]->write(0x200);
338	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe);
339	if (_param->_have_port_depth)
340	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
341	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_PSYNC);
342
343	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
344
345	do
346	{
347	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
348
349	SC_START(1);
350	}
351	while (not ( in_DECOD_EVENT_VAL [port]->read() and
352	out_DECOD_EVENT_ACK [port]->read()));
353	in_DECOD_EVENT_VAL [port]->write(0);
354
355	LABEL("psync (wait end)");
356	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
357
358	SC_START(3);
359
360	in_NB_INST_DECOD_ALL [context]->write(0);
361	in_NB_INST_COMMIT_ALL [context]->write(0);
362	in_NB_INST_COMMIT_MEM [context]->write(0);
363
364	SC_START(1);
365
366	bool find = false;
367	do
368	{
369	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
370
371	SC_START(0);
372
373	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
374	{
375	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x201);
376	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdeadbebe);
377	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
378	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
379
380	find = true;
381	}
382
383	SC_START(1);
384	}
385	while (not find);
386
387	in_EVENT_ACK [context]->write(0);
388	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
389	}
390
391	if (1)
392	{
393	SC_START(3);
394
395	LABEL("csync (begin)");
396	in_NB_INST_DECOD_ALL [context]->write(1);
397	in_NB_INST_COMMIT_ALL [context]->write(1);
398	in_NB_INST_COMMIT_MEM [context]->write(1);
399
400	uint32_t port = rand()%_param->_nb_decod_unit;
401
402	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
403	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
404	in_DECOD_EVENT_ADDRESS [port]->write(0x200);
405	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe);
406	if (_param->_have_port_depth)
407	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
408	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_CSYNC);
409
410	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
411
412	do
413	{
414	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
415
416	SC_START(1);
417	}
418	while (not ( in_DECOD_EVENT_VAL [port]->read() and
419	out_DECOD_EVENT_ACK [port]->read()));
420	in_DECOD_EVENT_VAL [port]->write(0);
421
422	LABEL("csync (wait end)");
423	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
424
425	SC_START(3);
426
427	in_NB_INST_DECOD_ALL [context]->write(0);
428	in_NB_INST_COMMIT_ALL [context]->write(0);
429	in_NB_INST_COMMIT_MEM [context]->write(0);
430
431	SC_START(1);
432
433	bool find = false;
434	do
435	{
436	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
437
438	SC_START(0);
439
440	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
441	{
442	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x201);
443	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdeadbebe);
444	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
445	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
446
447	find = true;
448	}
449
450	SC_START(1);
451	}
452	while (not find);
453	in_EVENT_ACK [context]->write(0);
454	}
455
456	if (1)
457	{
458	SC_START(3);
459
460	LABEL("spr (begin)");
461	in_NB_INST_DECOD_ALL [context]->write(1);
462	in_NB_INST_COMMIT_ALL [context]->write(1);
463	in_NB_INST_COMMIT_MEM [context]->write(1);
464
465	uint32_t port = rand()%_param->_nb_decod_unit;
466
467	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
468	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
469	in_DECOD_EVENT_ADDRESS [port]->write(0x100);
470	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef);
471	if (_param->_have_port_depth)
472	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
473	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_SPR_ACCESS);
474
475	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
476
477	do
478	{
479	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
480
481	SC_START(1);
482	}
483	while (not ( in_DECOD_EVENT_VAL [port]->read() and
484	out_DECOD_EVENT_ACK [port]->read()));
485	in_DECOD_EVENT_VAL [port]->write(0);
486
487	LABEL("spr (wait end)");
488	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
489
490	SC_START(3);
491
492	in_NB_INST_DECOD_ALL [context]->write(0);
493	in_NB_INST_COMMIT_ALL [context]->write(0);
494	in_NB_INST_COMMIT_MEM [context]->write(0);
495
496	SC_START(1);
497
498	LABEL("spr (send decod)");
499	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
500
501	SC_START(3);
502
503	in_NB_INST_DECOD_ALL [context]->write(1);
504	SC_START(1);
505
506	LABEL("spr (wait end)");
507	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
508	in_NB_INST_DECOD_ALL [context]->write(0);
509	in_NB_INST_COMMIT_ALL [context]->write(1);
510
511	SC_START(3);
512
513	in_NB_INST_COMMIT_ALL [context]->write(0);
514	SC_START(1);
515	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
516	}
517
518	if (1)
519	{
520	SC_START(3);
521
522	LABEL("miss (begin)");
523	in_NB_INST_DECOD_ALL [context]->write(1);
524	in_NB_INST_COMMIT_ALL [context]->write(1);
525	in_NB_INST_COMMIT_MEM [context]->write(1);
526
527	uint32_t port = rand()%_param->_nb_inst_branch_complete;
528
529	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context);
530	if (_param->_have_port_depth)
531	in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
532	in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400);
533	in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500);
534	in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1);
535	in_BRANCH_COMPLETE_TAKE [port]->write(0);
536
537	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
538
539	do
540	{
541	in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
542
543	SC_START(1);
544	}
545	while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
546	out_BRANCH_COMPLETE_ACK [port]->read()));
547	in_BRANCH_COMPLETE_VAL [port]->write(0);
548
549	LABEL("miss (wait end)");
550	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
551
552	SC_START(3);
553
554	in_NB_INST_DECOD_ALL [context]->write(0);
555	in_NB_INST_COMMIT_ALL [context]->write(0);
556	in_NB_INST_COMMIT_MEM [context]->write(0);
557
558	SC_START(1);
559
560	LABEL("miss (wait event)");
561
562
563	bool find = false;
564	do
565	{
566	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
567
568	SC_START(0);
569
570	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
571	{
572	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x401);
573	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x500);
574	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
575	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
576
577	find = true;
578	}
579
580	SC_START(1);
581	}
582	while (not find);
583
584	in_EVENT_ACK [context]->write(0);
585
586	}
587
588	if (1)
589	{
590	SC_START(3);
591
592	LABEL("miss (begin)");
593	in_NB_INST_DECOD_ALL [context]->write(1);
594	in_NB_INST_COMMIT_ALL [context]->write(1);
595	in_NB_INST_COMMIT_MEM [context]->write(1);
596
597	uint32_t port = rand()%_param->_nb_inst_branch_complete;
598
599	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context);
600	if (_param->_have_port_depth)
601	in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
602	in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600);
603	in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700);
604	in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1);
605	in_BRANCH_COMPLETE_TAKE [port]->write(1);
606
607	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
608
609	do
610	{
611	in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
612
613	SC_START(1);
614	}
615	while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
616	out_BRANCH_COMPLETE_ACK [port]->read()));
617	in_BRANCH_COMPLETE_VAL [port]->write(0);
618
619	LABEL("miss (wait end)");
620	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
621
622	SC_START(3);
623
624	in_NB_INST_DECOD_ALL [context]->write(0);
625	in_NB_INST_COMMIT_ALL [context]->write(0);
626	in_NB_INST_COMMIT_MEM [context]->write(0);
627
628	SC_START(1);
629
630	LABEL("miss (wait event)");
631
632	bool find = false;
633	do
634	{
635	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
636
637	SC_START(0);
638
639	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
640	{
641	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x601);
642	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x700);
643	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),1);
644	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),1);
645
646	find = true;
647	}
648
649	SC_START(1);
650	}
651	while (not find);
652
653	in_EVENT_ACK [context]->write(0);
654	}
655
656	if (1)
657	{
658	SC_START(3);
659
660	LABEL("exception (begin)");
661	in_NB_INST_DECOD_ALL [context]->write(1);
662	in_NB_INST_COMMIT_ALL [context]->write(1);
663	in_NB_INST_COMMIT_MEM [context]->write(1);
664
665	uint32_t port = rand()%_param->_nb_decod_unit;
666
667	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
668	if (_param->_have_port_depth)
669	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
670	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
671	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
672	in_DECOD_EVENT_ADDRESS [port]->write(0x800);
673	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0x900);
674
675	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
676
677	do
678	{
679	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
680
681	SC_START(1);
682	}
683	while (not ( in_DECOD_EVENT_VAL [port]->read() and
684	out_DECOD_EVENT_ACK [port]->read()));
685	in_DECOD_EVENT_VAL [port]->write(0);
686
687	LABEL("exception (wait end)");
688	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
689
690	SC_START(3);
691
692	in_NB_INST_DECOD_ALL [context]->write(0);
693	in_NB_INST_COMMIT_ALL [context]->write(0);
694	in_NB_INST_COMMIT_MEM [context]->write(0);
695
696	SC_START(1);
697
698	LABEL("exception (wait event)");
699
700	bool find = false;
701	do
702	{
703	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
704
705	SC_START(0);
706
707	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
708	{
709	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x800);
710	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x900);
711	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
712	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
713
714	find = true;
715	}
716
717	SC_START(1);
718	}
719	while (not find);
720
721	in_EVENT_ACK [context]->write(0);
722
723	LABEL("exception (wait spr)");
724
725	find = false;
726	do
727	{
728	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
729
730	SC_START(0);
731
732	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
733	{
734	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0x900);
735	//TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),);
736	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
737	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
738	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
739
740	find = true;
741	}
742
743	SC_START(1);
744	}
745	while (not find);
746
747	in_SPR_EVENT_ACK [context]->write(0);
748	}
749
750	if (1)
751	{
752	SC_START(3);
753
754	LABEL("exception (begin)");
755	in_NB_INST_DECOD_ALL [context]->write(1);
756	in_NB_INST_COMMIT_ALL [context]->write(1);
757	in_NB_INST_COMMIT_MEM [context]->write(1);
758
759	uint32_t port = rand()%_param->_nb_decod_unit;
760
761	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
762	if (_param->_have_port_depth)
763	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
764	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
765	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(1);
766	in_DECOD_EVENT_ADDRESS [port]->write(0x800);
767	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0x900);
768
769	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
770
771	do
772	{
773	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
774
775	SC_START(1);
776	}
777	while (not ( in_DECOD_EVENT_VAL [port]->read() and
778	out_DECOD_EVENT_ACK [port]->read()));
779	in_DECOD_EVENT_VAL [port]->write(0);
780
781	LABEL("exception (wait end)");
782	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
783
784	SC_START(3);
785
786	in_NB_INST_DECOD_ALL [context]->write(0);
787	in_NB_INST_COMMIT_ALL [context]->write(0);
788	in_NB_INST_COMMIT_MEM [context]->write(0);
789
790	SC_START(1);
791
792	LABEL("exception (wait event)");
793
794	bool find = false;
795	do
796	{
797	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
798
799	SC_START(0);
800
801	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
802	{
803	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x800);
804	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x900);
805	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
806	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
807
808	find = true;
809	}
810
811	SC_START(1);
812	}
813	while (not find);
814
815	in_EVENT_ACK [context]->write(0);
816
817	LABEL("exception (wait spr)");
818
819	find = false;
820	do
821	{
822	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
823
824	SC_START(0);
825
826	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
827	{
828	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0x900);
829	//TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),);
830	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
831	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
832	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
833
834	find = true;
835	}
836
837	SC_START(1);
838	}
839	while (not find);
840
841	in_SPR_EVENT_ACK [context]->write(0);
842	}
843
844	if (1)
845	{
846	SC_START(3);
847
848	LABEL("exception (begin)");
849	in_NB_INST_DECOD_ALL [context]->write(1);
850	in_NB_INST_COMMIT_ALL [context]->write(1);
851	in_NB_INST_COMMIT_MEM [context]->write(1);
852
853	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
854	if (_param->_have_port_depth)
855	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
856	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
857	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0);
858	in_COMMIT_EVENT_ADDRESS ->write(0xa00);
859	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00);
860	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00);
861	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0);
862
863	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
864
865	do
866	{
867	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
868
869	SC_START(1);
870	}
871	while (not ( in_COMMIT_EVENT_VAL ->read() and
872	out_COMMIT_EVENT_ACK ->read()));
873	in_COMMIT_EVENT_VAL ->write(0);
874
875	LABEL("exception (wait end)");
876	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
877
878	SC_START(3);
879
880	in_NB_INST_DECOD_ALL [context]->write(0);
881	in_NB_INST_COMMIT_ALL [context]->write(0);
882	in_NB_INST_COMMIT_MEM [context]->write(0);
883
884	SC_START(1);
885
886	LABEL("exception (wait event)");
887
888	bool find = false;
889	do
890	{
891	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
892
893	SC_START(0);
894
895	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
896	{
897	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xa00);
898	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xb00);
899	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
900	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
901
902	find = true;
903	}
904
905	SC_START(1);
906	}
907	while (not find);
908
909	in_EVENT_ACK [context]->write(0);
910
911	LABEL("exception (wait spr)");
912
913	find = false;
914	do
915	{
916	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
917
918	SC_START(0);
919
920	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
921	{
922	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xb00);
923	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xc00);
924	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
925	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
926	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
927
928	find = true;
929	}
930
931	SC_START(1);
932	}
933	while (not find);
934
935	in_SPR_EVENT_ACK [context]->write(0);
936	}
937
938	if (1)
939	{
940	SC_START(3);
941
942	LABEL("exception (begin)");
943	in_NB_INST_DECOD_ALL [context]->write(1);
944	in_NB_INST_COMMIT_ALL [context]->write(1);
945	in_NB_INST_COMMIT_MEM [context]->write(1);
946
947	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
948	if (_param->_have_port_depth)
949	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
950	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
951	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1);
952	in_COMMIT_EVENT_ADDRESS ->write(0xd00);
953	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00);
954	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00);
955	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0);
956
957	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
958
959	do
960	{
961	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
962
963	SC_START(1);
964	}
965	while (not ( in_COMMIT_EVENT_VAL ->read() and
966	out_COMMIT_EVENT_ACK ->read()));
967	in_COMMIT_EVENT_VAL ->write(0);
968
969	LABEL("exception (wait end)");
970	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
971
972	SC_START(3);
973
974	in_NB_INST_DECOD_ALL [context]->write(0);
975	in_NB_INST_COMMIT_ALL [context]->write(0);
976	in_NB_INST_COMMIT_MEM [context]->write(0);
977
978	SC_START(1);
979
980	LABEL("exception (wait event)");
981
982	bool find = false;
983	do
984	{
985	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
986
987	SC_START(0);
988
989	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
990	{
991	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xd00);
992	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xe00);
993	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
994	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
995
996	find = true;
997	}
998
999	SC_START(1);
1000	}
1001	while (not find);
1002
1003	in_EVENT_ACK [context]->write(0);
1004
1005	LABEL("exception (wait spr)");
1006
1007	find = false;
1008	do
1009	{
1010	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1011
1012	SC_START(0);
1013
1014	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1015	{
1016	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xe00);
1017	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xf00);
1018	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
1019	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
1020	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1021
1022	find = true;
1023	}
1024
1025	SC_START(1);
1026	}
1027	while (not find);
1028
1029	in_SPR_EVENT_ACK [context]->write(0);
1030	}
1031
1032	if (1)
1033	{
1034	SC_START(3);
1035
1036	LABEL("exception (begin)");
1037	in_NB_INST_DECOD_ALL [context]->write(1);
1038	in_NB_INST_COMMIT_ALL [context]->write(1);
1039	in_NB_INST_COMMIT_MEM [context]->write(1);
1040
1041	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
1042	if (_param->_have_port_depth)
1043	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
1044	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
1045	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0);
1046	in_COMMIT_EVENT_ADDRESS ->write(0xa00);
1047	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00);
1048	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00);
1049	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1);
1050
1051	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1052
1053	do
1054	{
1055	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
1056
1057	SC_START(1);
1058	}
1059	while (not ( in_COMMIT_EVENT_VAL ->read() and
1060	out_COMMIT_EVENT_ACK ->read()));
1061	in_COMMIT_EVENT_VAL ->write(0);
1062
1063	LABEL("exception (wait end)");
1064	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1065
1066	SC_START(3);
1067
1068	in_NB_INST_DECOD_ALL [context]->write(0);
1069	in_NB_INST_COMMIT_ALL [context]->write(0);
1070	in_NB_INST_COMMIT_MEM [context]->write(0);
1071
1072	SC_START(1);
1073
1074	LABEL("exception (wait event)");
1075
1076	bool find = false;
1077	do
1078	{
1079	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1080
1081	SC_START(0);
1082
1083	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1084	{
1085	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xa00);
1086	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xb00);
1087	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1088	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1089
1090	find = true;
1091	}
1092
1093	SC_START(1);
1094	}
1095	while (not find);
1096
1097	in_EVENT_ACK [context]->write(0);
1098
1099	LABEL("exception (wait spr)");
1100
1101	find = false;
1102	do
1103	{
1104	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1105
1106	SC_START(0);
1107
1108	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1109	{
1110	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xb00);
1111	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xc00);
1112	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),1);
1113	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
1114	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1115
1116	find = true;
1117	}
1118
1119	SC_START(1);
1120	}
1121	while (not find);
1122
1123	in_SPR_EVENT_ACK [context]->write(0);
1124	}
1125
1126	if (1)
1127	{
1128	SC_START(3);
1129
1130	LABEL("exception (begin)");
1131	in_NB_INST_DECOD_ALL [context]->write(1);
1132	in_NB_INST_COMMIT_ALL [context]->write(1);
1133	in_NB_INST_COMMIT_MEM [context]->write(1);
1134
1135	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
1136	if (_param->_have_port_depth)
1137	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
1138	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
1139	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1);
1140	in_COMMIT_EVENT_ADDRESS ->write(0xd00);
1141	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00);
1142	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00);
1143	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1);
1144
1145	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1146
1147	do
1148	{
1149	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
1150
1151	SC_START(1);
1152	}
1153	while (not ( in_COMMIT_EVENT_VAL ->read() and
1154	out_COMMIT_EVENT_ACK ->read()));
1155	in_COMMIT_EVENT_VAL ->write(0);
1156
1157	LABEL("exception (wait end)");
1158	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1159
1160	SC_START(3);
1161
1162	in_NB_INST_DECOD_ALL [context]->write(0);
1163	in_NB_INST_COMMIT_ALL [context]->write(0);
1164	in_NB_INST_COMMIT_MEM [context]->write(0);
1165
1166	SC_START(1);
1167
1168	LABEL("exception (wait event)");
1169
1170	bool find = false;
1171	do
1172	{
1173	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1174
1175	SC_START(0);
1176
1177	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1178	{
1179	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xd00);
1180	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xe00);
1181	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1182	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1183
1184	find = true;
1185	}
1186
1187	SC_START(1);
1188	}
1189	while (not find);
1190
1191	in_EVENT_ACK [context]->write(0);
1192
1193	LABEL("exception (wait spr)");
1194
1195	find = false;
1196	do
1197	{
1198	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1199
1200	SC_START(0);
1201
1202	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1203	{
1204	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xe00);
1205	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xf00);
1206	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),1);
1207	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
1208	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1209
1210	find = true;
1211	}
1212
1213	SC_START(1);
1214	}
1215	while (not find);
1216
1217	in_SPR_EVENT_ACK [context]->write(0);
1218	}
1219
1220
1221	SC_START(1);
1222	}
1223
1224
1225	/********************************************************
1226	* Simulation - End
1227	********************************************************/
1228
1229	TEST_OK ("End of Simulation");
1230	delete _time;
1231
1232	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
1233
1234	delete in_CLOCK;
1235	delete in_NRESET;
1236
1237	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_VAL ,_param->_nb_context);
1238	DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,_param->_nb_context);
1239	//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
1240	//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context);
1241	//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context);
1242	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
1243	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context);
1244	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
1245	DELETE1_SC_SIGNAL( in_DECOD_EVENT_VAL ,_param->_nb_decod_unit);
1246	DELETE1_SC_SIGNAL(out_DECOD_EVENT_ACK ,_param->_nb_decod_unit);
1247	DELETE1_SC_SIGNAL( in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit);
1248	DELETE1_SC_SIGNAL( in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit);
1249	DELETE1_SC_SIGNAL( in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit);
1250	DELETE1_SC_SIGNAL( in_DECOD_EVENT_IS_DELAY_SLOT ,_param->_nb_decod_unit);
1251	DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit);
1252	DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit);
1253	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_VAL );
1254	DELETE_SC_SIGNAL (out_COMMIT_EVENT_ACK );
1255	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID );
1256	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_DEPTH );
1257	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_TYPE );
1258	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT );
1259	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS );
1260	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR );
1261	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
1262	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR );
1263	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
1264	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
1265	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
1266	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
1267	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
1268	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
1269	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
1270	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
1271	DELETE1_SC_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_context );
1272	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context );
1273	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context );
1274	DELETE1_SC_SIGNAL(out_EVENT_VAL ,_param->_nb_context );
1275	DELETE1_SC_SIGNAL( in_EVENT_ACK ,_param->_nb_context );
1276	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context );
1277	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context );
1278	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context );
1279	DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context );
1280	DELETE1_SC_SIGNAL(out_EVENT_TYPE ,_param->_nb_context );
1281	DELETE1_SC_SIGNAL(out_EVENT_DEPTH ,_param->_nb_context );
1282	DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context );
1283	DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context );
1284	DELETE1_SC_SIGNAL(out_SPR_EVENT_EPCR ,_param->_nb_context );
1285	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR ,_param->_nb_context );
1286	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,_param->_nb_context );
1287	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,_param->_nb_context );
1288	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context );
1289	DELETE1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,_param->_nb_context );
1290	DELETE1_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_context );
1291	DELETE1_SC_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context );
1292	DELETE1_SC_SIGNAL( in_SPR_SR_EPH ,_param->_nb_context );
1293
1294	DELETE1_SC_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_context );
1295	}
1296	#endif
1297
1298	delete _Context_State;
1299	#ifdef STATISTICS
1300	delete _parameters_statistics;
1301	#endif
1302	}

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