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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp @ 105

Last change on this file since 105 was 105, checked in by rosiere, 15 years ago
1) Bug fix : Load Miss Speculation (in Commit_unit, Update Prediction Table and Context State) 2) Change address, in rob write address_next. 3) Move Meta_Predictor in save directory
Property svn:keywords set to `Id`
File size: 28.0 KB

Line
1	/*
2	* $Id: test.cpp 105 2009-02-05 11:18:31Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 1
10	#define CYCLE_MAX (2048*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/test.h"
13	#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h"
14	#include <list>
15	#include "Common/include/Test.h"
16	#include "Behavioural/include/Allocation.h"
17
18	void test (string name,
19	morpheo::behavioural::core::multi_front_end::front_end::decod_unit::decod::Parameters * _param)
20	{
21	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
22
23	#ifdef STATISTICS
24	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
25	#endif
26
27	Tusage_t _usage = USE_ALL;
28
29	// _usage = usage_unset(_usage,USE_SYSTEMC );
30	// _usage = usage_unset(_usage,USE_VHDL );
31	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
32	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
33	// _usage = usage_unset(_usage,USE_POSITION );
34	// _usage = usage_unset(_usage,USE_STATISTICS );
35	// _usage = usage_unset(_usage,USE_INFORMATION );
36
37	Decod * _Decod = new Decod
38	(name.c_str(),
39	#ifdef STATISTICS
40	_parameters_statistics,
41	#endif
42	_param,
43	_usage);
44
45	#ifdef SYSTEMC
46	/*********************************************************************
47	* Déclarations des signaux
48	*********************************************************************/
49	string rename;
50
51	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
52	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
53
54	ALLOC2_SC_SIGNAL( in_IFETCH_VAL ," in_IFETCH_VAL ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
55	ALLOC2_SC_SIGNAL(out_IFETCH_ACK ,"out_IFETCH_ACK ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
56	ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION ," in_IFETCH_INSTRUCTION ",Tinstruction_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
57	ALLOC1_SC_SIGNAL( in_IFETCH_CONTEXT_ID ," in_IFETCH_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
58	ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS ," in_IFETCH_ADDRESS ",Tgeneral_address_t ,_param->_nb_context);
59	// ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS_NEXT ," in_IFETCH_ADDRESS_NEXT ",Tgeneral_address_t ,_param->_nb_context);
60	ALLOC1_SC_SIGNAL( in_IFETCH_INST_IFETCH_PTR ," in_IFETCH_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ,_param->_nb_context);
61	ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_STATE ," in_IFETCH_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_context);
62	ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ," in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_context);
63	ALLOC1_SC_SIGNAL( in_IFETCH_EXCEPTION ," in_IFETCH_EXCEPTION ",Texception_t ,_param->_nb_context);
64
65	ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
66	ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
67	ALLOC1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
68	ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod);
69	ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_nb_inst_decod);
70	ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_nb_inst_decod);
71	ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod);
72	ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod);
73	ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod);
74	ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod);
75	ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_decod);
76	ALLOC1_SC_SIGNAL(out_DECOD_READ_RA ,"out_DECOD_READ_RA ",Tcontrol_t ,_param->_nb_inst_decod);
77	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,"out_DECOD_NUM_REG_RA ",Tgeneral_address_t ,_param->_nb_inst_decod);
78	ALLOC1_SC_SIGNAL(out_DECOD_READ_RB ,"out_DECOD_READ_RB ",Tcontrol_t ,_param->_nb_inst_decod);
79	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,"out_DECOD_NUM_REG_RB ",Tgeneral_address_t ,_param->_nb_inst_decod);
80	ALLOC1_SC_SIGNAL(out_DECOD_READ_RC ,"out_DECOD_READ_RC ",Tcontrol_t ,_param->_nb_inst_decod);
81	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,"out_DECOD_NUM_REG_RC ",Tspecial_address_t ,_param->_nb_inst_decod);
82	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RD ,"out_DECOD_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_decod);
83	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,"out_DECOD_NUM_REG_RD ",Tgeneral_address_t ,_param->_nb_inst_decod);
84	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RE ,"out_DECOD_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_decod);
85	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_nb_inst_decod);
86	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_nb_inst_decod);
87	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ,_param->_nb_inst_decod);
88	ALLOC1_SC_SIGNAL(out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
89	ALLOC1_SC_SIGNAL( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
90	ALLOC1_SC_SIGNAL(out_PREDICT_CONTEXT_ID ,"out_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
91	ALLOC1_SC_SIGNAL(out_PREDICT_MATCH_INST_IFETCH_PTR ,"out_PREDICT_MATCH_INST_IFETCH_PTR ",Tcontrol_t ,_param->_nb_inst_decod);
92	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,"out_PREDICT_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_inst_decod);
93	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"out_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ,_param->_nb_inst_decod);
94	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_CONDITION ,"out_PREDICT_BRANCH_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
95	// ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE ,"out_PREDICT_BRANCH_STACK_WRITE ",Tcontrol_t ,_param->_nb_inst_decod);
96	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_DIRECTION ,"out_PREDICT_BRANCH_DIRECTION ",Tcontrol_t ,_param->_nb_inst_decod);
97	ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,"out_PREDICT_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_decod);
98	ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,"out_PREDICT_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_decod);
99	// ALLOC1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ," in_PREDICT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod);
100	ALLOC1_SC_SIGNAL( in_CONTEXT_DECOD_ENABLE ," in_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context);
101	ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH_VAL ," in_CONTEXT_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context);
102	ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH ," in_CONTEXT_DEPTH ",Tdepth_t ,_param->_nb_context);
103	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_VAL ,"out_CONTEXT_EVENT_VAL ",Tcontrol_t );
104	ALLOC_SC_SIGNAL ( in_CONTEXT_EVENT_ACK ," in_CONTEXT_EVENT_ACK ",Tcontrol_t );
105	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_CONTEXT_ID ,"out_CONTEXT_EVENT_CONTEXT_ID ",Tcontext_t );
106	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_DEPTH ,"out_CONTEXT_EVENT_DEPTH ",Tdepth_t );
107	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_TYPE ,"out_CONTEXT_EVENT_TYPE ",Tevent_type_t );
108	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_IS_DELAY_SLOT ,"out_CONTEXT_EVENT_IS_DELAY_SLOT ",Tcontrol_t );
109	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_ADDRESS ,"out_CONTEXT_EVENT_ADDRESS ",Tgeneral_data_t );
110	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_ADDRESS_EPCR ,"out_CONTEXT_EVENT_ADDRESS_EPCR ",Tgeneral_data_t );
111
112	/********************************************************
113	* Instanciation
114	********************************************************/
115
116	msg(_("<%s> : Instanciation of _Decod.\n"),name.c_str());
117
118	((_Decod->in_CLOCK)) ((in_CLOCK));
119	((_Decod->in_NRESET)) ((in_NRESET));
120
121	INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_VAL ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
122	INSTANCE2_SC_SIGNAL(_Decod,out_IFETCH_ACK ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
123	INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
124	if (_param->_have_port_context_id)
125	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_CONTEXT_ID ,_param->_nb_context);
126	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS ,_param->_nb_context);
127	// INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS_NEXT ,_param->_nb_context);
128	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_STATE ,_param->_nb_context);
129	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_EXCEPTION ,_param->_nb_context);
130
131	for (uint32_t i=0; i<_param->_nb_context; i++)
132	{
133	if (_param->_have_port_inst_ifetch_ptr)
134	INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_INST_IFETCH_PTR [i]);
135	// if (_param->_have_port_branch_update_prediction_id)
136	if (_param->_have_port_depth)
137	INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]);
138	}
139
140	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_VAL ,_param->_nb_inst_decod);
141	INSTANCE1_SC_SIGNAL(_Decod, in_DECOD_ACK ,_param->_nb_inst_decod);
142	if (_param->_have_port_context_id)
143	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
144	if (_param->_have_port_depth)
145	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_DEPTH ,_param->_nb_inst_decod);
146	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_TYPE ,_param->_nb_inst_decod);
147	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_OPERATION ,_param->_nb_inst_decod);
148	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod);
149	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod);
150	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod);
151	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod);
152	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IMMEDIAT ,_param->_nb_inst_decod);
153	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RA ,_param->_nb_inst_decod);
154	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RA ,_param->_nb_inst_decod);
155	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RB ,_param->_nb_inst_decod);
156	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RB ,_param->_nb_inst_decod);
157	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RC ,_param->_nb_inst_decod);
158	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RC ,_param->_nb_inst_decod);
159	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_WRITE_RD ,_param->_nb_inst_decod);
160	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RD ,_param->_nb_inst_decod);
161	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_WRITE_RE ,_param->_nb_inst_decod);
162	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod);
163	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION_USE ,_param->_nb_inst_decod);
164	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION ,_param->_nb_inst_decod);
165	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_VAL ,_param->_nb_inst_decod);
166	INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_ACK ,_param->_nb_inst_decod);
167	if (_param->_have_port_context_id)
168	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_CONTEXT_ID ,_param->_nb_inst_decod);
169	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod);
170	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod);
171	// if (_param->_have_port_branch_update_prediction_id)
172	if (_param->_have_port_depth)
173	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod);
174	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod);
175	// INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STACK_WRITE ,_param->_nb_inst_decod);
176	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_DIRECTION ,_param->_nb_inst_decod);
177	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod);
178	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod);
179	// INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod);
180	INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DECOD_ENABLE ,_param->_nb_context);
181	INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH_VAL ,_param->_nb_context);
182	for (uint32_t i=0; i<_param->_nb_context; i++)
183	if (_param->_have_port_depth)
184	INSTANCE_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH [i]);
185	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_VAL );
186	INSTANCE_SC_SIGNAL (_Decod, in_CONTEXT_EVENT_ACK );
187	if (_param->_have_port_context_id)
188	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_CONTEXT_ID );
189	if (_param->_have_port_depth)
190	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_DEPTH );
191	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_TYPE );
192	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_IS_DELAY_SLOT );
193	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_ADDRESS );
194	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_ADDRESS_EPCR );
195
196	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
197
198	Time * _time = new Time();
199
200	/********************************************************
201	* Simulation - Begin
202	********************************************************/
203
204	// Initialisation
205
206	const uint32_t seed = 0;
207	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
208
209	const int32_t percent_transaction_ifetch = 75;
210	const int32_t percent_transaction_decod = 75;
211	const int32_t percent_transaction_predict = 75;
212	const int32_t percent_transaction_event = 75;
213
214	srand(seed);
215
216	SC_START(0);
217	LABEL("Initialisation");
218
219	LABEL("Reset");
220	in_NRESET->write(0);
221	SC_START(5);
222	in_NRESET->write(1);
223
224	LABEL("Loop of Test");
225
226	for (uint32_t i=0; i<_param->_nb_context; i++)
227	in_CONTEXT_DEPTH_VAL [i]->write(1);
228
229	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
230	{
231	LABEL("Iteration %d",iteration);
232
233	Decod_request request [_param->_nb_context];
234
235	uint32_t nb_request = 0;
236
237	uint32_t delay_slot_previous [_param->_nb_context];
238	uint32_t delay_slot_current [_param->_nb_context];
239	uint32_t delay_slot_next [_param->_nb_context];
240
241	for (uint32_t i=0; i<_param->_nb_context; i++)
242	{
243	nb_request += request[i].size();
244	delay_slot_current [i] = false;
245	delay_slot_next [i] = false;
246	}
247
248	while (nb_request > 0)
249	{
250	for (uint32_t i=0; i<_param->_nb_context; i++)
251	{
252	delay_slot_previous [i] = false;
253
254	in_CONTEXT_DECOD_ENABLE [i]->write((rand()%100)<percent_transaction_decod);
255
256	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
257	in_IFETCH_VAL [i][j]->write(0);
258
259	if ((rand()%100)<percent_transaction_ifetch)
260	{
261	list<entry_t>::iterator it = request[i].begin();
262
263	if (it!=request [i].end())
264	{
265	uint32_t lsb = it->_address%_param->_nb_inst_fetch[i];
266
267	in_IFETCH_ADDRESS [i]->write(it->_address-lsb);
268	in_IFETCH_BRANCH_STATE [i]->write(BRANCH_STATE_NONE);
269	if (_param->_have_port_inst_ifetch_ptr)
270	in_IFETCH_INST_IFETCH_PTR [i]->write(0);
271	in_IFETCH_EXCEPTION [i]->write(EXCEPTION_IFETCH_NONE);
272
273	// Alignement
274	for (uint32_t j=lsb; j<_param->_nb_inst_fetch[i]; j++)
275	{
276	in_IFETCH_VAL [i][j]->write(1);
277	in_IFETCH_INSTRUCTION [i][j]->write(it->_instruction);
278	// in_IFETCH_ADDRESS_NEXT [i]->write(it->_address_next);
279	if (it->_type == TYPE_BRANCH)
280	in_IFETCH_BRANCH_STATE [i]->write(it->_branch_state);
281	in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]->write(it->_branch_update_prediction_id);
282
283	if ((it->_is_delay_slot) or
284	((++it)==request [i].end()))
285	break;
286	}
287	}
288	}
289	}
290
291	{
292	bool previous_ack = true;
293
294	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
295	{
296	bool ack = previous_ack and ((rand()%100)<percent_transaction_decod);
297	in_DECOD_ACK [i]->write(ack);
298
299	previous_ack = ack;
300
301	in_PREDICT_ACK [i]->write((rand()%100)<percent_transaction_predict);
302	// in_PREDICT_CAN_CONTINUE [i]->write(0);
303	}
304	}
305
306	in_CONTEXT_EVENT_ACK->write((rand()%100)<percent_transaction_event);
307
308	SC_START(0);
309
310
311	uint32_t nb_inst_ifetch = 0;
312	for (uint32_t i=0; i<_param->_nb_context; i++)
313	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
314	if (in_IFETCH_VAL[i][j]->read() and out_IFETCH_ACK[i][j]->read())
315	{
316	LABEL("IFETCH [%d][%d] : transaction",i,j);
317	nb_inst_ifetch ++;
318	}
319
320	uint32_t nb_inst_decod = 0;
321	uint32_t find_event = false;
322
323	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
324	if (out_DECOD_VAL[i]->read() and in_DECOD_ACK[i]->read())
325	{
326	Tcontext_t context = (_param->_have_port_context_id)?out_DECOD_CONTEXT_ID[i]->read():0;
327
328	LABEL("DECOD [%d] : transaction",i );
329	LABEL(" * context : %d",context);
330	LABEL(" * instruction : 0x%x",request [context].front()._instruction);
331
332	if (_param->_have_port_depth)
333	TEST(Tdepth_t , out_DECOD_DEPTH [i]->read(), request [context].front()._depth );
334	TEST(Ttype_t , out_DECOD_TYPE [i]->read(), request [context].front()._type );
335	TEST(Toperation_t , out_DECOD_OPERATION [i]->read(), request [context].front()._operation );
336	TEST(Tcontrol_t , out_DECOD_IS_DELAY_SLOT [i]->read(), request [context].front()._is_delay_slot);
337	TEST(Tcontrol_t , delay_slot_current [context] , request [context].front()._is_delay_slot);
338	// TEST(Tgeneral_data_t , out_DECOD_ADDRESS_NEXT [i]->read(), request [context].front()._address_next );
339	TEST(Tcontrol_t , out_DECOD_HAS_IMMEDIAT [i]->read(), request [context].front()._has_immediat );
340	if (request [context].front()._has_immediat)
341	TEST(Tgeneral_data_t , out_DECOD_IMMEDIAT [i]->read(), request [context].front()._immediat );
342	TEST(Tcontrol_t , out_DECOD_READ_RA [i]->read(), request [context].front()._read_ra );
343	if (request [context].front()._read_ra)
344	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RA [i]->read(), request [context].front()._num_reg_ra );
345	TEST(Tcontrol_t , out_DECOD_READ_RB [i]->read(), request [context].front()._read_rb );
346	if (request [context].front()._read_rb)
347	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RB [i]->read(), request [context].front()._num_reg_rb );
348	TEST(Tcontrol_t , out_DECOD_READ_RC [i]->read(), request [context].front()._read_rc );
349	if (request [context].front()._read_rc)
350	TEST(Tspecial_address_t, out_DECOD_NUM_REG_RC [i]->read(), request [context].front()._num_reg_rc );
351	TEST(Tcontrol_t , out_DECOD_WRITE_RD [i]->read(), request [context].front()._write_rd );
352	if (request [context].front()._write_rd)
353	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RD [i]->read(), request [context].front()._num_reg_rd );
354	TEST(Tcontrol_t , out_DECOD_WRITE_RE [i]->read(), request [context].front()._write_re );
355	if (request [context].front()._write_re)
356	TEST(Tspecial_address_t, out_DECOD_NUM_REG_RE [i]->read(), request [context].front()._num_reg_re );
357	TEST(Texception_t , out_DECOD_EXCEPTION_USE [i]->read(), request [context].front()._exception_use);
358
359	if (request [context].front()._type == TYPE_BRANCH)
360	{
361	delay_slot_next [context] = true;
362
363	TEST(Tcontrol_t, out_PREDICT_VAL[i]->read(), true);
364	TEST(Tcontrol_t, in_PREDICT_ACK[i]->read(), true);
365
366	LABEL("PREDICT [%d] : transaction",i );
367
368	if (_param->_have_port_context_id)
369	TEST(Tcontext_t , out_PREDICT_CONTEXT_ID [i]->read(), context);
370	TEST(Tcontrol_t , out_PREDICT_MATCH_INST_IFETCH_PTR [i]->read(),((request [context].front()._address)%_param->_nb_inst_fetch[context]) == 0);
371	TEST(Tbranch_state_t , out_PREDICT_BRANCH_STATE [i]->read(), request [context].front()._branch_state );
372	// if (_param->_have_port_branch_update_prediction_id)
373	if (_param->_have_port_depth)
374	TEST(Tprediction_ptr_t , out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]->read(), request [context].front()._branch_update_prediction_id);
375	TEST(Tbranch_condition_t, out_PREDICT_BRANCH_CONDITION [i]->read(), request [context].front()._branch_condition );
376	// TEST(Tcontrol_t , out_PREDICT_BRANCH_STACK_WRITE [i]->read(), request [context].front()._branch_stack_write );
377	TEST(Tcontrol_t , out_PREDICT_BRANCH_DIRECTION [i]->read(), request [context].front()._branch_direction );
378	TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_SRC [i]->read(), request [context].front()._address );
379	TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_DEST [i]->read(), request [context].front()._branch_address_dest );
380	}
381	else
382	{
383	TEST(Tcontrol_t, out_PREDICT_VAL[i]->read(), false);
384	}
385
386	TEST(bool, find_event, false); // can continue decod after event
387	if (request [context].front()._context_event_type != EVENT_TYPE_NONE)
388	{
389	find_event = true;
390
391	LABEL("CONTEXT_EVENT : transaction");
392
393	if (_param->_have_port_context_id)
394	TEST(Tcontext_t ,out_CONTEXT_EVENT_CONTEXT_ID ->read(), context);
395	if (_param->_have_port_depth )
396	TEST(Tcontext_t ,out_CONTEXT_EVENT_DEPTH ->read(), request [context].front()._depth );
397	TEST(Tevent_type_t ,out_CONTEXT_EVENT_TYPE ->read(), request [context].front()._context_event_type);
398	TEST(Tcontrol_t ,out_CONTEXT_EVENT_IS_DELAY_SLOT->read(), request [context].front()._is_delay_slot);
399	TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS ->read(), request [context].front()._address );
400	TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS_EPCR ->read(), request [context].front()._address_next );
401
402	}
403
404	TEST(bool, delay_slot_previous [context], false); // can't continue
405	delay_slot_previous [context] = delay_slot_current [context];
406	delay_slot_current [context] = delay_slot_next [context];
407	delay_slot_next [context] = false;
408
409	request [context].pop_front();
410	nb_inst_decod ++;
411	nb_request --;
412	}
413
414	TEST(bool, (out_CONTEXT_EVENT_VAL->read() and in_CONTEXT_EVENT_ACK->read()), find_event);
415	TEST(uint32_t, nb_inst_decod, nb_inst_ifetch);
416
417	SC_START(1);
418	}
419	}
420
421	/********************************************************
422	* Simulation - End
423	********************************************************/
424
425	TEST_OK ("End of Simulation");
426	delete _time;
427
428	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
429
430	delete in_CLOCK;
431	delete in_NRESET;
432
433	delete [] in_IFETCH_VAL ;
434	delete [] out_IFETCH_ACK ;
435	delete [] in_IFETCH_INSTRUCTION ;
436	delete [] in_IFETCH_CONTEXT_ID ;
437	delete [] in_IFETCH_ADDRESS ;
438	// delete [] in_IFETCH_ADDRESS_NEXT ;
439	delete [] in_IFETCH_INST_IFETCH_PTR ;
440	delete [] in_IFETCH_BRANCH_STATE ;
441	delete [] in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;
442	delete [] in_IFETCH_EXCEPTION ;
443
444	delete [] out_DECOD_VAL ;
445	delete [] in_DECOD_ACK ;
446	delete [] out_DECOD_CONTEXT_ID ;
447	delete [] out_DECOD_DEPTH ;
448	delete [] out_DECOD_TYPE ;
449	delete [] out_DECOD_OPERATION ;
450	delete [] out_DECOD_NO_EXECUTE ;
451	delete [] out_DECOD_IS_DELAY_SLOT ;
452	delete [] out_DECOD_ADDRESS_NEXT ;
453	delete [] out_DECOD_HAS_IMMEDIAT ;
454	delete [] out_DECOD_IMMEDIAT ;
455	delete [] out_DECOD_READ_RA ;
456	delete [] out_DECOD_NUM_REG_RA ;
457	delete [] out_DECOD_READ_RB ;
458	delete [] out_DECOD_NUM_REG_RB ;
459	delete [] out_DECOD_READ_RC ;
460	delete [] out_DECOD_NUM_REG_RC ;
461	delete [] out_DECOD_WRITE_RD ;
462	delete [] out_DECOD_NUM_REG_RD ;
463	delete [] out_DECOD_WRITE_RE ;
464	delete [] out_DECOD_NUM_REG_RE ;
465	delete [] out_DECOD_EXCEPTION_USE ;
466	delete [] out_DECOD_EXCEPTION ;
467
468	delete [] out_PREDICT_VAL ;
469	delete [] in_PREDICT_ACK ;
470	delete [] out_PREDICT_CONTEXT_ID ;
471	delete [] out_PREDICT_MATCH_INST_IFETCH_PTR ;
472	delete [] out_PREDICT_BRANCH_STATE ;
473	delete [] out_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
474	delete [] out_PREDICT_BRANCH_CONDITION ;
475	//delete [] out_PREDICT_BRANCH_STACK_WRITE ;
476	delete [] out_PREDICT_BRANCH_DIRECTION ;
477	delete [] out_PREDICT_ADDRESS_SRC ;
478	delete [] out_PREDICT_ADDRESS_DEST ;
479	//delete [] in_PREDICT_CAN_CONTINUE ;
480
481	delete [] in_CONTEXT_DECOD_ENABLE ;
482	delete [] in_CONTEXT_DEPTH_VAL ;
483	delete [] in_CONTEXT_DEPTH ;
484
485	delete out_CONTEXT_EVENT_VAL ;
486	delete in_CONTEXT_EVENT_ACK ;
487	delete out_CONTEXT_EVENT_CONTEXT_ID ;
488	delete out_CONTEXT_EVENT_DEPTH ;
489	delete out_CONTEXT_EVENT_TYPE ;
490	delete out_CONTEXT_EVENT_IS_DELAY_SLOT ;
491	delete out_CONTEXT_EVENT_ADDRESS ;
492	delete out_CONTEXT_EVENT_ADDRESS_EPCR ;
493	#endif
494
495	delete _Decod;
496	#ifdef STATISTICS
497	delete _parameters_statistics;
498	#endif
499	}

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