source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp @ 98

Last change on this file since 98 was 98, checked in by rosiere, 15 years ago

1) Fix bug (read unit, RAT -> write in R0, SPR desallocation ...)
2) Change VHDL Execute_queue -> use Generic/Queue?
3) Complete document on VHDL generation
4) Add soc test
  • Property svn:keywords set to Id
File size: 7.5 KB
Line 
1#ifdef SYSTEMC
2/*
3 * $Id: Address_management_transition.cpp 98 2008-12-31 10:18:08Z rosiere $
4 *
5 * [ Description ]
6 *
7 */
8
9#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_front_end {
15namespace front_end {
16namespace ifetch_unit {
17namespace address_management {
18
19
20#undef  FUNCTION
21#define FUNCTION "Address_management::transition"
22  void Address_management::transition (void)
23  {
24    log_begin(Address_management,FUNCTION);
25    log_function(Address_management,FUNCTION,_name.c_str());
26
27    if (PORT_READ(in_NRESET) == 0)
28      {
29        // nothing is valid
30        reg_PC_CURRENT_VAL   = 0;
31
32        reg_PC_NEXT_VAL      = 1;
33        reg_PC_NEXT          = 0x100>>2;
34
35        reg_PC_NEXT_NEXT_VAL = 0;
36      }
37    else
38      {
39        // =========================================
40        // ===== PREDICT ===========================
41        // =========================================
42        if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL)
43          {
44            for (uint32_t i=0; i<_param->_nb_instruction; i++)
45            reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]);
46            if (_param->_have_port_inst_ifetch_ptr)
47            reg_PC_NEXT_INST_IFETCH_PTR             = PORT_READ(in_PREDICT_INST_IFETCH_PTR            );
48            reg_PC_NEXT_BRANCH_STATE                = PORT_READ(in_PREDICT_BRANCH_STATE               );
49            if (_param->_have_port_depth)
50            reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
51           
52            reg_PC_NEXT_NEXT_VAL                    = 1; // address is valid
53            reg_PC_NEXT_NEXT                        = PORT_READ(in_PREDICT_PC_NEXT                    );
54            reg_PC_NEXT_NEXT_IS_DS_TAKE             = PORT_READ(in_PREDICT_PC_NEXT_IS_DS_TAKE         );
55
56#ifdef STATISTICS
57            if (usage_is_set(_usage,USE_STATISTICS))
58              (*_stat_nb_transaction_predict) ++;
59#endif
60          }
61
62        // =========================================
63        // ===== ADDRESS ===========================
64        // =========================================
65        // transaction with icache
66        if ( (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK)) or not reg_PC_CURRENT_VAL)
67          {
68#ifdef STATISTICS
69            if (usage_is_set(_usage,USE_STATISTICS))
70              if (reg_PC_CURRENT_VAL)
71                {
72                  (*_stat_nb_transaction_address) ++;
73                 
74                  for (uint32_t i=0; i<_param->_nb_instruction; i++)
75                    if (reg_PC_CURRENT_INSTRUCTION_ENABLE [i] == true)
76                      (*_stat_sum_packet_size) ++;
77                }
78#endif
79
80
81            Tcontrol_t pc_next_val = reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL;
82
83            // next pc became current pc
84            reg_PC_CURRENT_VAL                             = pc_next_val;
85
86            // if pc_next is not valid : don't erase PC and PC_IS_DS_TAKE : this register is send a the predict (to compute pc_next)
87            if (pc_next_val)
88              {
89                reg_PC_CURRENT                             = reg_PC_NEXT                            ;
90                reg_PC_CURRENT_IS_DS_TAKE                  = reg_PC_NEXT_IS_DS_TAKE                 ;
91                reg_PC_CURRENT_INST_IFETCH_PTR             = reg_PC_NEXT_INST_IFETCH_PTR            ;
92                reg_PC_CURRENT_BRANCH_STATE                = reg_PC_NEXT_BRANCH_STATE               ;
93                reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;
94
95                for (uint32_t i=0; i<_param->_nb_instruction; i++)
96                reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i];
97           
98                reg_PC_NEXT_VAL                            = reg_PC_NEXT_NEXT_VAL       ;
99                // if pc_next_next is not valid : don't erase PC_NEXT and PC_NEXT_IS_DS_TAKE : this register is send a the predict (to compute pc_next)
100                if (reg_PC_NEXT_NEXT_VAL)
101                  {
102                    reg_PC_NEXT                            = reg_PC_NEXT_NEXT           ;
103                    reg_PC_NEXT_IS_DS_TAKE                 = reg_PC_NEXT_NEXT_IS_DS_TAKE;
104                  }
105               
106                // invalid next next pc
107                reg_PC_NEXT_NEXT_VAL                       = 0;
108              }
109
110          }
111       
112
113        // =========================================
114        // ===== EVENT =============================
115        // =========================================
116        if (PORT_READ(in_EVENT_VAL) and internal_EVENT_ACK)
117          {
118            log_printf(TRACE,Address_management,FUNCTION,"  * EVENT : Transaction");
119            log_printf(TRACE,Address_management,FUNCTION,"    * IS_DS_TAKE       : %d"  ,PORT_READ(in_EVENT_IS_DS_TAKE      ));
120            log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS          : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS         ),PORT_READ(in_EVENT_ADDRESS         )<<2);
121            log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS_NEXT     : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS_NEXT    ),PORT_READ(in_EVENT_ADDRESS_NEXT    )<<2);
122            log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS_NEXT_VAL : %d"  ,PORT_READ(in_EVENT_ADDRESS_NEXT_VAL));
123            reg_PC_CURRENT_VAL                      = 0;
124            reg_PC_NEXT_VAL                         = 1;
125            reg_PC_NEXT                             = PORT_READ(in_EVENT_ADDRESS);
126            // Event is never is ds_take :
127            //  * branch miss speculation : can't be place a branch in delay slot
128            //  * load   miss speculation : the load is execute, the event_address is the next address (also the destination of branch)
129            //  * exception               : goto the first instruction of exception handler (also is not in delay slot).
130
131            reg_PC_NEXT_IS_DS_TAKE                  = PORT_READ(in_EVENT_IS_DS_TAKE);
132//          reg_PC_NEXT_INST_IFETCH_PTR             = 0;
133//          reg_PC_NEXT_BRANCH_STATE                = BRANCH_STATE_NONE;
134//          reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0;
135           
136            reg_PC_NEXT_INSTRUCTION_ENABLE [0]      = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle.
137            for (uint32_t i=1; i<_param->_nb_instruction; i++)
138              reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0;
139
140            reg_PC_NEXT_NEXT_VAL                    = PORT_READ(in_EVENT_ADDRESS_NEXT_VAL);
141            reg_PC_NEXT_NEXT                        = PORT_READ(in_EVENT_ADDRESS_NEXT);
142            reg_PC_NEXT_NEXT_IS_DS_TAKE             = 0;//??
143
144            // Note : is_ds_take = address_next_val
145            // Because, is not ds take, can continue in sequence
146
147// #ifdef DEBUG_TEST
148//             if (PORT_READ(in_EVENT_ADDRESS_NEXT_VAL) and not PORT_READ(in_EVENT_IS_DS_TAKE))
149//               throw ERRORMORPHEO(FUNCTION,_("Event : address_next_next_val but next is not a ds take"));
150// #endif
151
152#ifdef STATISTICS
153            if (usage_is_set(_usage,USE_STATISTICS))
154              (*_stat_nb_transaction_event) ++;
155#endif
156          }
157      }
158
159#if defined(DEBUG) and (DEBUG >= DEBUG_TRACE)
160    log_printf(TRACE,Address_management,FUNCTION,"  * Dump PC");
161    log_printf(TRACE,Address_management,FUNCTION,"    * Current   : %d %d 0x%.8x (%.8x)",reg_PC_CURRENT_VAL  , reg_PC_CURRENT_IS_DS_TAKE  , reg_PC_CURRENT  , reg_PC_CURRENT  <<2);
162    log_printf(TRACE,Address_management,FUNCTION,"    * Next      : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_VAL     , reg_PC_NEXT_IS_DS_TAKE     , reg_PC_NEXT     , reg_PC_NEXT     <<2);   
163    log_printf(TRACE,Address_management,FUNCTION,"    * Next_Next : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT, reg_PC_NEXT_NEXT<<2);   
164#endif
165
166#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
167    end_cycle ();
168#endif
169   
170    log_end(Address_management,FUNCTION);
171  };
172
173}; // end namespace address_management
174}; // end namespace ifetch_unit
175}; // end namespace front_end
176}; // end namespace multi_front_end
177}; // end namespace core
178
179}; // end namespace behavioural
180}; // end namespace morpheo             
181#endif
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