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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/test.cpp @ 113

Last change on this file since 113 was 113, checked in by rosiere, 15 years ago
1) Add modelsim simulation systemC 2) Modelsim cosimulation systemC / VHDL is not finish !!!! (cf execute_queue and write_unit) 3) Add multi architecture 5) Add template for comparator, multiplier and divider 6) Change Message Warning) Various test macro have change, many selftest can't compile
Property svn:keywords set to `Id`
File size: 18.0 KB

Line
1	/*
2	* $Id: test.cpp 113 2009-04-14 18:39:12Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 1
10	#define CYCLE_MAX (2048*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Behavioural/include/Allocation.h"
15	#include <list>
16	#include <set>
17
18	class entry_t
19	{
20	public : uint32_t _cycle;
21	public : Tpacket_t _packet;
22	public : Tgeneral_address_t _addr;
23
24	public : entry_t (uint32_t cycle,
25	Tpacket_t packet,
26	Tgeneral_address_t addr )
27	{
28	_cycle = cycle ;
29	_packet = packet;
30	_addr = addr ;
31	}
32	};
33
34	void test (string name,
35	morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Parameters * _param)
36	{
37	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
38
39	#ifdef STATISTICS
40	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,1000);
41	#endif
42
43	Tusage_t _usage = USE_ALL;
44
45	// _usage = usage_unset(_usage,USE_SYSTEMC );
46	// _usage = usage_unset(_usage,USE_VHDL );
47	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
48	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
49	// _usage = usage_unset(_usage,USE_POSITION );
50	// _usage = usage_unset(_usage,USE_STATISTICS );
51	// _usage = usage_unset(_usage,USE_INFORMATION );
52
53	Ifetch_queue * _Ifetch_queue = new Ifetch_queue
54	(name.c_str(),
55	#ifdef STATISTICS
56	_parameters_statistics,
57	#endif
58	_param,
59	_usage);
60
61	#ifdef SYSTEMC
62	/*********************************************************************
63	* Déclarations des signaux
64	*********************************************************************/
65	string rename;
66
67	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
68	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
69
70	sc_signal<Tcontrol_t > * in_ADDRESS_VAL ;
71	sc_signal<Tcontrol_t > * out_ADDRESS_ACK ;
72	sc_signal<Tifetch_queue_ptr_t > * out_ADDRESS_IFETCH_QUEUE_ID ;
73	sc_signal<Tcontrol_t > ** in_ADDRESS_INSTRUCTION_ENABLE ;//[nb_instruction]
74	sc_signal<Tgeneral_address_t > * in_ADDRESS_INSTRUCTION_ADDRESS ;
75	sc_signal<Tinst_ifetch_ptr_t > * in_ADDRESS_INST_IFETCH_PTR ;
76	sc_signal<Tbranch_state_t > * in_ADDRESS_BRANCH_STATE ;
77	sc_signal<Tprediction_ptr_t > * in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ;
78	sc_signal<Tcontrol_t > ** out_DECOD_VAL ;//[nb_instruction]
79	sc_signal<Tcontrol_t > ** in_DECOD_ACK ;//[nb_instruction]
80	sc_signal<Tinstruction_t > ** out_DECOD_INSTRUCTION ;//[nb_instruction]
81	sc_signal<Tgeneral_address_t > * out_DECOD_ADDRESS ;
82	sc_signal<Tinst_ifetch_ptr_t > * out_DECOD_INST_IFETCH_PTR ;
83	sc_signal<Tbranch_state_t > * out_DECOD_BRANCH_STATE ;
84	sc_signal<Tprediction_ptr_t > * out_DECOD_BRANCH_UPDATE_PREDICTION_ID ;
85	sc_signal<Texception_t > * out_DECOD_EXCEPTION ;
86	sc_signal<Tcontrol_t > * in_ICACHE_RSP_VAL ;
87	sc_signal<Tcontrol_t > * out_ICACHE_RSP_ACK ;
88	sc_signal<Tpacket_t > * in_ICACHE_RSP_PACKET_ID ;
89	sc_signal<Ticache_instruction_t > ** in_ICACHE_RSP_INSTRUCTION ;//[nb_instruction]
90	sc_signal<Ticache_error_t > * in_ICACHE_RSP_ERROR ;
91	sc_signal<Tcontrol_t > * in_EVENT_RESET_VAL ;// val if : miss_speculation, exception, synchronization
92	sc_signal<Tcontrol_t > * out_EVENT_RESET_ACK ;
93
94	ALLOC0_SC_SIGNAL( in_ADDRESS_VAL ," in_ADDRESS_VAL ",Tcontrol_t );
95	ALLOC0_SC_SIGNAL(out_ADDRESS_ACK ,"out_ADDRESS_ACK ",Tcontrol_t );
96	ALLOC0_SC_SIGNAL(out_ADDRESS_IFETCH_QUEUE_ID ,"out_ADDRESS_IFETCH_QUEUE_ID ",Tifetch_queue_ptr_t );
97	ALLOC1_SC_SIGNAL( in_ADDRESS_INSTRUCTION_ENABLE ," in_ADDRESS_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction);
98	ALLOC0_SC_SIGNAL( in_ADDRESS_INSTRUCTION_ADDRESS ," in_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t );
99	ALLOC0_SC_SIGNAL( in_ADDRESS_INST_IFETCH_PTR ," in_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t );
100	ALLOC0_SC_SIGNAL( in_ADDRESS_BRANCH_STATE ," in_ADDRESS_BRANCH_STATE ",Tbranch_state_t );
101	ALLOC0_SC_SIGNAL( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID," in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
102	ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_instruction);
103	ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_instruction);
104	ALLOC1_SC_SIGNAL(out_DECOD_INSTRUCTION ,"out_DECOD_INSTRUCTION ",Tinstruction_t ,_param->_nb_instruction);
105	ALLOC0_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_address_t );
106	ALLOC0_SC_SIGNAL(out_DECOD_INST_IFETCH_PTR ,"out_DECOD_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t );
107	ALLOC0_SC_SIGNAL(out_DECOD_BRANCH_STATE ,"out_DECOD_BRANCH_STATE ",Tbranch_state_t );
108	ALLOC0_SC_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t );
109	ALLOC0_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Tprediction_ptr_t );
110	ALLOC0_SC_SIGNAL( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t );
111	ALLOC0_SC_SIGNAL(out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t );
112	ALLOC0_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t );
113	ALLOC1_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION ",Ticache_instruction_t,_param->_nb_instruction);
114	ALLOC0_SC_SIGNAL( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t );
115	ALLOC0_SC_SIGNAL( in_EVENT_RESET_VAL ," in_EVENT_RESET_VAL ",Tcontrol_t );
116	ALLOC0_SC_SIGNAL(out_EVENT_RESET_ACK ,"out_EVENT_RESET_ACK ",Tcontrol_t );
117
118	/********************************************************
119	* Instanciation
120	********************************************************/
121
122	msg(_("<%s> : Instanciation of _Ifetch_queue.\n"),name.c_str());
123
124	((_Ifetch_queue->in_CLOCK)) ((in_CLOCK));
125	((_Ifetch_queue->in_NRESET)) ((in_NRESET));
126
127	INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_VAL );
128	INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_ADDRESS_ACK );
129	if (_param->_have_port_ifetch_queue_ptr)
130	INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_ADDRESS_IFETCH_QUEUE_ID );
131	INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction);
132	INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INSTRUCTION_ADDRESS );
133	if (_param->_have_port_inst_ifetch_ptr)
134	INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INST_IFETCH_PTR );
135	INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_BRANCH_STATE );
136	if (_param->_have_port_depth)
137	INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID);
138	INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_VAL ,_param->_nb_instruction);
139	INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_DECOD_ACK ,_param->_nb_instruction);
140	INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_INSTRUCTION ,_param->_nb_instruction);
141	INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_ADDRESS );
142	if (_param->_have_port_inst_ifetch_ptr)
143	INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_INST_IFETCH_PTR );
144	INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_BRANCH_STATE );
145	if (_param->_have_port_depth)
146	INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_BRANCH_UPDATE_PREDICTION_ID );
147	INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_EXCEPTION );
148	INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_VAL );
149	INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_ICACHE_RSP_ACK );
150	if (_param->_have_port_ifetch_queue_ptr)
151	INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_PACKET_ID );
152	INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_instruction);
153	INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_ERROR );
154	INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_EVENT_RESET_VAL );
155	INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_EVENT_RESET_ACK );
156
157	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
158
159	Time * _time = new Time();
160
161	/********************************************************
162	* Simulation - Begin
163	********************************************************/
164
165	// Initialisation
166
167	const uint32_t seed = 0;
168	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
169
170	srand(seed);
171
172	const int32_t percent_transaction_address = 75;
173	const int32_t percent_transaction_decod = 75;
174	const int32_t percent_transaction_event_reset = 10;
175	const int32_t percent_icache_hit = 100;
176	const int32_t icache_miss_penality = 10;
177
178	SC_START(0);
179	LABEL("Initialisation");
180
181	LABEL("Reset");
182	in_NRESET->write(0);
183	SC_START(5);
184	in_NRESET->write(1);
185
186	LABEL("Loop of Test");
187
188	list<Tgeneral_data_t> list_wait_decod;
189	list<entry_t> list_req_icache;
190
191	Tgeneral_data_t modulo_iberr = 23;
192	Tinstruction_t xor_inst = 0xdeadbeef;
193	Tgeneral_data_t address;
194	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
195	{
196	LABEL("Iteration %d",iteration);
197
198	int32_t nb_request_in = 64;
199	int32_t nb_request_out = 64;
200
201	address = 0x100;
202
203	list_wait_decod.clear();
204
205	while ((nb_request_in > 0) and
206	(nb_request_out > 0))
207	{
208	// =====
209	// ===== ADDRESS
210	// =====
211	in_ADDRESS_VAL ->write((nb_request_in > 0) and ((rand()%100)<percent_transaction_address));
212	in_ADDRESS_INSTRUCTION_ADDRESS ->write(address);
213	uint32_t nb_inst_enable = (rand() % _param->_nb_instruction);
214	for (uint32_t i=0; i<_param->_nb_instruction; i++)
215	in_ADDRESS_INSTRUCTION_ENABLE [i] ->write(i<=nb_inst_enable);
216	if (_param->_have_port_inst_ifetch_ptr)
217	in_ADDRESS_INST_IFETCH_PTR ->write(address%_param->_nb_instruction);
218	in_ADDRESS_BRANCH_STATE ->write(address%SIZE_BRANCH_STATE);
219	if (_param->_have_port_depth)
220	in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ->write(address%_param->_size_depth);
221
222	// =====
223	// ===== DECOD
224	// =====
225	for (uint32_t i=0; i<_param->_nb_instruction; i++)
226	in_DECOD_ACK [i]->write(0);
227	for (uint32_t i=0; i<_param->_nb_instruction; i++)
228	{
229	if ((rand()%100)>percent_transaction_decod)
230	break;
231	in_DECOD_ACK [i]->write(1);
232	}
233
234	// =====
235	// ===== ICACHE_RSP
236	// =====
237	Tcontrol_t icache_rsp_val = not list_req_icache.empty() and (list_req_icache.front()._cycle == 0);
238
239	// LABEL("Test ICACHE_RSP :");
240	// LABEL(" * list_req_icache.empty() : %d",list_req_icache.empty());
241	// if (not list_req_icache.empty())
242	// LABEL(" * list_req_icache.front()._cycle : %d",list_req_icache.front()._cycle);
243
244	in_ICACHE_RSP_VAL->write(icache_rsp_val);
245
246	if (icache_rsp_val)
247	{
248	for (uint32_t i=0; i<_param->_nb_instruction; i++)
249	in_ICACHE_RSP_INSTRUCTION [i]->write((list_req_icache.front()._addr + 4*i)^xor_inst);
250	in_ICACHE_RSP_PACKET_ID ->write(list_req_icache.front()._packet);
251	in_ICACHE_RSP_ERROR ->write(((list_req_icache.front()._addr % modulo_iberr)==0)?ICACHE_ERROR_BUS_ERROR:ICACHE_ERROR_NONE);
252	}
253
254	// =====
255	// ===== EVENT_RESET
256	// =====
257	in_EVENT_RESET_VAL->write((rand()%100)<percent_transaction_event_reset);
258
259	// ----------------------------------------------
260	// ----------------------------------------------
261	// ----------------------------------------------
262	SC_START(0);
263	// ----------------------------------------------
264	// ----------------------------------------------
265	// ----------------------------------------------
266
267	// =====
268	// ===== ADDRESS
269	// =====
270	if ( in_ADDRESS_VAL->read() and
271	out_ADDRESS_ACK->read())
272	{
273	LABEL("ADDRESS : transaction accepted");
274	LABEL(" * address : %.8x",address);
275
276	list_wait_decod.push_back(address);
277	// list_req_icache.insert(, entry_t((_param->_have_port_ifetch_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address));
278
279	uint32_t cycle = ((rand()%100)<percent_icache_hit)?1:icache_miss_penality;
280	LABEL(" * cycle : %d",cycle);
281
282	list<entry_t>::iterator it;
283	for (it=list_req_icache.begin(); it != list_req_icache.end(); it++)
284	if (cycle < it->_cycle)
285	break;
286
287	LABEL(" * list_req_icache : %d",list_req_icache.size());
288	list_req_icache.insert(it,entry_t(cycle,(_param->_have_port_ifetch_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address));
289	LABEL(" * list_req_icache : %d",list_req_icache.size());
290	address += 4*_param->_nb_instruction;
291	}
292
293	// =====
294	// ===== DECOD
295	// =====
296	bool have_decod_transaction = false;
297	uint32_t nb_decod_keep = 0;
298	for (uint32_t i=0; i<_param->_nb_instruction; i++)
299	{
300	if (out_DECOD_VAL [i]->read())
301	{
302	LABEL("DECOD_VAL [%d] ",i);
303	nb_decod_keep ++;
304
305	if (in_DECOD_ACK [i]->read())
306	{
307	LABEL("DECOD_ACK [%d] ",i);
308
309	have_decod_transaction = true;
310	nb_decod_keep --;
311
312	TEST(bool , list_wait_decod.empty() , false);
313	TEST(Tinstruction_t , out_DECOD_INSTRUCTION[i]->read(), (list_wait_decod.front()+4*i)^xor_inst);
314	}
315	}
316	}
317
318	if (have_decod_transaction)
319	{
320
321	Tgeneral_data_t addr = list_wait_decod.front();
322
323	LABEL("DECOD : transaction accepted");
324	LABEL(" * address : %.8x",addr);
325
326	TEST(Tgeneral_data_t ,out_DECOD_ADDRESS ->read(), addr);
327	TEST(Tbranch_state_t ,out_DECOD_BRANCH_STATE ->read(),addr%SIZE_BRANCH_STATE);
328	if (_param->_have_port_inst_ifetch_ptr)
329	TEST(Tinst_ifetch_ptr_t,out_DECOD_INST_IFETCH_PTR ->read(),addr%_param->_nb_instruction);
330	if (_param->_have_port_depth)
331	TEST(Tprediction_ptr_t ,out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(),addr%_param->_size_depth);
332	if ((addr % modulo_iberr) == 0)
333	TEST(Texception_t ,out_DECOD_EXCEPTION ->read(),EXCEPTION_IFETCH_BUS_ERROR);
334	else
335	TEST(Texception_t ,out_DECOD_EXCEPTION ->read(),EXCEPTION_IFETCH_NONE );
336
337	// all is decod
338	LABEL(" * nb_decod_keep : %d",nb_decod_keep);
339	if (nb_decod_keep == 0)
340	{
341	LABEL(" * decod all bundle");
342	list_wait_decod.pop_front();
343	nb_request_out --;
344	}
345	}
346
347	// =====
348	// ===== ICACHE_RSP
349	// =====
350	if ( in_ICACHE_RSP_VAL->read() and
351	out_ICACHE_RSP_ACK->read())
352	{
353	LABEL("ICACHE_RSP : transaction accepted");
354	LABEL(" * address : %.8x",list_req_icache.front()._addr);
355	LABEL(" * list_req_icache : %d",list_req_icache.size());
356	list_req_icache.pop_front();
357	LABEL(" * list_req_icache : %d",list_req_icache.size());
358
359	}
360
361	// =====
362	// ===== EVENT_RESET
363	// =====
364	if ( in_EVENT_RESET_VAL->read() and
365	out_EVENT_RESET_ACK->read() )
366	{
367	LABEL("EVENT_RESET : transaction accepted");
368	list_wait_decod.clear();
369	}
370
371	SC_START(1);
372
373	for (list<entry_t>::iterator it=list_req_icache.begin(); it != list_req_icache.end(); it++)
374	{
375	LABEL("ICACHE : %d %d %.8x",it->_cycle, it->_packet, it->_addr);
376	if (it->_cycle > 0)
377	it->_cycle --;
378	}
379	}
380	}
381
382	/********************************************************
383	* Simulation - End
384	********************************************************/
385
386	TEST_OK ("End of Simulation");
387	delete _time;
388
389	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
390
391	delete in_CLOCK;
392	delete in_NRESET;
393	delete in_ADDRESS_VAL ;
394	delete out_ADDRESS_ACK ;
395	delete out_ADDRESS_IFETCH_QUEUE_ID ;
396	delete [] in_ADDRESS_INSTRUCTION_ENABLE ;
397	delete in_ADDRESS_INSTRUCTION_ADDRESS ;
398	delete in_ADDRESS_INST_IFETCH_PTR ;
399	delete in_ADDRESS_BRANCH_STATE ;
400	delete in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;
401	delete [] out_DECOD_VAL ;
402	delete [] in_DECOD_ACK ;
403	delete [] out_DECOD_INSTRUCTION ;
404	delete out_DECOD_ADDRESS ;
405	delete out_DECOD_INST_IFETCH_PTR ;
406	delete out_DECOD_BRANCH_STATE ;
407	delete out_DECOD_BRANCH_UPDATE_PREDICTION_ID ;
408	delete out_DECOD_EXCEPTION ;
409	delete in_ICACHE_RSP_VAL ;
410	delete out_ICACHE_RSP_ACK ;
411	delete in_ICACHE_RSP_PACKET_ID ;
412	delete [] in_ICACHE_RSP_INSTRUCTION ;
413	delete in_ICACHE_RSP_ERROR ;
414	delete in_EVENT_RESET_VAL ;
415	delete out_EVENT_RESET_ACK ;
416
417	#endif
418
419	delete _Ifetch_queue;
420	#ifdef STATISTICS
421	delete _parameters_statistics;
422	#endif
423	}

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