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test.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 15 years ago
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1	/*
2	* $Id: test.cpp 88 2008-12-10 18:31:39Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 1024
10	#define CYCLE_MAX (128*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Common/include/BitManipulation.h"
15	#include "Behavioural/include/Allocation.h"
16	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/include/test_BTB.h"
17
18	void test (string name,
19	morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters * _param)
20	{
21	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
22
23	#ifdef STATISTICS
24	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
25	#endif
26
27	Tusage_t _usage = USE_ALL;
28
29	// _usage = usage_unset(_usage,USE_SYSTEMC );
30	// _usage = usage_unset(_usage,USE_VHDL );
31	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
32	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
33	// _usage = usage_unset(_usage,USE_POSITION );
34	// _usage = usage_unset(_usage,USE_STATISTICS );
35	// _usage = usage_unset(_usage,USE_INFORMATION );
36
37	Branch_Target_Buffer_Register * _Branch_Target_Buffer_Register = new Branch_Target_Buffer_Register
38	(name.c_str(),
39	#ifdef STATISTICS
40	_parameters_statistics,
41	#endif
42	_param,
43	_usage);
44
45	#ifdef SYSTEMC
46	/*********************************************************************
47	* Déclarations des signaux
48	*********************************************************************/
49	string rename;
50
51	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
52	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
53
54	ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_predict);
55	ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_predict);
56	ALLOC1_SC_SIGNAL( in_PREDICT_CONTEXT_ID ," in_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_predict);
57	ALLOC1_SC_SIGNAL( in_PREDICT_ADDRESS ," in_PREDICT_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_predict);
58	ALLOC2_SC_SIGNAL(out_PREDICT_HIT ,"out_PREDICT_HIT ",Tcontrol_t ,_param->_nb_inst_predict,_param->_associativity);
59	ALLOC2_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,"out_PREDICT_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_predict,_param->_associativity);
60	ALLOC2_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,"out_PREDICT_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_predict,_param->_associativity);
61	ALLOC2_SC_SIGNAL(out_PREDICT_CONDITION ,"out_PREDICT_CONDITION ",Tbranch_condition_t,_param->_nb_inst_predict,_param->_associativity);
62	ALLOC2_SC_SIGNAL(out_PREDICT_LAST_TAKE ,"out_PREDICT_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_predict,_param->_associativity);
63	ALLOC2_SC_SIGNAL(out_PREDICT_IS_ACCURATE ,"out_PREDICT_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_predict,_param->_associativity);
64	ALLOC1_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
65	ALLOC1_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
66	ALLOC1_SC_SIGNAL(out_DECOD_HIT ,"out_DECOD_HIT ",Tcontrol_t ,_param->_nb_inst_decod);
67	ALLOC1_SC_SIGNAL(out_DECOD_HIT_INDEX ,"out_DECOD_HIT_INDEX ",Tptr_t ,_param->_nb_inst_decod);
68	ALLOC1_SC_SIGNAL( in_DECOD_VICTIM ," in_DECOD_VICTIM ",Tptr_t ,_param->_nb_inst_decod);
69	ALLOC1_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
70	ALLOC1_SC_SIGNAL( in_DECOD_ADDRESS_SRC ," in_DECOD_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_decod);
71	ALLOC1_SC_SIGNAL( in_DECOD_ADDRESS_DEST ," in_DECOD_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_decod);
72	ALLOC1_SC_SIGNAL( in_DECOD_CONDITION ," in_DECOD_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
73	ALLOC1_SC_SIGNAL( in_DECOD_LAST_TAKE ," in_DECOD_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_decod);
74	ALLOC1_SC_SIGNAL( in_DECOD_MISS_PREDICTION ," in_DECOD_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_decod);
75	ALLOC1_SC_SIGNAL( in_DECOD_IS_ACCURATE ," in_DECOD_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_decod);
76	ALLOC1_SC_SIGNAL( in_UPDATE_VAL ," in_UPDATE_VAL ",Tcontrol_t ,_param->_nb_inst_update);
77	ALLOC1_SC_SIGNAL(out_UPDATE_ACK ,"out_UPDATE_ACK ",Tcontrol_t ,_param->_nb_inst_update);
78	ALLOC1_SC_SIGNAL(out_UPDATE_HIT ,"out_UPDATE_HIT ",Tcontrol_t ,_param->_nb_inst_update);
79	ALLOC1_SC_SIGNAL(out_UPDATE_HIT_INDEX ,"out_UPDATE_HIT_INDEX ",Tptr_t ,_param->_nb_inst_update);
80	ALLOC1_SC_SIGNAL( in_UPDATE_VICTIM ," in_UPDATE_VICTIM ",Tptr_t ,_param->_nb_inst_update);
81	ALLOC1_SC_SIGNAL( in_UPDATE_CONTEXT_ID ," in_UPDATE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_update);
82	ALLOC1_SC_SIGNAL( in_UPDATE_ADDRESS_SRC ," in_UPDATE_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_update);
83	ALLOC1_SC_SIGNAL( in_UPDATE_ADDRESS_DEST ," in_UPDATE_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_update);
84	ALLOC1_SC_SIGNAL( in_UPDATE_CONDITION ," in_UPDATE_CONDITION ",Tbranch_condition_t,_param->_nb_inst_update);
85	ALLOC1_SC_SIGNAL( in_UPDATE_LAST_TAKE ," in_UPDATE_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_update);
86	ALLOC1_SC_SIGNAL( in_UPDATE_MISS_PREDICTION," in_UPDATE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_update);
87
88	/********************************************************
89	* Instanciation
90	********************************************************/
91
92	msg(_("<%s> : Instanciation of _Branch_Target_Buffer_Register.\n"),name.c_str());
93
94	((_Branch_Target_Buffer_Register->in_CLOCK)) ((in_CLOCK));
95	((_Branch_Target_Buffer_Register->in_NRESET)) ((in_NRESET));
96
97	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_PREDICT_VAL ,_param->_nb_inst_predict);
98	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_PREDICT_ACK ,_param->_nb_inst_predict);
99	if (_param->_have_port_context_id)
100	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict);
101	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_PREDICT_ADDRESS ,_param->_nb_inst_predict);
102	INSTANCE2_SC_SIGNAL(_Branch_Target_Buffer_Register,out_PREDICT_HIT ,_param->_nb_inst_predict,_param->_associativity);
103	INSTANCE2_SC_SIGNAL(_Branch_Target_Buffer_Register,out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_predict,_param->_associativity);
104	INSTANCE2_SC_SIGNAL(_Branch_Target_Buffer_Register,out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_predict,_param->_associativity);
105	INSTANCE2_SC_SIGNAL(_Branch_Target_Buffer_Register,out_PREDICT_CONDITION ,_param->_nb_inst_predict,_param->_associativity);
106	INSTANCE2_SC_SIGNAL(_Branch_Target_Buffer_Register,out_PREDICT_LAST_TAKE ,_param->_nb_inst_predict,_param->_associativity);
107	INSTANCE2_SC_SIGNAL(_Branch_Target_Buffer_Register,out_PREDICT_IS_ACCURATE ,_param->_nb_inst_predict,_param->_associativity);
108
109	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_VAL ,_param->_nb_inst_decod);
110	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_DECOD_ACK ,_param->_nb_inst_decod);
111	if (_param->_have_port_victim)
112	{
113	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_DECOD_HIT ,_param->_nb_inst_decod);
114	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_DECOD_HIT_INDEX ,_param->_nb_inst_decod);
115	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_VICTIM ,_param->_nb_inst_decod);
116	}
117	if (_param->_have_port_context_id)
118	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
119	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_ADDRESS_SRC ,_param->_nb_inst_decod);
120	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_ADDRESS_DEST ,_param->_nb_inst_decod);
121	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_CONDITION ,_param->_nb_inst_decod);
122	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_LAST_TAKE ,_param->_nb_inst_decod);
123	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_MISS_PREDICTION ,_param->_nb_inst_decod);
124	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod);
125
126	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_VAL ,_param->_nb_inst_update);
127	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_UPDATE_ACK ,_param->_nb_inst_update);
128	if (_param->_have_port_victim)
129	{
130	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_UPDATE_HIT ,_param->_nb_inst_update);
131	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_UPDATE_HIT_INDEX ,_param->_nb_inst_update);
132	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_VICTIM ,_param->_nb_inst_update);
133	}
134	if (_param->_have_port_context_id)
135	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_CONTEXT_ID ,_param->_nb_inst_update);
136	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_ADDRESS_SRC ,_param->_nb_inst_update);
137	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_ADDRESS_DEST ,_param->_nb_inst_update);
138	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_CONDITION ,_param->_nb_inst_update);
139	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_LAST_TAKE ,_param->_nb_inst_update);
140	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_MISS_PREDICTION,_param->_nb_inst_update);
141
142	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
143
144	Time * _time = new Time();
145
146	/********************************************************
147	* Simulation - Begin
148	********************************************************/
149
150	// Initialisation
151
152	const uint32_t seed = 0;
153	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
154
155	srand(seed);
156
157	const int32_t percent_transaction_predict = 75;
158	const int32_t percent_transaction_decod = 75;
159	const int32_t percent_transaction_update = 75;
160
161	uint32_t num_index = 0;
162	entry_t tab_old [_param->_associativity];
163	entry_t tab [_param->_associativity];
164
165	for (uint32_t i=0; i<_param->_associativity; i++)
166	tab[i]._val = false;
167
168	SC_START(0);
169	LABEL("Initialisation");
170
171	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
172	in_PREDICT_VAL [i]->write(0);
173	for (uint32_t i=0; i<_param->_nb_inst_decod ; i++)
174	in_DECOD_VAL [i]->write(0);
175	for (uint32_t i=0; i<_param->_nb_inst_update ; i++)
176	in_UPDATE_VAL [i]->write(0);
177
178	LABEL("Reset");
179	in_NRESET->write(0);
180	SC_START(5);
181	in_NRESET->write(1);
182
183	LABEL("Loop of Test");
184
185	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
186	{
187	LABEL("Iteration %d",iteration);
188
189	for (uint32_t j=0; j<_param->_associativity; j++)
190	tab[j].print();
191
192	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
193	{
194	Tgeneral_data_t addr;
195	uint32_t j = rand()%_param->_associativity;
196
197	if ( ((rand()%100)<percent_transaction_predict) and
198	tab [j]._val)
199	addr = tab [j]._address_src;
200	else
201	addr = gen_addr(_param, num_index);
202
203	in_PREDICT_VAL [i]->write((rand()%100)<percent_transaction_predict);
204	in_PREDICT_CONTEXT_ID [i]->write(rand()%_param->_nb_context);
205	in_PREDICT_ADDRESS [i]->write(addr);
206	}
207
208	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
209	{
210	Tgeneral_data_t addr = gen_addr(_param, num_index);
211
212	in_DECOD_VAL [i]->write((rand()%100)<percent_transaction_decod);
213	in_DECOD_VICTIM [i]->write(rand()%_param->_associativity);
214	in_DECOD_CONTEXT_ID [i]->write(rand()%_param->_nb_context);
215	in_DECOD_ADDRESS_SRC [i]->write( addr);
216	in_DECOD_ADDRESS_DEST [i]->write(~addr);
217	in_DECOD_CONDITION [i]->write((addr&1)?BRANCH_CONDITION_FLAG_SET:BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK);
218	in_DECOD_LAST_TAKE [i]->write(rand()%2);
219	in_DECOD_MISS_PREDICTION [i]->write(rand()%2);
220	in_DECOD_IS_ACCURATE [i]->write(rand()%2);
221	}
222
223	for (uint32_t i=0; i<_param->_nb_inst_update; i++)
224	{
225	Tgeneral_data_t addr = gen_addr(_param, num_index);
226
227	in_UPDATE_VAL [i]->write((rand()%100)<percent_transaction_update);
228	in_UPDATE_VICTIM [i]->write(rand()%_param->_associativity);
229	in_UPDATE_CONTEXT_ID [i]->write(rand()%_param->_nb_context);
230	in_UPDATE_ADDRESS_SRC [i]->write( addr);
231	in_UPDATE_ADDRESS_DEST [i]->write(~addr);
232	in_UPDATE_CONDITION [i]->write((addr&1)?BRANCH_CONDITION_FLAG_SET:BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK);
233	in_UPDATE_LAST_TAKE [i]->write(rand()%2);
234	in_UPDATE_MISS_PREDICTION [i]->write(rand()%2);
235	}
236
237	SC_START(0);
238
239	for (uint32_t i=0; i<_param->_associativity; i++)
240	tab_old [i] = tab [i];
241
242	for (uint32_t i=0; i<_param->_nb_inst_predict ; i++)
243	if (in_PREDICT_VAL [i]->read() and out_PREDICT_ACK [i]->read())
244	{
245	LABEL("PREDICT [%d] : Transaction accepted",i);
246	LABEL(" * context : %d" ,in_PREDICT_CONTEXT_ID [i]->read());
247	LABEL(" * address : %.8x",in_PREDICT_ADDRESS [i]->read());
248
249	Tcontext_t ctxt = in_PREDICT_CONTEXT_ID [i]->read();
250	Tgeneral_data_t addr = in_PREDICT_ADDRESS [i]->read();
251
252	for (uint32_t j=0; j<_param->_associativity; j++)
253	{
254	LABEL(" * [%d]",j);
255
256	bool hit = tab_old[j].hit(_param, addr, ctxt);
257	TEST(Tcontrol_t , out_PREDICT_HIT [i][j]->read(), hit);
258
259	if (tab_old[j]._val)
260	{
261	Tgeneral_data_t addr_src = tab_old[j]._address_src;
262
263	TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_SRC [i][j]->read(), addr_src);
264	TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_DEST [i][j]->read(), ~addr_src);
265	TEST(Tbranch_condition_t, out_PREDICT_CONDITION [i][j]->read(), ((addr_src&1)?BRANCH_CONDITION_FLAG_SET:BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK));
266	TEST(Tcontrol_t , out_PREDICT_LAST_TAKE [i][j]->read(), tab_old[j]._last_take);
267	// TEST(Tcontrol_t , out_PREDICT_IS_ACCURATE [i][j]->read(), );
268	}
269	}
270	}
271
272	for (uint32_t i=0; i<_param->_nb_inst_decod ; i++)
273	if (in_DECOD_VAL [i]->read() and out_DECOD_ACK [i]->read())
274	{
275	LABEL("DECOD [%d] : Transaction accepted",i);
276	LABEL(" * context : %d" ,in_DECOD_CONTEXT_ID [i]->read());
277	LABEL(" * address_src : %.8x",in_DECOD_ADDRESS_SRC [i]->read());
278
279	bool hit = false;
280
281	Tptr_t k;
282	for (k=0; k<_param->_associativity; k++)
283	{
284	hit \|= ((tab_old[k]._val == 1) and
285	(tab_old[k]._context == in_DECOD_CONTEXT_ID [i]->read()) and
286	(tab_old[k]._address_src == in_DECOD_ADDRESS_SRC [i]->read()));
287
288	if (hit)
289	break;
290	}
291
292	if (not hit)
293	{
294	k = in_DECOD_VICTIM [i]->read();
295	LABEL(" * miss");
296	LABEL(" * victim : %d",k);
297
298	tab[k]._val = 1;
299	tab[k]._context = in_DECOD_CONTEXT_ID [i]->read();
300	tab[k]._address_src = in_DECOD_ADDRESS_SRC [i]->read();
301	tab[k]._address_dest_val = in_DECOD_CONDITION [i]->read() == BRANCH_CONDITION_FLAG_SET;
302	tab[k]._address_dest = in_DECOD_ADDRESS_DEST[i]->read();
303	tab[k]._condition = in_DECOD_CONDITION [i]->read();
304	tab[k]._last_take = in_DECOD_LAST_TAKE [i]->read();
305	tab[k]._accurate =(in_DECOD_IS_ACCURATE [i]->read())?_param->_first_accurate_if_hit:_param->_first_accurate_if_miss;
306	}
307	else
308	{
309	LABEL(" * hit");
310	}
311
312	if (_param->_have_port_victim)
313	{
314	TEST(Tcontrol_t, out_DECOD_HIT [i]->read(), hit);
315	if (hit)
316	TEST(Tptr_t , out_DECOD_HIT_INDEX [i]->read(), k);
317	}
318	}
319
320	for (uint32_t i=0; i<_param->_nb_inst_update ; i++)
321	if (in_UPDATE_VAL [i]->read() and out_UPDATE_ACK [i]->read())
322	{
323	LABEL("UPDATE [%d] : Transaction accepted",i);
324	LABEL(" * context : %d" ,in_UPDATE_CONTEXT_ID [i]->read());
325	LABEL(" * address_src : %.8x",in_UPDATE_ADDRESS_SRC [i]->read());
326
327	bool hit = false;
328
329	Tptr_t k;
330	for (k=0; k<_param->_associativity; k++)
331	{
332	hit \|= ((tab_old[k]._val == 1) and
333	(tab_old[k]._context == in_UPDATE_CONTEXT_ID [i]->read()) and
334	(tab_old[k]._address_src == in_UPDATE_ADDRESS_SRC [i]->read()));
335	if (hit)
336	break;
337	}
338
339	if (not hit)
340	{
341	k = in_UPDATE_VICTIM [i]->read();
342
343	LABEL(" * miss");
344	LABEL(" * victim : %d",k);
345
346	tab[k]._val = 1;
347	tab[k]._context = in_UPDATE_CONTEXT_ID [i]->read();
348	tab[k]._address_src = in_UPDATE_ADDRESS_SRC [i]->read();
349	tab[k]._address_dest_val = 1;
350	tab[k]._address_dest = in_UPDATE_ADDRESS_DEST[i]->read();
351	tab[k]._condition = in_UPDATE_CONDITION [i]->read();
352	tab[k]._last_take = in_UPDATE_LAST_TAKE [i]->read();
353	tab[k]._accurate = (in_UPDATE_MISS_PREDICTION [i]->read())?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit;
354	}
355	else
356	{
357	LABEL(" * hit");
358	LABEL(" * update : %d",k);
359
360	tab[k]._val = 1;
361	tab[k]._context = in_UPDATE_CONTEXT_ID [i]->read();
362	tab[k]._address_src = in_UPDATE_ADDRESS_SRC [i]->read();
363	tab[k]._address_dest_val = 1;
364	tab[k]._address_dest = in_UPDATE_ADDRESS_DEST[i]->read();
365	tab[k]._condition = in_UPDATE_CONDITION [i]->read();
366	tab[k]._last_take = in_UPDATE_LAST_TAKE [i]->read();
367
368
369	Tcounter_t accurate_old = tab[k]._accurate;
370	// hit : increase accurate
371	// miss : decrease accurate
372	Tcounter_t accurate_new = (in_UPDATE_MISS_PREDICTION [i]->read())?((accurate_old>0)?(accurate_old-1):accurate_old):((accurate_old<_param->_accurate_max)?(accurate_old+1):accurate_old);
373
374	// test if accurate go to the threshold
375	if ((accurate_old >= _param->_accurate_limit) and
376	(accurate_new < _param->_accurate_limit))
377	accurate_new = 0;
378
379
380	tab[k]._accurate = accurate_new;
381	}
382
383	if (_param->_have_port_victim)
384	{
385	TEST(Tcontrol_t, out_UPDATE_HIT [i]->read(), hit);
386	if (hit)
387	TEST(Tptr_t , out_UPDATE_HIT_INDEX [i]->read(), k);
388	}
389	}
390
391	SC_START(1);
392	}
393
394	/********************************************************
395	* Simulation - End
396	********************************************************/
397
398	TEST_OK ("End of Simulation");
399	delete _time;
400
401	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
402
403	delete in_CLOCK;
404	delete in_NRESET;
405
406	delete [] in_PREDICT_VAL ;
407	delete [] out_PREDICT_ACK ;
408	delete [] in_PREDICT_CONTEXT_ID ;
409	delete [] in_PREDICT_ADDRESS ;
410	delete [] out_PREDICT_HIT ;
411	delete [] out_PREDICT_ADDRESS_SRC ;
412	delete [] out_PREDICT_ADDRESS_DEST ;
413	delete [] out_PREDICT_CONDITION ;
414	delete [] out_PREDICT_LAST_TAKE ;
415	delete [] out_PREDICT_IS_ACCURATE ;
416	delete [] in_DECOD_VAL ;
417	delete [] out_DECOD_ACK ;
418	delete [] out_DECOD_HIT ;
419	delete [] out_DECOD_HIT_INDEX ;
420	delete [] in_DECOD_VICTIM ;
421	delete [] in_DECOD_CONTEXT_ID ;
422	delete [] in_DECOD_ADDRESS_SRC ;
423	delete [] in_DECOD_ADDRESS_DEST ;
424	delete [] in_DECOD_CONDITION ;
425	delete [] in_DECOD_LAST_TAKE ;
426	delete [] in_DECOD_MISS_PREDICTION ;
427	delete [] in_DECOD_IS_ACCURATE ;
428	delete [] in_UPDATE_VAL ;
429	delete [] out_UPDATE_ACK ;
430	delete [] out_UPDATE_HIT ;
431	delete [] out_UPDATE_HIT_INDEX ;
432	delete [] in_UPDATE_VICTIM ;
433	delete [] in_UPDATE_CONTEXT_ID ;
434	delete [] in_UPDATE_ADDRESS_SRC ;
435	delete [] in_UPDATE_ADDRESS_DEST ;
436	delete [] in_UPDATE_CONDITION ;
437	delete [] in_UPDATE_LAST_TAKE ;
438	delete [] in_UPDATE_MISS_PREDICTION;
439
440	#endif
441
442	delete _Branch_Target_Buffer_Register;
443	#ifdef STATISTICS
444	delete _parameters_statistics;
445	#endif
446	}

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/test.cpp @ 88

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