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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp @ 98

Last change on this file since 98 was 98, checked in by rosiere, 15 years ago
1) Fix bug (read unit, RAT -> write in R0, SPR desallocation ...) 2) Change VHDL Execute_queue -> use Generic/Queue? 3) Complete document on VHDL generation 4) Add soc test
Property svn:keywords set to `Id`
File size: 23.7 KB

Line
1	/*
2	* $Id: test.cpp 98 2008-12-31 10:18:08Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 1
10	#define CYCLE_MAX 1000000
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Behavioural/include/Allocation.h"
15
16	void test (string name,
17	morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::Parameters * _param)
18	{
19	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
20
21	#ifdef STATISTICS
22	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
23	#endif
24
25	Tusage_t _usage = USE_ALL;
26
27	// _usage = usage_unset(_usage,USE_SYSTEMC );
28	// _usage = usage_unset(_usage,USE_VHDL );
29	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
30	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
31	// _usage = usage_unset(_usage,USE_POSITION );
32	// _usage = usage_unset(_usage,USE_STATISTICS );
33	// _usage = usage_unset(_usage,USE_INFORMATION );
34
35	Prediction_unit * _Prediction_unit = new Prediction_unit
36	(name.c_str(),
37	#ifdef STATISTICS
38	_parameters_statistics,
39	#endif
40	_param,
41	_usage);
42
43	#ifdef SYSTEMC
44	/*********************************************************************
45	* Déclarations des signaux
46	*********************************************************************/
47	string rename;
48
49	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
50	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
51
52
53	ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t ,_param->_nb_context);
54	ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t ,_param->_nb_context);
55	ALLOC1_SC_SIGNAL( in_PREDICT_PC_PREVIOUS ," in_PREDICT_PC_PREVIOUS ",Taddress_t ,_param->_nb_context);
56	ALLOC1_SC_SIGNAL( in_PREDICT_PC_CURRENT ," in_PREDICT_PC_CURRENT ",Taddress_t ,_param->_nb_context);
57	ALLOC1_SC_SIGNAL( in_PREDICT_PC_CURRENT_IS_DS_TAKE ," in_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context);
58	ALLOC1_SC_SIGNAL(out_PREDICT_PC_NEXT ,"out_PREDICT_PC_NEXT ",Taddress_t ,_param->_nb_context);
59	ALLOC1_SC_SIGNAL(out_PREDICT_PC_NEXT_IS_DS_TAKE ,"out_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context);
60	ALLOC2_SC_SIGNAL(out_PREDICT_INSTRUCTION_ENABLE ,"out_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_context,_param->_nb_instruction[it1]);
61	ALLOC1_SC_SIGNAL(out_PREDICT_INST_IFETCH_PTR ,"out_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ,_param->_nb_context);
62	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,"out_PREDICT_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_context);
63	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"out_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ,_param->_nb_context);
64
65	ALLOC2_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
66	ALLOC2_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
67	ALLOC2_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
68	ALLOC2_SC_SIGNAL( in_DECOD_MATCH_INST_IFETCH_PTR ," in_DECOD_MATCH_INST_IFETCH_PTR ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
69	ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_STATE ," in_DECOD_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
70	ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_UPDATE_PREDICTION_ID ," in_DECOD_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
71	ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_CONDITION ," in_DECOD_BRANCH_CONDITION ",Tbranch_condition_t,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
72	ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_DIRECTION ," in_DECOD_BRANCH_DIRECTION ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
73	ALLOC2_SC_SIGNAL( in_DECOD_ADDRESS_SRC ," in_DECOD_ADDRESS_SRC ",Taddress_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
74	ALLOC2_SC_SIGNAL( in_DECOD_ADDRESS_DEST ," in_DECOD_ADDRESS_DEST ",Taddress_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
75
76	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
77	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
78	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
79	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
80	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete);
81	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
82	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION ,"out_BRANCH_COMPLETE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_branch_complete);
83	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,"out_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
84	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,"out_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
85	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,"out_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
86
87	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,"out_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
88	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ACK ," in_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
89	//ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,"out_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
90	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,"out_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
91	//ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,"out_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context);
92	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
93	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,"out_BRANCH_EVENT_ADDRESS_DEST_VAL ",Tcontrol_t ,_param->_nb_context);
94	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
95
96	ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
97	ALLOC1_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
98	ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context);
99	ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
100
101	ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context);
102	ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context);
103	ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context);
104
105	/********************************************************
106	* Instanciation
107	********************************************************/
108
109	msg(_("<%s> : Instanciation of _Prediction_unit.\n"),name.c_str());
110
111	((_Prediction_unit->in_CLOCK)) ((in_CLOCK));
112	((_Prediction_unit->in_NRESET)) ((in_NRESET));
113
114	INSTANCE1_SC_SIGNAL(_Prediction_unit, in_PREDICT_VAL ,_param->_nb_context);
115	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_ACK ,_param->_nb_context);
116	INSTANCE1_SC_SIGNAL(_Prediction_unit, in_PREDICT_PC_PREVIOUS ,_param->_nb_context);
117	INSTANCE1_SC_SIGNAL(_Prediction_unit, in_PREDICT_PC_CURRENT ,_param->_nb_context);
118	INSTANCE1_SC_SIGNAL(_Prediction_unit, in_PREDICT_PC_CURRENT_IS_DS_TAKE ,_param->_nb_context);
119	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_PC_NEXT ,_param->_nb_context);
120	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_PC_NEXT_IS_DS_TAKE ,_param->_nb_context);
121	INSTANCE2_SC_SIGNAL(_Prediction_unit,out_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_context,_param->_nb_instruction[it1]);
122	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_BRANCH_STATE ,_param->_nb_context);
123	if (_param->_have_port_inst_ifetch_ptr)
124	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_INST_IFETCH_PTR ,_param->_nb_context);
125	if (_param->_have_port_depth)
126	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_context);
127	INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_VAL ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
128	INSTANCE2_SC_SIGNAL(_Prediction_unit,out_DECOD_ACK ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
129	if (_param->_have_port_context_id)
130	INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
131	INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_MATCH_INST_IFETCH_PTR ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
132	INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_BRANCH_STATE ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
133	if (_param->_have_port_depth)
134	INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_BRANCH_UPDATE_PREDICTION_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
135	INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_BRANCH_CONDITION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
136	INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_BRANCH_DIRECTION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
137	INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
138	INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
139
140	INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
141	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
142	if (_param->_have_port_context_id)
143	INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
144	if (_param->_have_port_depth)
145	INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
146	INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
147	INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete);
148	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete);
149	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
150	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
151	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
152
153	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_VAL ,_param->_nb_context);
154	INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_EVENT_ACK ,_param->_nb_context);
155	//if (_param->_have_port_context_id)
156	//INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
157	if (_param->_have_port_depth)
158	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_DEPTH ,_param->_nb_context);
159	//INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context);
160	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
161	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context);
162	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
163
164	INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_VAL ,_param->_nb_context);
165	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_EVENT_ACK ,_param->_nb_context);
166	INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_TYPE ,_param->_nb_context);
167	if (_param->_have_port_depth)
168	{
169	INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_DEPTH ,_param->_nb_context);
170	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_CURRENT ,_param->_nb_context);
171	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_MIN ,_param->_nb_context);
172	}
173	INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_MAX ,_param->_nb_context);
174
175	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
176
177	Time * _time = new Time();
178
179	/********************************************************
180	* Simulation - Begin
181	********************************************************/
182
183	// Initialisation
184
185	const uint32_t seed = 0;
186	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
187
188	const int32_t percent_transaction_predict = 80;
189	const int32_t percent_transaction_decod = 80;
190	const int32_t percent_transaction_branch_complete = 80;
191	const int32_t percent_transaction_branch_event = 80;
192
193	srand(seed);
194
195	uint32_t test1 = 1024; // TEST 1 : instruction without branch
196	uint32_t test2 = 1024; // TEST 2 : sequence : 1 branch, 1 delayed slot
197
198	SC_START(0);
199	LABEL("Initialisation");
200
201	for (uint32_t i=0; i<_param->_nb_context; ++i)
202	{
203	in_PREDICT_VAL [i]->write(0);
204	in_BRANCH_EVENT_ACK [i]->write(0);
205	}
206
207	for (uint32_t i=0; i<_param->_nb_decod_unit;++i)
208	for (uint32_t j=0; j<_param->_nb_inst_decod[i]; ++j)
209	{
210	in_DECOD_VAL [i][j]->write(0);
211	}
212
213	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
214	{
215	in_BRANCH_COMPLETE_VAL [i]->write(0);
216	}
217
218	LABEL("Reset");
219	in_NRESET->write(0);
220	SC_START(5);
221	in_NRESET->write(1);
222
223	for (uint32_t i=0; i<_param->_nb_context; ++i)
224	{
225	// TEST(Tcontrol_t,out_PREDICT_ACK [i]->read(),1); // Accept new request
226	TEST(Tcontrol_t,out_BRANCH_EVENT_VAL [i]->read(),0);
227	TEST(Tdepth_t ,out_DEPTH_CURRENT [i]->read(),0);
228	TEST(Tdepth_t ,out_DEPTH_MIN [i]->read(),0);
229	TEST(Tdepth_t ,out_DEPTH_MAX [i]->read(),0);
230	}
231
232	for (uint32_t i=0; i<_param->_nb_decod_unit;++i)
233	for (uint32_t j=0; j<_param->_nb_inst_decod[i]; ++j)
234	{
235	TEST(Tcontrol_t,out_DECOD_ACK [i][j]->read(),0); // No decod instruction
236	}
237
238	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
239	{
240	TEST(Tcontrol_t,out_BRANCH_COMPLETE_ACK [i]->read(),1); // Accept new branch_complete
241	}
242
243	LABEL("Loop of Test");
244
245	Taddress_t PC_PREVIOUS [_param->_nb_context];
246	Taddress_t PC_CURRENT [_param->_nb_context];
247	Tcontrol_t PC_CURRENT_IS_DS_TAKE [_param->_nb_context];
248
249	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
250	{
251	LABEL("Iteration %d",iteration);
252
253	// TEST 1 : instruction without branch
254	for (uint32_t test=0; test<test1; ++test)
255	{
256	for (uint32_t i=0; i<_param->_nb_context; ++i)
257	{
258	PC_CURRENT [i] = (0x100000>>2);
259	PC_CURRENT_IS_DS_TAKE [i] = 0;
260	PC_PREVIOUS [i] = PC_CURRENT[i]-1;
261	}
262
263	for (uint32_t i=0; i<_param->_nb_context; ++i)
264	{
265	in_PREDICT_VAL [i]->write((rand()%100)<percent_transaction_predict);
266	in_PREDICT_PC_PREVIOUS [i]->write(PC_PREVIOUS [i]);
267	in_PREDICT_PC_CURRENT [i]->write(PC_CURRENT [i]);
268	in_PREDICT_PC_CURRENT_IS_DS_TAKE [i]->write(PC_CURRENT_IS_DS_TAKE[i]);
269	}
270
271	SC_START(1);
272
273	for (uint32_t i=0; i<_param->_nb_context; ++i)
274	// Test if transaction
275	if (in_PREDICT_VAL [i]->read() and out_PREDICT_ACK [i]->read())
276	{
277	TEST(Taddress_t ,out_PREDICT_PC_NEXT [i]->read(),PC_CURRENT[i]+_param->_nb_instruction[i]);
278	TEST(Tcontrol_t ,out_PREDICT_PC_NEXT_IS_DS_TAKE [i]->read(),0);
279	for (uint32_t j=0; j<_param->_nb_instruction[i]; ++j)
280	TEST(Tcontrol_t ,out_PREDICT_INSTRUCTION_ENABLE [i][j]->read(),1);
281	TEST(Tinst_ifetch_ptr_t,out_PREDICT_INST_IFETCH_PTR [i]->read(),0);
282	TEST(Tbranch_state_t ,out_PREDICT_BRANCH_STATE [i]->read(),BRANCH_STATE_NONE);
283	TEST(Tprediction_ptr_t ,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]->read(),0);
284
285	PC_PREVIOUS [i] = PC_CURRENT [i];
286	PC_CURRENT [i] = out_PREDICT_PC_NEXT [i]->read();
287	PC_CURRENT_IS_DS_TAKE [i] = out_PREDICT_PC_NEXT_IS_DS_TAKE [i]->read();
288	}
289
290	// Test another output
291	for (uint32_t i=0; i<_param->_nb_context; ++i)
292	{
293	TEST(Tcontrol_t,out_BRANCH_EVENT_VAL [i]->read(),0);
294	TEST(Tdepth_t ,out_DEPTH_CURRENT [i]->read(),0);
295	TEST(Tdepth_t ,out_DEPTH_MIN [i]->read(),0);
296	TEST(Tdepth_t ,out_DEPTH_MAX [i]->read(),0);
297	}
298
299	for (uint32_t i=0; i<_param->_nb_decod_unit;++i)
300	for (uint32_t j=0; j<_param->_nb_inst_decod[i]; ++j)
301	{
302	TEST(Tcontrol_t,out_DECOD_ACK [i][j]->read(),0); // No decod instruction
303	}
304
305	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
306	{
307	TEST(Tcontrol_t,out_BRANCH_COMPLETE_ACK [i]->read(),1); // Accept new branch_complete
308	}
309	}
310
311	SC_START(1);
312	}
313
314	/********************************************************
315	* Simulation - End
316	********************************************************/
317
318	TEST_OK ("End of Simulation");
319	delete _time;
320
321	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
322
323	delete in_CLOCK;
324	delete in_NRESET;
325
326	DELETE1_SC_SIGNAL( in_PREDICT_VAL ,_param->_nb_context);
327	DELETE1_SC_SIGNAL(out_PREDICT_ACK ,_param->_nb_context);
328	DELETE1_SC_SIGNAL( in_PREDICT_PC_PREVIOUS ,_param->_nb_context);
329	DELETE1_SC_SIGNAL( in_PREDICT_PC_CURRENT ,_param->_nb_context);
330	DELETE1_SC_SIGNAL( in_PREDICT_PC_CURRENT_IS_DS_TAKE ,_param->_nb_context);
331	DELETE1_SC_SIGNAL(out_PREDICT_PC_NEXT ,_param->_nb_context);
332	DELETE1_SC_SIGNAL(out_PREDICT_PC_NEXT_IS_DS_TAKE ,_param->_nb_context);
333	DELETE1_SC_SIGNAL(out_PREDICT_INST_IFETCH_PTR ,_param->_nb_context);
334	DELETE1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,_param->_nb_context);
335	DELETE1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_context);
336
337	DELETE2_SC_SIGNAL(out_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_context,_param->_nb_instruction[it1]);
338	DELETE2_SC_SIGNAL( in_DECOD_VAL ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
339	DELETE2_SC_SIGNAL(out_DECOD_ACK ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
340	DELETE2_SC_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
341	DELETE2_SC_SIGNAL( in_DECOD_MATCH_INST_IFETCH_PTR ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
342	DELETE2_SC_SIGNAL( in_DECOD_BRANCH_STATE ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
343	DELETE2_SC_SIGNAL( in_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
344	DELETE2_SC_SIGNAL( in_DECOD_BRANCH_CONDITION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
345	DELETE2_SC_SIGNAL( in_DECOD_BRANCH_DIRECTION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
346	DELETE2_SC_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
347	DELETE2_SC_SIGNAL( in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);
348
349	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
350	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
351	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
352	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
353	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
354	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete);
355	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
356	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
357	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
358	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
359
360	DELETE1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,_param->_nb_context);
361	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context);
362	//DELETE1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
363	DELETE1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context);
364	//DELETE1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context);
365	DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
366	DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context);
367	DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
368
369	DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context);
370	DELETE1_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_context);
371	DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context);
372	DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context);
373
374	DELETE1_SC_SIGNAL(out_DEPTH_CURRENT ,_param->_nb_context);
375	DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context);
376	DELETE1_SC_SIGNAL(out_DEPTH_MAX ,_param->_nb_context);
377	#endif
378
379	delete _Prediction_unit;
380	#ifdef STATISTICS
381	delete _parameters_statistics;
382	#endif
383	}

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