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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp @ 109

Last change on this file since 109 was 109, checked in by rosiere, 15 years ago
1) Configuration : instance configuration file : regroup similar instance 2) Configuration : timing default = 0 3) Debug/Commit_unit : Add watch dog timer 4) Issue_queue : Test parameters : add test if type is optionnal 5) Cor_glue : Fix insert index 6) Free_list : remove bank_by_pop (else deadlock) 7) Update Free List : add register to source event
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File size: 55.1 KB

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1	#ifdef SYSTEMC
2	/*
3	* $Id: Update_Prediction_Table_transition.cpp 109 2009-02-16 20:28:31Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace prediction_unit {
17	namespace update_prediction_table {
18
19	#undef FUNCTION
20	#define FUNCTION "Update_Prediction_Table::transition"
21	void Update_Prediction_Table::transition (void)
22	{
23	log_begin(Update_Prediction_Table,FUNCTION);
24	log_function(Update_Prediction_Table,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	// Initialisation
29
30	reg_UPDATE_PRIORITY = 0;
31
32	// All pointer is set at 0
33	for (uint32_t i=0; i<_param->_nb_context; i++)
34	{
35	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
36	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
37	reg_UFPT_BOTTOM [i] = 0;
38	reg_UFPT_TOP [i] = 0;
39	reg_UFPT_UPDATE [i] = 0;
40	reg_UFPT_NB_NEED_UPDATE [i] = 0;
41	reg_UFPT_NB_UPDATE [i] = 0;
42
43	for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j)
44	reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY;
45	reg_UPT_BOTTOM [i] = 0;
46	reg_UPT_TOP [i] = 0;
47	reg_UPT_TOP_EVENT [i] = 0;
48	reg_UPT_UPDATE [i] = 0;
49	reg_UPT_EMPTY [i] = true;
50
51	reg_IS_ACCURATE [i] = true;
52
53	reg_EVENT_VAL [i] = false;
54	reg_EVENT_STATE [i] = EVENT_STATE_OK;
55	}
56	}
57	else
58	{
59	bool flush_UFPT [_param->_nb_context];
60	for (uint32_t i=0; i<_param->_nb_context; i++)
61	{
62	flush_UFPT [i] = false;
63	}
64
65	// ===================================================================
66	// =====[ GARBAGE COLLECTOR ]=========================================
67	// ===================================================================
68
69	// Each cycle, if the most lastest branch have update all prediction struction (state = end), free this slot
70	// * Update state -> new status is "empty"
71	// * Update pointer (bottom and accurate)
72	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (BEGIN)");
73	for (uint32_t i=0; i<_param->_nb_context; i++)
74	{
75	// UPDATE_FETCH_PREDICTION_TABLE
76	{
77	uint32_t bottom = reg_UFPT_BOTTOM [i];
78
79	// Test if state is end
80	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state == UPDATE_FETCH_PREDICTION_STATE_END)
81	{
82	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d]",i,bottom);
83	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state = UPDATE_FETCH_PREDICTION_STATE_EMPTY",i,bottom);
84
85	// Free slot
86	reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
87	// Update pointer
88	reg_UFPT_BOTTOM [i] = (bottom+1)%_param->_size_ufpt_queue[i];
89	}
90	}
91
92	// UPDATE_PREDICTION_TABLE
93	{
94	uint32_t bottom = reg_UPT_BOTTOM [i];
95	bool end = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END);
96	// bool end_ok = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_OK);
97	// bool end_ko = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_KO);
98	// event_state_t event_state = reg_EVENT_STATE [i];
99
100	// Test if state is end
101	// if (end_ok or end_ko)
102	if (end)
103	{
104	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom);
105	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]._state = UPDATE_PREDICTION_STATE_EMPTY",i,bottom);
106	// Free slot
107	reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY;
108
109	// Update pointer
110	reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i];
111
112	if (reg_UPT_BOTTOM [i] == reg_UPT_TOP [i])
113	reg_UPT_EMPTY [i] = true; // free a slot
114
115	// if (bottom = reg_UPT_UPDATE [i])
116	// reg_UPT_UPDATE [i] = reg_UPT_BOTTOM [i];
117
118	if (reg_EVENT_VAL [i] and (reg_EVENT_UPT_PTR [i] == bottom))
119	{
120	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * END EVENT");
121
122	reg_EVENT_VAL [i] = false;
123	reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i];
124	reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i];
125
126	if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i])
127	reg_UPT_EMPTY [i] = false;
128
129	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]);
130	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]);
131	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]);
132	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]);
133	}
134
135	}
136	}
137	}
138
139	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (END)");
140
141	// ===================================================================
142	// =====[ PREDICT ]===================================================
143	// ===================================================================
144
145	// An ifetch_unit compute next cycle and have an branch : predict_val is set
146	// * Alloc new entry -> new status is "wait decod"
147	// * Save input (to restore in miss or error)
148	// * Update pointer
149
150	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
151	if (PORT_READ(in_PREDICT_VAL[i]) and internal_PREDICT_ACK [i])
152	{
153	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0;
154	uint32_t top = internal_PREDICT_UPDATE_PREDICTION_ID [i];
155
156	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * PREDICT[%d] - Accepted",i);
157	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
158	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
159
160	#ifdef DEBUG_TEST
161	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
162	throw ERRORMORPHEO(FUNCTION,_("Predict : invalid state."));
163	#endif
164
165	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD (predict)",context,top);
166	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state = UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD;
167
168	Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]);
169
170	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._condition = condition;
171	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]);
172	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]);
173	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]);
174	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]);
175	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._history = (_param->_have_port_history)?PORT_READ(in_PREDICT_DIR_HISTORY [i]):0;
176	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_PREDICT_RAS_ADDRESS [i]);
177	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_PREDICT_RAS_INDEX [i]);
178
179	reg_UFPT_TOP [context] = (top+1)%_param->_size_ufpt_queue [context];
180	// reg_UFPT_UPDATE [context] = reg_UFPT_TOP [context];
181	if (need_update(condition))
182	reg_UFPT_NB_NEED_UPDATE [context] ++;
183	}
184
185	// ===================================================================
186	// =====[ DECOD ]=====================================================
187	// ===================================================================
188
189
190	// An decod is detected by decod stage
191	// 1) Hit prediction : The instruction bundle have a branch predicted in ifetch stage and it is this branch
192	// * Update state, wait_decod -> wait_end
193	// * Pop ufpt -> push upt
194	// * Update accurate register : if the predict stage have tagged this branch as not accurate, stop decod
195	// 2) Miss : The instruction bundle have a branch but it is not predicted
196	// * Flush ufpt
197	// * decod information is write in upt
198
199	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
200	if (PORT_READ(in_DECOD_VAL[i]) and internal_DECOD_ACK [i])
201	{
202	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0;
203	Tcontrol_t miss_ifetch = PORT_READ(in_DECOD_MISS_IFETCH [i]);
204	Tcontrol_t miss_decod = PORT_READ(in_DECOD_MISS_DECOD [i]);
205	uint32_t upt_ptr_write = internal_DECOD_UPT_PTR_WRITE [i];
206	Tbranch_condition_t condition ;
207	Tcontrol_t is_accurate;
208	Taddress_t address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]);
209	Taddress_t address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]);
210	Tcontrol_t last_take = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]);
211
212	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * DECOD[%d] - Accepted",i);
213	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
214	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch);
215	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod);
216	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_ptr_write : %d",upt_ptr_write);
217
218	if (miss_ifetch or miss_decod)
219	{
220	// Have a miss !!!
221	#ifdef DEBUG_TEST
222	if (reg_EVENT_STATE [context] != EVENT_STATE_OK)
223	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state."));
224	#endif
225	if (reg_UFPT_NB_NEED_UPDATE [context] == 0)
226	{
227	// Change state
228	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context);
229	reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT;
230	}
231	else
232	{
233	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT (decod - miss - flush ufpt)",context);
234	reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT;
235	}
236	reg_EVENT_SOURCE [context] = EVENT_SOURCE_UFPT;
237
238	// Flush UPFT
239	flush_UFPT [context] = true;
240
241	reg_EVENT_DEPTH [context] = upt_ptr_write;
242	reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State
243	reg_EVENT_ADDRESS_DEST_VAL[context] = last_take;
244	reg_EVENT_ADDRESS_DEST [context] = address_dest;
245
246	// Push upt (from decod interface)
247	condition = PORT_READ(in_DECOD_BTB_CONDITION [i]);
248	is_accurate = PORT_READ(in_DECOD_IS_ACCURATE [i]);
249
250	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
251	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = address_src ;
252	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = address_dest;
253	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = last_take ;
254	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
255	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
256	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = ; // static prediction
257	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = PORT_READ(in_DECOD_RAS_ADDRESS [i]);
258	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = PORT_READ(in_DECOD_RAS_INDEX [i]);
259	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = false; // static prediction
260	}
261	else
262	{
263	// Normal case : branch is previous predicated, change state of branch
264	uint32_t ufpt_ptr_read = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0;
265
266	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ufpt_ptr_read : %d",ufpt_ptr_read);
267
268	#ifdef DEBUG_TEST
269	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state != UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
270	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt state."));
271	#endif
272	// Change state
273	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (decod - hit)",context,ufpt_ptr_read);
274	reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state = UPDATE_FETCH_PREDICTION_STATE_END;
275
276	// Push upt (from Pop ufpt)
277	condition = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._condition;
278	is_accurate = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._is_accurate;
279
280	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
281	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_src ;
282	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_dest;
283	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._last_take ;
284	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
285	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
286	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._history ;
287	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_ras ;
288	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._index_ras ;
289	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true ; // prediction from ifetch
290
291	// Update pointer
292	if (need_update(condition))
293	{
294	reg_UFPT_NB_NEED_UPDATE [context] --;
295	}
296	}
297
298	// All case !!!
299	#ifdef DEBUG_TEST
300	if (reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state != UPDATE_PREDICTION_STATE_EMPTY)
301	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt state."));
302	#endif
303
304	// Change state
305	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_WAIT_END (decod - hit)",context,upt_ptr_write);
306	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state = UPDATE_PREDICTION_STATE_WAIT_END;
307
308	// Write new accurate
309	#ifdef DEBUG_TEST
310	if (not reg_IS_ACCURATE [context] and not is_accurate)
311	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid accurate flag."));
312	#endif
313	reg_IS_ACCURATE [context] = is_accurate;
314
315	// Update pointer
316	reg_UPT_TOP [context] = (upt_ptr_write+1)%_param->_size_upt_queue [context];
317	reg_UPT_EMPTY [context] = false;
318	// reg_UPT_UPDATE [context] = reg_UPT_TOP [context];
319
320	// if (miss_ifetch or miss_decod)
321	// reg_UPT_TOP_EVENT [context] = reg_UPT_TOP [context];
322	}
323
324	// ===================================================================
325	// =====[ UPDATE ]====================================================
326	// ===================================================================
327	{
328	bool can_continue [_param->_nb_context];
329	for (uint32_t i=0; i<_param->_nb_context; ++i)
330	can_continue [i] = true;
331
332	for (uint32_t i=0; i<_param->_nb_inst_update; i++)
333	{
334	Tcontext_t context = internal_UPDATE_CONTEXT_ID [i];
335
336	if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or
337	(internal_UPDATE_VAL_WITHOUT_ACK [i] and can_continue [context]))
338	{
339	Tdepth_t depth = internal_UPDATE_DEPTH [i];
340
341	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i);
342	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
343	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
344
345	if (internal_UPDATE_FROM_UFPT [i])
346	{
347	// if free a slot, also all queue is updated
348	// Last slot ?
349	// if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context])
350	if ((--reg_UFPT_NB_UPDATE [context])==0)
351	switch (reg_EVENT_STATE [context])
352	{
353	case EVENT_STATE_MISS_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; break;
354	// impossible to have an update on ufpt and reg_upt_update>reg_upt_top
355	case EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT ; break;
356	case EVENT_STATE_EVENT_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_OK ; break;
357	case EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT: reg_EVENT_STATE [context] = EVENT_STATE_EVENT_FLUSH_UPT; break;
358	default : break;
359	}
360
361	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table");
362
363	// Change state
364	#ifdef DEBUG_TEST
365	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT)
366	throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state."));
367	#endif
368
369	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth);
370
371	reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END;
372
373	// Update pointer
374	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]);
375	reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1;
376	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]);
377	// Free a register that need update ?
378	if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition))
379	reg_UFPT_NB_NEED_UPDATE [context] --;
380	}
381	else
382	{
383	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table");
384
385	// Change state
386	#ifdef DEBUG_TEST
387	if (internal_UPDATE_RAS [i])
388	{
389	if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT) and
390	(reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO ) )
391	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
392	}
393	else
394	{
395	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK )
396	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
397	}
398	#endif
399
400	// bool have_event = ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO) or
401	// (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_EVENT));
402	#ifdef STATISTICS
403	Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
404	bool ok = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_OK);
405	#endif
406	bool ko = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO);
407
408	// Have an update, test the state to transiste to the good state
409	if (ko)
410	{
411	// Ko : wait end of all instruction
412	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO_WAIT_END (update)",context,depth);
413
414	// reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO_WAIT_END;
415
416	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",context,depth);
417
418	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO;
419
420	reg_EVENT_VAL [context] = true;
421	reg_EVENT_UPT_PTR [context] = depth;
422
423	#ifdef STATISTICS
424	if (usage_is_set(_usage,USE_STATISTICS))
425	(*_stat_nb_branch_miss [context][condition])++;
426	#endif
427	}
428	else
429	{
430	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_OK (update)",context,depth);
431	// reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_OK;
432
433	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth);
434	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END;
435
436	#ifdef STATISTICS
437	if (usage_is_set(_usage,USE_STATISTICS))
438	{
439	if (ok)
440	(*_stat_nb_branch_hit [context][condition]) ++;
441	else
442	(*_stat_nb_branch_unused [context]) ++;
443	}
444	#endif
445	}
446
447	// Update pointer
448	// * if update RAS : update pointer is decreaste until it equal at top pointer
449	if (internal_UPDATE_RAS [i])
450	{
451	// if end_event, restart too bottom, else decrease pointer
452	bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]);
453
454	reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1);
455	if (end_event)
456	{
457	// reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context];
458
459	if (reg_EVENT_STATE [context] == EVENT_STATE_EVENT_FLUSH_UPT)
460	{
461	reg_EVENT_STATE [context] = EVENT_STATE_OK;
462	}
463	else
464	reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT;
465	}
466	else
467	{
468	reg_UPT_UPDATE [context] = (((depth==0)?_param->_size_upt_queue[context]:depth)-1);
469	}
470	}
471	else
472	{
473	// increase pointer
474	reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context];
475	}
476
477	// Free the branch with no accurate ?
478	if ( (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) and not ko)
479	reg_IS_ACCURATE [context] = true;
480	}
481	}
482	else
483	can_continue [context] = false;
484	}
485
486	// Round robin
487	reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context;
488	}
489
490
491	// ===================================================================
492	// =====[ BRANCH_COMPLETE ]===========================================
493	// ===================================================================
494
495	// The branch is complete
496	// * Hit prediction :
497	// * update status
498	// * Miss prediction :
499	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
500	if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i])
501	{
502	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
503	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;
504	Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i];
505	Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i];
506	Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i];
507
508	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i);
509	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
510	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
511	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss);
512
513	if (miss)
514	{
515	// Have a miss !!!
516	// Flush UPFT
517	flush_UFPT [context] = true;
518
519	// Flush UPT
520	uint32_t top = reg_UPT_TOP [context];
521	uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1;
522
523	Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;
524	event_state_t event_state = reg_EVENT_STATE [context];
525	bool previous_event = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
526	(event_state == EVENT_STATE_MISS_FLUSH_UPT ) or
527	(event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
528	(event_state == EVENT_STATE_EVENT_FLUSH_UPT ) or
529	((event_state == EVENT_STATE_UPDATE_CONTEXT ) and
530	(reg_EVENT_SOURCE [context] == EVENT_SOURCE_UPT)));
531	// bool update_ras = (new_update != depth);
532
533	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
534	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update);
535	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras);
536	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_event : %d",previous_event);
537
538	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
539	{
540	for (uint32_t j=(depth+1)%_param->_size_upt_queue[context];
541	j!=top;
542	j=(j+1)%_param->_size_upt_queue[context])
543	reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT;
544
545
546	// reg_UPT_BOTTOM [context];
547	reg_UPT_TOP [context] = depth;
548	// reg_UPT_TOP_EVENT [context] = top;
549
550	if (not previous_event)
551	{
552	reg_UPT_TOP_EVENT [context] = top;
553	reg_UPT_UPDATE [context] = new_update;
554	}
555	else
556	{
557	// Have event. Top index this slot
558
559	switch (reg_UPDATE_PREDICTION_TABLE [context][top]._state)
560	{
561	case UPDATE_PREDICTION_STATE_END_KO :
562	{
563	// Have already update predictor
564	reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_END;
565	break;
566	}
567	case UPDATE_PREDICTION_STATE_KO :
568	{
569	// Doesn't have update predictor
570	reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT;
571	break;
572	}
573	default :
574	{
575	#ifdef DEBUG_TEST
576	throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
577	#endif
578	}
579	}
580	}
581
582	if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context])
583	reg_UPT_EMPTY [context] = true;
584
585	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth);
586	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO;
587
588	if (reg_UFPT_NB_NEED_UPDATE [context] > 0)
589	{
590	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context);
591	reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT;
592	}
593	else
594	{
595	// if (not previous_update_ras)
596	{
597	// have ras prediction ?
598	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context);
599
600	reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT;
601
602	}
603	}
604	reg_EVENT_SOURCE [context] = EVENT_SOURCE_UPT;
605
606	// else no update
607
608	reg_EVENT_DEPTH [context] = depth;
609	reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State
610	reg_EVENT_ADDRESS_DEST_VAL[context] = good_take;
611	reg_EVENT_ADDRESS_DEST [context] = good_addr;
612	}
613	}
614	else
615	{
616	// Hit case
617
618	// #ifdef DEBUG_TEST
619	// if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
620	// throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
621	// #endif
622
623	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
624	{
625	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth);
626	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK;
627	}
628	}
629
630	// In all case : update good_take
631	reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take;
632
633	// Write address_dest if need read register
634	Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
635
636	if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or
637	(condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or
638	(condition == BRANCH_CONDITION_READ_STACK ) )
639	reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr;
640	}
641
642	// ===================================================================
643	// =====[ BRANCH_EVENT ]==============================================
644	// ===================================================================
645	for (uint32_t i=0; i<_param->_nb_context; i++)
646	if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i]))
647	{
648	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_EVENT [%d] - Accepted",i);
649
650	// if different : an other branch is occured
651	if (reg_EVENT_STATE [i] == EVENT_STATE_UPDATE_CONTEXT)
652	{
653	// Change state
654	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_WAIT_END_EVENT (branch_event)",i);
655
656	reg_EVENT_STATE [i] = EVENT_STATE_WAIT_END_EVENT;
657	}
658	}
659
660	// ===================================================================
661	// =====[ EVENT ]=====================================================
662	// ===================================================================
663	for (uint32_t i=0; i<_param->_nb_context; ++i)
664	if (PORT_READ(in_EVENT_VAL [i]) and internal_EVENT_ACK [i])
665	{
666	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT");
667
668	//----------------------------------------------------------------
669	// Cases
670	//----------------------------------------------------------------
671	// * EVENT_TYPE_NONE - nothing
672	// * EVENT_TYPE_MISS_SPECULATION - Change state, reset pointer
673	// * EVENT_TYPE_EXCEPTION - Flush upft and upt, Change state, reset pointer
674	// * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update
675	// * EVENT_TYPE_SPR_ACCESS - nothing
676	// * EVENT_TYPE_MSYNC - nothing
677	// * EVENT_TYPE_PSYNC - nothing
678	// * EVENT_TYPE_CSYNC - nothing
679
680	Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]);
681
682	// Test if end of miss -> all previous branch is complete
683	// -> all next branch is finish
684
685	switch (event_type)
686	{
687	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
688	{
689	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_BRANCH_MISS_SPECULATION");
690
691	#ifdef DEBUG_TEST
692	if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT)
693	throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state."));
694	#endif
695
696	// Change state
697	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i);
698
699	reg_EVENT_STATE [i] = EVENT_STATE_OK;
700	reg_IS_ACCURATE [i] = true;
701
702	Tdepth_t depth = reg_EVENT_UPT_PTR [i];
703
704	if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_END_KO)
705	{
706	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (event)",i,depth);
707
708	reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END;
709	}
710
711	#ifdef DEBUG_TEST
712	// if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO_WAIT_END)
713	// throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state."));
714	// if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO)
715	// throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state."));
716	#endif
717
718	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",i,depth);
719
720	// reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END_KO;
721
722	break;
723	}
724	case EVENT_TYPE_LOAD_MISS_SPECULATION :
725	case EVENT_TYPE_EXCEPTION :
726	{
727	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_LOAD_MISS_SPECULATION");
728
729	// Have a miss !!!
730	// Flush UPFT
731	flush_UFPT [i] = true;
732
733	// Flush UPT
734	Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_EVENT_DEPTH [i]):0;
735	uint32_t top = reg_UPT_TOP [i];
736	uint32_t bottom = reg_UPT_BOTTOM [i];
737	uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1;
738	bool full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]);
739	// bool empty = reg_UPT_EMPTY [i];
740
741	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
742	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
743	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update);
744
745	event_state_t event_state = reg_EVENT_STATE [i];
746	bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
747	(event_state == EVENT_STATE_MISS_FLUSH_UPT ) or
748	(event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
749	(event_state == EVENT_STATE_EVENT_FLUSH_UPT));
750
751	bool find = false; // have slot to update ???
752
753	// flush all slot after the event
754	for (uint32_t j=(depth+1)%_param->_size_upt_queue[i];
755	j!=top;
756	j=(j+1)%_param->_size_upt_queue[i])
757	if ((reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_END) and
758	(reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY))
759	{
760	find = true;
761	reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT;
762	}
763
764	if ((reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END) and
765	(reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_EMPTY))
766	{
767	find = true;
768	reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT;
769	}
770
771	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find);
772
773	// Test if have update slot
774	if (find)
775	{
776	// flush all slot after the event
777	for (uint32_t j=(depth+1)%_param->_size_upt_queue[i];
778	j!=top;
779	j=(j+1)%_param->_size_upt_queue[i])
780	reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT;
781
782	reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT;
783
784	// reg_UPT_BOTTOM [i];
785	// TODO : special case : event is an exception on branch, also depth is not valid
786	reg_UPT_TOP [i] = depth; // depth is again valid
787	reg_UPT_TOP_EVENT [i] = top;
788
789	if (bottom == reg_UPT_TOP [i])
790	reg_UPT_EMPTY [i] = true;
791	}
792
793	bool update_ras = find and ((top != depth) or full);
794
795	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras);
796
797	if (not previous_update_ras and update_ras)
798	reg_UPT_UPDATE [i] = new_update;
799
800	// new state :
801	// * test if ufpt is empty
802	// * ok : flush upft and upt
803	// * ko : test if have previous flush upt
804	// * ok : nothing
805	// * ko : flush upt
806	reg_EVENT_VAL [i] = true;
807	reg_EVENT_UPT_PTR [i] = depth;
808
809	if (reg_UFPT_NB_NEED_UPDATE [i] > 0)
810	{
811	if (update_ras)
812	{
813	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT (branch_complete - miss)",i);
814	reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT;
815	}
816	else
817	{
818	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (branch_complete - miss)",i);
819	reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT;
820	}
821	}
822	else
823	{
824	// if (not previous_update_ras)
825	if (update_ras)
826	{
827	// have ras prediction ?
828	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (branch_complete - miss)",i);
829
830	reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UPT;
831	}
832	else
833	{
834	// special case : nothing
835	reg_EVENT_VAL [i] = false;
836
837	reg_EVENT_STATE [i] = EVENT_STATE_OK;
838	}
839	}
840
841	// else no update
842
843	reg_EVENT_DEPTH [i] = depth;
844	// reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State
845	// reg_EVENT_ADDRESS_DEST_VAL[i] = good_take;
846	// reg_EVENT_ADDRESS_DEST [i] = good_addr;
847
848	break;
849	}
850	default :
851	{
852	// nothing
853	break;
854	}
855	}
856	}
857
858	// ===================================================================
859	// =====[ FLUSH ]=====================================================
860	// ===================================================================
861
862	for (uint32_t i=0; i<_param->_nb_context; ++i)
863	{
864	if (flush_UFPT [i])
865	{
866	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Flush Update Fetch Prediction Table");
867	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",i);
868	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
869
870	// It's to accelerate miss speculation
871	if (reg_UFPT_NB_NEED_UPDATE [i] == 0)
872	{
873
874	// No entry need prediction, flush all entry -> Reset
875	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
876	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
877	reg_UFPT_BOTTOM [i] = 0;
878	reg_UFPT_TOP [i] = 0;
879	// reg_UFPT_UPDATE [i];
880	}
881	else
882	{
883	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
884	// EMPTY : no event
885	// END : already update
886	// EVENT : previous event
887	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state == UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
888	{
889	reg_UFPT_NB_UPDATE [i] ++;
890	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT;
891	}
892
893	// TOP is next write slot : last slot is TOP-1
894	uint32_t top = reg_UFPT_TOP [i];
895	reg_UFPT_UPDATE [i] = ((top==0)?_param->_size_ufpt_queue[i]:top)-1;
896
897	// reg_UFPT_BOTTOM [i];
898	// reg_UFPT_TOP [i];
899	}
900
901	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [i]);
902
903	}
904	}
905
906	#ifdef STATISTICS
907	if (usage_is_set(_usage,USE_STATISTICS))
908	for (uint32_t i=0; i<_param->_nb_context; i++)
909	{
910	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
911	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
912	(*_stat_ufpt_queue_nb_elt [i]) ++;
913	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
914	if (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY)
915	(*_stat_upt_queue_nb_elt [i]) ++;
916	}
917	#endif
918
919	// ===================================================================
920	// =====[ PRINT ]=====================================================
921	// ===================================================================
922
923	#if (DEBUG >= DEBUG_TRACE)
924	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump Update_Prediction_Table");
925	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPDATE_PRIORITY : %d",reg_UPDATE_PRIORITY);
926	for (uint32_t i=0; i<_param->_nb_context; i++)
927	{
928	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]);
929	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d" ,reg_EVENT_VAL [i]);
930	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d" ,reg_EVENT_UPT_PTR [i]);
931	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str());
932	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_SOURCE : %s" ,toString(reg_EVENT_SOURCE[i]).c_str());
933	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]);
934	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]<<2);
935	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST_VAL: %d" ,reg_EVENT_ADDRESS_DEST_VAL[i]);
936	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x (%.8x)",reg_EVENT_ADDRESS_DEST [i],reg_EVENT_ADDRESS_DEST [i]<<2);
937
938	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Fetch_Prediction_Table [%d]",i);
939	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_BOTTOM : %d",reg_UFPT_BOTTOM [i]);
940	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_TOP : %d",reg_UFPT_TOP [i]);
941	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE : %d",reg_UFPT_UPDATE [i]);
942	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
943	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]);
944	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
945	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d, %.8d %.8x (%.8x) %.4d - %s",
946	j,
947	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition,
948	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src,
949	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src<<2,
950	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest,
951	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest<<2,
952	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take,
953	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate,
954	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history,
955	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras,
956	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras<<2,
957	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras,
958	toString(reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state).c_str()
959	);
960
961	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Prediction_Table [%d]",i);
962	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]);
963	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]);
964	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]);
965	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]);
966	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]);
967	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
968	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d %.1d, %.8d %.8x (%.8x) %.4d - %s",
969	j,
970	reg_UPDATE_PREDICTION_TABLE [i][j]._condition,
971	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src,
972	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src<<2,
973	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest,
974	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest<<2,
975	reg_UPDATE_PREDICTION_TABLE [i][j]._last_take,
976	reg_UPDATE_PREDICTION_TABLE [i][j]._good_take,
977	reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate,
978	reg_UPDATE_PREDICTION_TABLE [i][j]._history,
979	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras,
980	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras<<2,
981	reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras,
982	toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str()
983	);
984	}
985	#endif
986
987	#ifdef DEBUG_TEST
988	for (uint32_t i=0; i<_param->_nb_context; i++)
989	{
990	if (reg_UFPT_NB_NEED_UPDATE [i] > _param->_size_ufpt_queue[i])
991	throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_NEED_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_NEED_UPDATE [i],_param->_size_ufpt_queue[i]));
992	if (reg_UFPT_NB_UPDATE [i] > _param->_size_ufpt_queue[i])
993	throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_UPDATE [i],_param->_size_ufpt_queue[i]));
994	}
995	#endif
996
997	}
998
999
1000	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
1001	end_cycle ();
1002	#endif
1003
1004	log_end(Update_Prediction_Table,FUNCTION);
1005	};
1006
1007	}; // end namespace update_prediction_table
1008	}; // end namespace prediction_unit
1009	}; // end namespace front_end
1010	}; // end namespace multi_front_end
1011	}; // end namespace core
1012
1013	}; // end namespace behavioural
1014	}; // end namespace morpheo
1015	#endif

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