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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 15 years ago
Almost complete design with Test and test platform
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1	#ifdef SYSTEMC
2	/*
3	* $Id: Update_Prediction_Table_transition.cpp 88 2008-12-10 18:31:39Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace prediction_unit {
17	namespace update_prediction_table {
18
19	#undef FUNCTION
20	#define FUNCTION "Update_Prediction_Table::transition"
21	void Update_Prediction_Table::transition (void)
22	{
23	log_begin(Update_Prediction_Table,FUNCTION);
24	log_function(Update_Prediction_Table,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	// Initialisation
29
30	reg_UPDATE_PRIORITY = 0;
31
32	// All pointer is set at 0
33	for (uint32_t i=0; i<_param->_nb_context; i++)
34	{
35	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
36	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
37	reg_UFPT_BOTTOM [i] = 0;
38	reg_UFPT_TOP [i] = 0;
39	reg_UFPT_UPDATE [i] = 0;
40	reg_UFPT_NB_NEED_UPDATE [i] = 0;
41
42	for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j)
43	reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY;
44	reg_UPT_BOTTOM [i] = 0;
45	reg_UPT_TOP [i] = 0;
46	reg_UPT_UPDATE [i] = 0;
47	reg_UPT_NB_NEED_UPDATE [i] = 0;
48
49	reg_IS_ACCURATE [i] = true;
50
51	reg_EVENT_STATE [i] = EVENT_STATE_OK;
52	}
53	}
54	else
55	{
56	// ===================================================================
57	// =====[ GARBAGE COLLECTOR ]=========================================
58	// ===================================================================
59
60	// Each cycle, if the most lastest branch have update all prediction struction (state = end), free this slot
61	// * Update state -> new status is "empty"
62	// * Update pointer (bottom and accurate)
63	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR");
64	for (uint32_t i=0; i<_param->_nb_context; i++)
65	{
66	// UPDATE_FETCH_PREDICTION_TABLE
67	{
68	uint32_t bottom = reg_UFPT_BOTTOM [i];
69
70	// Test if state is end
71	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state == UPDATE_FETCH_PREDICTION_STATE_END)
72	{
73	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d]",i,bottom);
74	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state = UPDATE_FETCH_PREDICTION_STATE_EMPTY",i,bottom);
75
76	// Free slot
77	reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
78	// Update pointer
79	reg_UFPT_BOTTOM [i] = (bottom+1)%_param->_size_ufpt_queue[i];
80	}
81	}
82
83	// UPDATE_PREDICTION_TABLE
84	{
85	uint32_t bottom = reg_UPT_BOTTOM [i];
86
87	// Test if state is end
88	if (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END)
89	{
90	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom);
91	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]._state = UPDATE_PREDICTION_STATE_EMPTY",i,bottom);
92
93	// Free slot
94	reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY;
95	// Update pointer
96	reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i];
97	}
98	}
99	}
100
101	// ===================================================================
102	// =====[ PREDICT ]===================================================
103	// ===================================================================
104
105	// An ifetch_unit compute next cycle and have an branch : predict_val is set
106	// * Alloc new entry -> new status is "wait decod"
107	// * Save input (to restore in miss or error)
108	// * Update pointer
109
110	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
111	if (PORT_READ(in_PREDICT_VAL[i]) and internal_PREDICT_ACK [i])
112	{
113	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0;
114	uint32_t top = internal_PREDICT_UPDATE_PREDICTION_ID [i];
115
116	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * PREDICT[%d] - Accepted",i);
117	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
118	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
119
120	#ifdef DEBUG_TEST
121	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
122	throw ERRORMORPHEO(FUNCTION,_("Predict : invalid state."));
123	#endif
124
125	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD (predict)",context,top);
126	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state = UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD;
127
128	Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]);
129
130	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._condition = condition;
131	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]);
132	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]);
133	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]);
134	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]);
135	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._history = (_param->_have_port_history)?PORT_READ(in_PREDICT_DIR_HISTORY [i]):0;
136	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_PREDICT_RAS_ADDRESS [i]);
137	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_PREDICT_RAS_INDEX [i]);
138
139	reg_UFPT_TOP [context] = (top+1)%_param->_size_ufpt_queue [context];
140	// reg_UFPT_UPDATE [context] = reg_UFPT_TOP [context];
141	if (need_update(condition))
142	reg_UFPT_NB_NEED_UPDATE [context] ++;
143	}
144
145	// ===================================================================
146	// =====[ DECOD ]=====================================================
147	// ===================================================================
148
149
150	// An decod is detected by decod stage
151	// 1) Hit prediction : The instruction bundle have a branch predicted in ifetch stage and it is this branch
152	// * Update state, wait_decod -> wait_end
153	// * Pop ufpt -> push upt
154	// * Update accurate register : if the predict stage have tagged this branch as not accurate, stop decod
155	// 2) Miss : The instruction bundle have a branch but it is not predicted
156	// * Flush ufpt
157	// * decod information is write in upt
158
159	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
160	if (PORT_READ(in_DECOD_VAL[i]) and internal_DECOD_ACK [i])
161	{
162	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0;
163	Tcontrol_t miss_ifetch = PORT_READ(in_DECOD_MISS_IFETCH [i]);
164	Tcontrol_t miss_decod = PORT_READ(in_DECOD_MISS_DECOD [i]);
165	uint32_t upt_ptr_write = internal_DECOD_UPT_PTR_WRITE [i];
166	Tbranch_condition_t condition ;
167	Tcontrol_t is_accurate;
168
169	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * DECOD[%d] - Accepted",i);
170	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
171	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch);
172	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod);
173	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_ptr_write : %d",upt_ptr_write);
174
175	if (miss_ifetch or miss_decod)
176	{
177	// Have a miss !!!
178
179	// Flush UPFT
180
181	// It's to accelerate miss speculation
182	if (reg_UFPT_NB_NEED_UPDATE [context] == 0)
183	{
184	// No entry need prediction, flush all entry -> Reset
185	for (uint32_t j=0; j<_param->_size_ufpt_queue[context]; ++j)
186	reg_UPDATE_FETCH_PREDICTION_TABLE [context][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
187	reg_UFPT_BOTTOM [context] = 0;
188	reg_UFPT_TOP [context] = 0;
189	// reg_UFPT_UPDATE [context] = 0;
190	}
191	else
192	{
193	reg_UFPT_UPDATE [context] = reg_UFPT_TOP [context];
194
195	#ifdef DEBUG_TEST
196	if (reg_EVENT_STATE [context] == EVENT_STATE_OK)
197	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state."));
198	#endif
199
200	// Change state
201	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT (decod - miss)",context);
202
203	reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UFPT;
204	}
205
206	// Push upt (from decod interface)
207	condition = PORT_READ(in_DECOD_BTB_CONDITION [i]);
208	is_accurate = PORT_READ(in_DECOD_IS_ACCURATE [i]);
209
210	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
211	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]);
212	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]);
213	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]);
214	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
215	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
216	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = ; // static prediction
217	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = PORT_READ(in_DECOD_RAS_ADDRESS [i]);
218	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = PORT_READ(in_DECOD_RAS_INDEX [i]);
219	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = false; // static prediction
220	}
221	else
222	{
223	// Normal case : branch is previous predicated, change state of branch
224	uint32_t ufpt_ptr_read = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0;
225
226	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ufpt_ptr_read : %d",ufpt_ptr_read);
227
228	#ifdef DEBUG_TEST
229	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state != UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
230	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt state."));
231	#endif
232	// Change state
233	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (decod - hit)",context,ufpt_ptr_read);
234	reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state = UPDATE_FETCH_PREDICTION_STATE_END;
235
236	// Push upt (from Pop ufpt)
237	condition = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._condition;
238	is_accurate = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._is_accurate;
239
240	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
241	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_src ;
242	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_dest;
243	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._last_take ;
244	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
245	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
246	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._history ;
247	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_ras ;
248	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._index_ras ;
249	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true; // prediction from ifetch
250
251	// Update pointer
252	if (need_update(condition))
253	{
254	reg_UFPT_NB_NEED_UPDATE [context] --;
255	}
256	}
257
258	// All case !!!
259
260	#ifdef DEBUG_TEST
261	if (reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state != UPDATE_PREDICTION_STATE_EMPTY)
262	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt state."));
263	#endif
264
265	// Change state
266	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_WAIT_END (decod - hit)",context,upt_ptr_write);
267	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state = UPDATE_PREDICTION_STATE_WAIT_END;
268
269	// Write new accurate
270	#ifdef DEBUG_TEST
271	if (not reg_IS_ACCURATE [context] and not is_accurate)
272	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid accurate flag."));
273	#endif
274	reg_IS_ACCURATE [context] = is_accurate;
275
276	// Update pointer
277	reg_UPT_TOP [context] = (upt_ptr_write+1)%_param->_size_upt_queue [context];
278	// reg_UPT_UPDATE [context] = reg_UPT_TOP [context];
279	if (need_update(condition))
280	{
281	reg_UPT_NB_NEED_UPDATE [context] ++;
282	}
283	}
284
285	// ===================================================================
286	// =====[ BRANCH_COMPLETE ]===========================================
287	// ===================================================================
288
289	// The branch is complete
290	// * Hit prediction :
291	// * update status
292	// * Miss prediction :
293	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
294	if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i])
295	{
296	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
297	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;
298
299	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i);
300	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
301	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
302	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",internal_BRANCH_COMPLETE_MISS_PREDICTION [i]);
303
304	if (internal_BRANCH_COMPLETE_MISS_PREDICTION [i])
305	{
306	// Miss case
307	// // breakpoint("Branch_complete and miss ...");
308
309	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_EVENT (branch_complete)",context,depth);
310	// reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_EVENT;
311
312	// // Another prediction (prediction with depth higer)
313	// Tdepth_t top = reg_TOP [context];
314	// uint32_t nb_elt_miss = ((top> depth)?top:(top+_param->_size_queue[context]))-depth;
315	// uint32_t nb_elt_need_update = 1;
316	// for (uint32_t j=1; j<nb_elt_miss; j++)
317	// {
318	// uint32_t k=(depth+j)%_param->_size_queue[context];
319
320	// // Ifetch have make a prediction and it's a miss
321	// // When ifetch predict :
322	// // * btb is not change -> needn't update
323	// // * direction is not change -> needn't update
324	// // * ras have change -> need update
325
326	// Tbranch_condition_t cond = reg_UPDATE_PREDICTION_TABLE [context][k]._condition;
327	// if ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK) or
328	// (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK) or
329	// (cond == BRANCH_CONDITION_READ_STACK))
330	// {
331	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch miss, update ras)",context,k);
332
333	// nb_elt_need_update ++;
334	// reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_KO;
335	// }
336	// else
337	// {
338	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_END (branch_complete, ifetch miss, don't update ras)",context,k);
339
340	// reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_END;
341	// }
342	// }
343	// reg_NB_ELT_NEED_UPDATE [context] += nb_elt_need_update;
344
345	// // Update pointer :
346	// reg_TOP [context] = depth;
347	// reg_NB_ELT [context] -= nb_elt_miss;
348	// reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = internal_BRANCH_COMPLETE_ADDRESS_DEST [i];
349
350	}
351	else
352	{
353	// Hit case
354
355	#ifdef DEBUG_TEST
356	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
357	throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
358	#endif
359
360	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth);
361	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK;
362	}
363
364	// In all case : update good_take
365	reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = internal_BRANCH_COMPLETE_TAKE [i];
366	}
367
368	// ===================================================================
369	// =====[ UPDATE ]====================================================
370	// ===================================================================
371	for (uint32_t i=0; i<_param->_nb_inst_update; i++)
372	if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or
373	(internal_UPDATE_VAL_WITHOUT_ACK [i]))
374	{
375	Tcontext_t context = internal_UPDATE_CONTEXT_ID [i];
376	Tdepth_t depth = internal_UPDATE_DEPTH [i];
377	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i);
378	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
379	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
380
381	if (internal_UPDATE_FROM_UFPT [i])
382	{
383	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table");
384
385	// Change state
386	#ifdef DEBUG_TEST
387	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT)
388	throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state."));
389	#endif
390
391	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth);
392
393	reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END;
394
395	// Update pointer
396	reg_UFPT_UPDATE [context] = (depth==0)?(_param->_size_ufpt_queue[context]-1):(depth-1);
397
398	// Free a register that need update ?
399	if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition))
400	reg_UFPT_NB_NEED_UPDATE [context] --;
401	}
402	else
403	{
404	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table");
405
406	// Change state
407	#ifdef DEBUG_TEST
408	if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK ) and
409	(reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO ) and
410	(reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT))
411	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
412	#endif
413
414	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth);
415
416	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END;
417
418	// Update pointer
419	if (internal_UPDATE_RAS [i])
420	reg_UPT_UPDATE [context] = (depth==0)?(_param->_size_upt_queue[context]-1):(depth-1);
421	else
422	reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context];
423
424	// Free a register that need update ?
425	if (need_update(reg_UPDATE_PREDICTION_TABLE [context][depth]._condition))
426	reg_UPT_NB_NEED_UPDATE [context] --;
427	// Free the branch with no accurate ?
428	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false)
429	reg_IS_ACCURATE [i] = true;
430	}
431	}
432
433	// Round robin
434	reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context;
435
436	// // ===================================================================
437	// // =====[ BRANCH_EVENT ]==============================================
438	// // ===================================================================
439	// for (uint32_t i=0; i<_param->_nb_context; i++)
440	// if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i]))
441	// {
442	// Tdepth_t depth = internal_BRANCH_EVENT_DEPTH [i];
443
444	// if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_EVENT)
445	// {
446	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_KO (branch_event)",i,depth);
447
448	// reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_KO;
449	// }
450	// else
451	// {
452	// #ifdef DEBUG_TEST
453	// if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_WAITEND_AND_EVENT)
454	// throw ERRORMORPHEO(FUNCTION,_("Branche event : invalid state"));
455	// #endif
456
457	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_WAITEND (branch_event)",i,depth);
458
459	// reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_WAITEND;
460	// }
461	// }
462
463	#if (DEBUG >= DEBUG_TRACE)
464	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump Update_Prediction_Table");
465	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPDATE_PRIORITY : %d",reg_UPDATE_PRIORITY);
466	for (uint32_t i=0; i<_param->_nb_context; i++)
467	{
468	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]);
469	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str());
470	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_RAS_CORRUPTED : %d" ,reg_EVENT_RAS_CORRUPTED [i]);
471	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x",reg_EVENT_ADDRESS_SRC [i]);
472	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC_VAL : %d" ,reg_EVENT_ADDRESS_SRC_VAL [i]);
473	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x",reg_EVENT_ADDRESS_DEST [i]);
474
475	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Fetch_Prediction_Table [%d]",i);
476	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_BOTTOM : %d",reg_UFPT_BOTTOM [i]);
477	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_TOP : %d",reg_UFPT_TOP [i]);
478	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
479	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
480	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x %.8x, %.1d %.1d, %.8d %.8x %.4d - %s",
481	j,
482	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition,
483	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src,
484	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest,
485	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take,
486	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate,
487	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history,
488	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras,
489	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras,
490	toString(reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state).c_str()
491	);
492
493	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Prediction_Table [%d]",i);
494	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]);
495	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]);
496	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]);
497	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_NB_NEED_UPDATE : %d",reg_UPT_NB_NEED_UPDATE [i]);
498	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
499	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x %.8x, %.1d %.1d %.1d, %.8d %.8x %.4d - %s",
500	j,
501	reg_UPDATE_PREDICTION_TABLE [i][j]._condition,
502	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src,
503	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest,
504	reg_UPDATE_PREDICTION_TABLE [i][j]._last_take,
505	reg_UPDATE_PREDICTION_TABLE [i][j]._good_take,
506	reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate,
507	reg_UPDATE_PREDICTION_TABLE [i][j]._history,
508	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras,
509	reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras,
510	toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str()
511	);
512	}
513	#endif
514	}
515
516
517	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
518	end_cycle ();
519	#endif
520
521	log_end(Update_Prediction_Table,FUNCTION);
522	};
523
524	}; // end namespace update_prediction_table
525	}; // end namespace prediction_unit
526	}; // end namespace front_end
527	}; // end namespace multi_front_end
528	}; // end namespace core
529
530	}; // end namespace behavioural
531	}; // end namespace morpheo
532	#endif

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