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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp @ 95

Last change on this file since 95 was 95, checked in by rosiere, 15 years ago
1) Update Prediction Table - New architecture (systemC) done (and tested) -> need change interface in top level 2) Change documentation on VHDL generation 3) Change VHDL constant (case std_logic and std_logic_vector)
Property svn:keywords set to `Id`
File size: 37.6 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Update_Prediction_Table_transition.cpp 95 2008-12-16 16:24:26Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace prediction_unit {
17	namespace update_prediction_table {
18
19	#undef FUNCTION
20	#define FUNCTION "Update_Prediction_Table::transition"
21	void Update_Prediction_Table::transition (void)
22	{
23	log_begin(Update_Prediction_Table,FUNCTION);
24	log_function(Update_Prediction_Table,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	// Initialisation
29
30	reg_UPDATE_PRIORITY = 0;
31
32	// All pointer is set at 0
33	for (uint32_t i=0; i<_param->_nb_context; i++)
34	{
35	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
36	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
37	reg_UFPT_BOTTOM [i] = 0;
38	reg_UFPT_TOP [i] = 0;
39	reg_UFPT_UPDATE [i] = 0;
40	reg_UFPT_NB_NEED_UPDATE [i] = 0;
41
42	for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j)
43	reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY;
44	reg_UPT_BOTTOM [i] = 0;
45	reg_UPT_TOP [i] = 0;
46	reg_UPT_TOP_EVENT [i] = 0;
47	reg_UPT_UPDATE [i] = 0;
48
49	reg_IS_ACCURATE [i] = true;
50
51	reg_EVENT_STATE [i] = EVENT_STATE_OK;
52	}
53	}
54	else
55	{
56	bool flush_UFPT [_param->_nb_context];
57	for (uint32_t i=0; i<_param->_nb_context; i++)
58	flush_UFPT [i] = false;
59
60	// ===================================================================
61	// =====[ GARBAGE COLLECTOR ]=========================================
62	// ===================================================================
63
64	// Each cycle, if the most lastest branch have update all prediction struction (state = end), free this slot
65	// * Update state -> new status is "empty"
66	// * Update pointer (bottom and accurate)
67	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR");
68	for (uint32_t i=0; i<_param->_nb_context; i++)
69	{
70	// UPDATE_FETCH_PREDICTION_TABLE
71	{
72	uint32_t bottom = reg_UFPT_BOTTOM [i];
73
74	// Test if state is end
75	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state == UPDATE_FETCH_PREDICTION_STATE_END)
76	{
77	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d]",i,bottom);
78	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state = UPDATE_FETCH_PREDICTION_STATE_EMPTY",i,bottom);
79
80	// Free slot
81	reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
82	// Update pointer
83	reg_UFPT_BOTTOM [i] = (bottom+1)%_param->_size_ufpt_queue[i];
84	}
85	}
86
87	// UPDATE_PREDICTION_TABLE
88	{
89	uint32_t bottom = reg_UPT_BOTTOM [i];
90	bool end_ok = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_OK);
91	bool end_ko = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_KO);
92
93	// Test if state is end
94	if (end_ok or end_ko)
95	{
96	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom);
97	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]._state = UPDATE_PREDICTION_STATE_EMPTY",i,bottom);
98
99	// Free slot
100	reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY;
101
102	// Update pointer
103	reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i];
104	// if (bottom = reg_UPT_UPDATE [i])
105	// reg_UPT_UPDATE [i] = reg_UPT_BOTTOM [i];
106	if (end_ko) // free
107	{
108	reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i];
109	reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i];
110	}
111	}
112	}
113	}
114
115	// ===================================================================
116	// =====[ PREDICT ]===================================================
117	// ===================================================================
118
119	// An ifetch_unit compute next cycle and have an branch : predict_val is set
120	// * Alloc new entry -> new status is "wait decod"
121	// * Save input (to restore in miss or error)
122	// * Update pointer
123
124	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
125	if (PORT_READ(in_PREDICT_VAL[i]) and internal_PREDICT_ACK [i])
126	{
127	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0;
128	uint32_t top = internal_PREDICT_UPDATE_PREDICTION_ID [i];
129
130	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * PREDICT[%d] - Accepted",i);
131	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
132	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
133
134	#ifdef DEBUG_TEST
135	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
136	throw ERRORMORPHEO(FUNCTION,_("Predict : invalid state."));
137	#endif
138
139	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD (predict)",context,top);
140	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state = UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD;
141
142	Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]);
143
144	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._condition = condition;
145	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]);
146	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]);
147	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]);
148	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]);
149	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._history = (_param->_have_port_history)?PORT_READ(in_PREDICT_DIR_HISTORY [i]):0;
150	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_PREDICT_RAS_ADDRESS [i]);
151	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_PREDICT_RAS_INDEX [i]);
152
153	reg_UFPT_TOP [context] = (top+1)%_param->_size_ufpt_queue [context];
154	// reg_UFPT_UPDATE [context] = reg_UFPT_TOP [context];
155	if (need_update(condition))
156	reg_UFPT_NB_NEED_UPDATE [context] ++;
157	}
158
159	// ===================================================================
160	// =====[ DECOD ]=====================================================
161	// ===================================================================
162
163
164	// An decod is detected by decod stage
165	// 1) Hit prediction : The instruction bundle have a branch predicted in ifetch stage and it is this branch
166	// * Update state, wait_decod -> wait_end
167	// * Pop ufpt -> push upt
168	// * Update accurate register : if the predict stage have tagged this branch as not accurate, stop decod
169	// 2) Miss : The instruction bundle have a branch but it is not predicted
170	// * Flush ufpt
171	// * decod information is write in upt
172
173	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
174	if (PORT_READ(in_DECOD_VAL[i]) and internal_DECOD_ACK [i])
175	{
176	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0;
177	Tcontrol_t miss_ifetch = PORT_READ(in_DECOD_MISS_IFETCH [i]);
178	Tcontrol_t miss_decod = PORT_READ(in_DECOD_MISS_DECOD [i]);
179	uint32_t upt_ptr_write = internal_DECOD_UPT_PTR_WRITE [i];
180	Tbranch_condition_t condition ;
181	Tcontrol_t is_accurate;
182	Taddress_t address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]);
183	Taddress_t address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]);
184	Tcontrol_t last_take = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]);
185
186	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * DECOD[%d] - Accepted",i);
187	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
188	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch);
189	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod);
190	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_ptr_write : %d",upt_ptr_write);
191
192	if (miss_ifetch or miss_decod)
193	{
194	// Have a miss !!!
195	#ifdef DEBUG_TEST
196	if (reg_EVENT_STATE [context] != EVENT_STATE_OK)
197	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state."));
198	#endif
199
200	if (reg_UFPT_NB_NEED_UPDATE [context] == 0)
201	{
202	// Change state
203	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context);
204	reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT;
205	}
206	else
207	{
208	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT (decod - miss - flush ufpt)",context);
209	reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UFPT;
210	}
211
212	// Flush UPFT
213	flush_UFPT [context] = true;
214
215	reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State
216	reg_EVENT_ADDRESS_DEST_VAL[context] = last_take;
217	reg_EVENT_ADDRESS_DEST [context] = address_dest;
218
219	// Push upt (from decod interface)
220	condition = PORT_READ(in_DECOD_BTB_CONDITION [i]);
221	is_accurate = PORT_READ(in_DECOD_IS_ACCURATE [i]);
222
223	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
224	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = address_src ;
225	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = address_dest;
226	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = last_take ;
227	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
228	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
229	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = ; // static prediction
230	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = PORT_READ(in_DECOD_RAS_ADDRESS [i]);
231	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = PORT_READ(in_DECOD_RAS_INDEX [i]);
232	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = false; // static prediction
233	}
234	else
235	{
236	// Normal case : branch is previous predicated, change state of branch
237	uint32_t ufpt_ptr_read = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0;
238
239	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ufpt_ptr_read : %d",ufpt_ptr_read);
240
241	#ifdef DEBUG_TEST
242	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state != UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
243	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt state."));
244	#endif
245	// Change state
246	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (decod - hit)",context,ufpt_ptr_read);
247	reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state = UPDATE_FETCH_PREDICTION_STATE_END;
248
249	// Push upt (from Pop ufpt)
250	condition = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._condition;
251	is_accurate = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._is_accurate;
252
253	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
254	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_src ;
255	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_dest;
256	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._last_take ;
257	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
258	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
259	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._history ;
260	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_ras ;
261	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._index_ras ;
262	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true; // prediction from ifetch
263
264	// Update pointer
265	if (need_update(condition))
266	{
267	reg_UFPT_NB_NEED_UPDATE [context] --;
268	}
269	}
270
271	// All case !!!
272
273	#ifdef DEBUG_TEST
274	if (reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state != UPDATE_PREDICTION_STATE_EMPTY)
275	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt state."));
276	#endif
277
278	// Change state
279	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_WAIT_END (decod - hit)",context,upt_ptr_write);
280	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state = UPDATE_PREDICTION_STATE_WAIT_END;
281
282	// Write new accurate
283	#ifdef DEBUG_TEST
284	if (not reg_IS_ACCURATE [context] and not is_accurate)
285	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid accurate flag."));
286	#endif
287	reg_IS_ACCURATE [context] = is_accurate;
288
289	// Update pointer
290	reg_UPT_TOP [context] = (upt_ptr_write+1)%_param->_size_upt_queue [context];
291	// reg_UPT_UPDATE [context] = reg_UPT_TOP [context];
292	}
293
294	// ===================================================================
295	// =====[ BRANCH_COMPLETE ]===========================================
296	// ===================================================================
297
298	// The branch is complete
299	// * Hit prediction :
300	// * update status
301	// * Miss prediction :
302	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
303	if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i])
304	{
305	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
306	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;
307	Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i];
308	Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i];
309	Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i];
310
311	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i);
312	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
313	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
314	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss);
315
316	if (miss)
317	{
318	// Have a miss !!!
319	// Flush UPFT
320	flush_UFPT [context] = true;
321
322	// Flush UPT
323	uint32_t top = reg_UPT_TOP [context];
324	uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1;
325
326	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
327	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update);
328
329	for (uint32_t j=(depth+1)%_param->_size_upt_queue[context];
330	j!=top;
331	j=(j+1)%_param->_size_upt_queue[context])
332	reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT;
333
334
335	// reg_UPT_BOTTOM [context];
336	reg_UPT_TOP [context] = depth;
337	reg_UPT_TOP_EVENT [context] = top;
338
339	#ifdef DEBUG_TEST
340	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
341	throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
342	#endif
343
344	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth);
345	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO;
346
347	Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;
348	event_state_t event_state = reg_EVENT_STATE [context];
349	bool previous_update_ras = (event_state == EVENT_STATE_FLUSH_UPT);
350	bool update_ras = (new_update != depth);
351
352	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras);
353
354	if (reg_UFPT_NB_NEED_UPDATE [context] > 0)
355	{
356	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context);
357	reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UFPT_AND_UPT;
358	}
359	else
360	{
361	if (not previous_update_ras)
362	{
363	// have ras prediction ?
364	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UPT (branch_complete - miss)",context);
365
366	reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UPT;
367
368	}
369	}
370
371	if (not previous_update_ras)
372	{
373	reg_UPT_UPDATE [context] = new_update;
374	}
375	// else no update
376
377	reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State
378	reg_EVENT_ADDRESS_DEST_VAL[context] = good_take;
379	reg_EVENT_ADDRESS_DEST [context] = good_addr;
380	}
381	else
382	{
383	// Hit case
384
385	#ifdef DEBUG_TEST
386	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
387	throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
388	#endif
389
390	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth);
391	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK;
392	}
393
394	// In all case : update good_take
395	reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take;
396	}
397
398	// ===================================================================
399	// =====[ UPDATE ]====================================================
400	// ===================================================================
401	{
402	bool can_continue [_param->_nb_context];
403	for (uint32_t i=0; i<_param->_nb_context; ++i)
404	can_continue [i] = true;
405
406	for (uint32_t i=0; i<_param->_nb_inst_update; i++)
407	{
408	Tcontext_t context = internal_UPDATE_CONTEXT_ID [i];
409
410	if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or
411	(internal_UPDATE_VAL_WITHOUT_ACK [i] and can_continue [context]))
412	{
413	Tdepth_t depth = internal_UPDATE_DEPTH [i];
414
415	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i);
416	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
417	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
418
419	if (internal_UPDATE_FROM_UFPT [i])
420	{
421	// if free a slot, also all queue is updated
422	// Last slot ?
423	if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context])
424	switch (reg_EVENT_STATE [context])
425	{
426	case EVENT_STATE_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; break;
427	// impossible to have an update on ufpt and reg_upt_update>reg_upt_top
428	case EVENT_STATE_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UPT ; break;
429	default : break;
430	}
431
432	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table");
433
434	// Change state
435	#ifdef DEBUG_TEST
436	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT)
437	throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state."));
438	#endif
439
440	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth);
441
442	reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END;
443
444
445	// Update pointer
446	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]);
447	reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1;
448	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]);
449	// Free a register that need update ?
450	if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition))
451	reg_UFPT_NB_NEED_UPDATE [context] --;
452	}
453	else
454	{
455	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table");
456
457	// Change state
458	#ifdef DEBUG_TEST
459	if (internal_UPDATE_RAS [i])
460	{
461	if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT) and
462	(reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO ))
463	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
464	}
465	else
466	{
467	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK )
468	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
469	}
470	#endif
471
472	// bool have_event = ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO) or
473	// (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_EVENT));
474	bool ko = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO);
475
476	// Have an update, test the state to transiste to the good state
477	if (ko)
478	{
479	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",context,depth);
480
481	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO;
482	}
483	else
484	{
485	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_OK (update)",context,depth);
486
487	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_OK;
488	}
489
490	// Update pointer
491	// * if update RAS : update pointer is decreaste until it equal at top pointer
492	if (internal_UPDATE_RAS [i])
493	{
494	// if end_event, restart too bottom, else decrease pointer
495	bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]);
496
497	reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1);
498	if (end_event)
499	{
500	reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context];
501	reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT;
502	}
503	else
504	{
505	reg_UPT_UPDATE [context] = (((depth==0)?_param->_size_upt_queue[context]:depth)-1);
506	}
507	}
508	else
509	{
510	// increase pointer
511	reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context];
512	}
513
514	// Free the branch with no accurate ?
515	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false)
516	reg_IS_ACCURATE [context] = true;
517	}
518	}
519	else
520	can_continue [context] = false;
521	}
522
523	// Round robin
524	reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context;
525	}
526
527	// ===================================================================
528	// =====[ BRANCH_EVENT ]==============================================
529	// ===================================================================
530	for (uint32_t i=0; i<_param->_nb_context; i++)
531	if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i]))
532	{
533	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_EVENT [%d] - Accepted",i);
534
535	#ifdef DEBUG_TEST
536	if (reg_EVENT_STATE [i] != EVENT_STATE_UPDATE_CONTEXT)
537	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state."));
538	#endif
539
540	// Change state
541	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_WAIT_END_EVENT (branch_event)",i);
542
543	reg_EVENT_STATE [i] = EVENT_STATE_WAIT_END_EVENT;
544	}
545
546	// ===================================================================
547	// =====[ EVENT ]=====================================================
548	// ===================================================================
549	for (uint32_t i=0; i<_param->_nb_context; ++i)
550	{
551	//----------------------------------------------------------------
552	// Cases
553	//----------------------------------------------------------------
554	// * EVENT_TYPE_NONE - nothing
555	// * EVENT_TYPE_MISS_SPECULATION
556	// * EVENT_STATE_END - Change state, reset pointer
557	// * EVENT_TYPE_EXCEPTION -
558	// * EVENT_STATE_EVENT - Flush upft and upt
559	// * EVENT_STATE_END - Change state, reset pointer
560	// * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update
561	// * EVENT_TYPE_SPR_ACCESS - nothing
562	// * EVENT_TYPE_MSYNC - nothing
563	// * EVENT_TYPE_PSYNC - nothing
564	// * EVENT_TYPE_CSYNC - nothing
565
566	Tevent_state_t event_state = PORT_READ(in_EVENT_STATE [i]);
567	Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]);
568	// Tdepth_t depth = PORT_READ(in_EVENT_DEPTH [i]);
569
570	// Test if end of miss
571	if ((event_state == EVENT_STATE_END) and
572	(event_type == EVENT_TYPE_MISS_SPECULATION))
573	{
574	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT");
575	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state : EVENT_STATE_END");
576	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_MISS_SPECULATION");
577
578	#ifdef DEBUG_TEST
579	if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT)
580	throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state."));
581	#endif
582
583	// Change state
584	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i);
585
586	reg_EVENT_STATE [i] = EVENT_STATE_OK;
587
588	// uint32_t bottom = reg_UPT_BOTTOM [i];
589
590	// reg_UPT_TOP [i] = bottom;
591	// reg_UPT_UPDATE [i] = bottom;
592	}
593	}
594
595	// ===================================================================
596	// =====[ FLUSH ]=====================================================
597	// ===================================================================
598
599	for (uint32_t i=0; i<_param->_nb_context; ++i)
600	{
601	if (flush_UFPT [i])
602	{
603	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Flush Update Fetch Prediction Table");
604	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",i);
605	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
606
607	// It's to accelerate miss speculation
608	if (reg_UFPT_NB_NEED_UPDATE [i] == 0)
609	{
610
611	// No entry need prediction, flush all entry -> Reset
612	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
613	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
614	reg_UFPT_BOTTOM [i] = 0;
615	reg_UFPT_TOP [i] = 0;
616	// reg_UFPT_UPDATE [i];
617	}
618	else
619	{
620	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
621	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT;
622
623	// TOP is next write slot : last slot is TOP-1
624	uint32_t top = reg_UFPT_TOP [i];
625	reg_UFPT_UPDATE [i] = ((top==0)?_param->_size_ufpt_queue[i]:top)-1;
626
627	// reg_UFPT_BOTTOM [i];
628	// reg_UFPT_TOP [i];
629	}
630
631	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [i]);
632
633	}
634	}
635
636	// ===================================================================
637	// =====[ PRINT ]=====================================================
638	// ===================================================================
639
640	#if (DEBUG >= DEBUG_TRACE)
641	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump Update_Prediction_Table");
642	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPDATE_PRIORITY : %d",reg_UPDATE_PRIORITY);
643	for (uint32_t i=0; i<_param->_nb_context; i++)
644	{
645	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]);
646	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str());
647	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x",reg_EVENT_ADDRESS_SRC [i]);
648	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST_VAL: %d" ,reg_EVENT_ADDRESS_DEST_VAL[i]);
649	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x",reg_EVENT_ADDRESS_DEST [i]);
650
651	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Fetch_Prediction_Table [%d]",i);
652	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_BOTTOM : %d",reg_UFPT_BOTTOM [i]);
653	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_TOP : %d",reg_UFPT_TOP [i]);
654	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE : %d",reg_UFPT_UPDATE [i]);
655	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
656	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
657	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x %.8x, %.1d %.1d, %.8d %.8x %.4d - %s",
658	j,
659	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition,
660	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src,
661	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest,
662	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take,
663	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate,
664	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history,
665	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras,
666	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras,
667	toString(reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state).c_str()
668	);
669
670	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Prediction_Table [%d]",i);
671	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]);
672	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]);
673	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]);
674	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]);
675	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
676	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x %.8x, %.1d %.1d %.1d, %.8d %.8x %.4d - %s",
677	j,
678	reg_UPDATE_PREDICTION_TABLE [i][j]._condition,
679	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src,
680	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest,
681	reg_UPDATE_PREDICTION_TABLE [i][j]._last_take,
682	reg_UPDATE_PREDICTION_TABLE [i][j]._good_take,
683	reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate,
684	reg_UPDATE_PREDICTION_TABLE [i][j]._history,
685	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras,
686	reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras,
687	toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str()
688	);
689	}
690	#endif
691	}
692
693
694	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
695	end_cycle ();
696	#endif
697
698	log_end(Update_Prediction_Table,FUNCTION);
699	};
700
701	}; // end namespace update_prediction_table
702	}; // end namespace prediction_unit
703	}; // end namespace front_end
704	}; // end namespace multi_front_end
705	}; // end namespace core
706
707	}; // end namespace behavioural
708	}; // end namespace morpheo
709	#endif

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