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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp @ 101

Last change on this file since 101 was 101, checked in by rosiere, 15 years ago
1) Add soc test 2) fix bug (Pc management, Decod and execute, Update prediction ...)
Property svn:keywords set to `Id`
File size: 26.6 KB

Line
1	/*
2	* $Id: test.cpp 101 2009-01-15 17:19:08Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/SelfTest/include/test.h"
10	#include "Behavioural/include/Allocation.h"
11
12	void test (string name,
13	morpheo::behavioural::core::multi_front_end::front_end::Parameters * _param)
14	{
15	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
16
17	#ifdef STATISTICS
18	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
19	#endif
20
21	Tusage_t _usage = USE_ALL;
22
23	// _usage = usage_unset(_usage,USE_SYSTEMC );
24	// _usage = usage_unset(_usage,USE_VHDL );
25	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
26	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
27	// _usage = usage_unset(_usage,USE_POSITION );
28	// _usage = usage_unset(_usage,USE_STATISTICS );
29	// _usage = usage_unset(_usage,USE_INFORMATION );
30
31	Front_end * _Front_end = new Front_end
32	(name.c_str(),
33	#ifdef STATISTICS
34	_parameters_statistics,
35	#endif
36	_param,
37	_usage);
38
39	#ifdef SYSTEMC
40	if (usage_is_set(_usage,USE_SYSTEMC))
41	{
42	/*********************************************************************
43	* Déclarations des signaux
44	*********************************************************************/
45	string rename;
46
47	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
48	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
49
50	ALLOC1_SC_SIGNAL(out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_context);
51	ALLOC1_SC_SIGNAL( in_ICACHE_REQ_ACK ," in_ICACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_context);
52	//ALLOC1_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,"out_ICACHE_REQ_THREAD_ID ",Tcontext_t ,_param->_nb_context);
53	ALLOC1_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,"out_ICACHE_REQ_PACKET_ID ",Tpacket_t ,_param->_nb_context);
54	ALLOC1_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,"out_ICACHE_REQ_ADDRESS ",Ticache_instruction_t,_param->_nb_context);
55	ALLOC1_SC_SIGNAL(out_ICACHE_REQ_TYPE ,"out_ICACHE_REQ_TYPE ",Ticache_type_t ,_param->_nb_context);
56	ALLOC1_SC_SIGNAL( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ,_param->_nb_context);
57	ALLOC1_SC_SIGNAL(out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ,_param->_nb_context);
58	//ALLOC1_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ," in_ICACHE_RSP_THREAD_ID ",Tcontext_t ,_param->_nb_context);
59	ALLOC1_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t ,_param->_nb_context);
60	ALLOC2_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION ",Ticache_instruction_t,_param->_nb_context,_param->_nb_inst_fetch[it1]);
61	ALLOC1_SC_SIGNAL( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ,_param->_nb_context);
62	ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_sum_inst_decod);
63	ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_sum_inst_decod);
64	ALLOC1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_sum_inst_decod);
65	ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_sum_inst_decod);
66	ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_sum_inst_decod);
67	ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_sum_inst_decod);
68	ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_sum_inst_decod);
69	ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_sum_inst_decod);
70	ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_sum_inst_decod);
71	ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_sum_inst_decod);
72	ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_sum_inst_decod);
73	ALLOC1_SC_SIGNAL(out_DECOD_READ_RA ,"out_DECOD_READ_RA ",Tcontrol_t ,_param->_sum_inst_decod);
74	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,"out_DECOD_NUM_REG_RA ",Tgeneral_address_t ,_param->_sum_inst_decod);
75	ALLOC1_SC_SIGNAL(out_DECOD_READ_RB ,"out_DECOD_READ_RB ",Tcontrol_t ,_param->_sum_inst_decod);
76	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,"out_DECOD_NUM_REG_RB ",Tgeneral_address_t ,_param->_sum_inst_decod);
77	ALLOC1_SC_SIGNAL(out_DECOD_READ_RC ,"out_DECOD_READ_RC ",Tcontrol_t ,_param->_sum_inst_decod);
78	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,"out_DECOD_NUM_REG_RC ",Tspecial_address_t ,_param->_sum_inst_decod);
79	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RD ,"out_DECOD_WRITE_RD ",Tcontrol_t ,_param->_sum_inst_decod);
80	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,"out_DECOD_NUM_REG_RD ",Tgeneral_address_t ,_param->_sum_inst_decod);
81	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RE ,"out_DECOD_WRITE_RE ",Tcontrol_t ,_param->_sum_inst_decod);
82	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_sum_inst_decod);
83	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_sum_inst_decod);
84	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ,_param->_sum_inst_decod);
85	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
86	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
87	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
88	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
89	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete);
90	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
91	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
92	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t );
93	ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t );
94	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t );
95	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t );
96	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t );
97	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t );
98	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t );
99	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t );
100	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t );
101	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t );
102	ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
103	ALLOC1_SC_SIGNAL( in_EVENT_ACK ," in_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
104	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS ,"out_EVENT_ADDRESS ",Taddress_t ,_param->_nb_context);
105	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,"out_EVENT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_context);
106	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,"out_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ,_param->_nb_context);
107	ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context);
108	ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL ,"out_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
109	ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK ," in_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
110	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EPCR ,"out_SPR_EVENT_EPCR ",Tspr_t ,_param->_nb_context);
111	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,"out_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_context);
112	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR ,"out_SPR_EVENT_EEAR ",Tspr_t ,_param->_nb_context);
113	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,"out_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_context);
114	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,"out_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_context);
115	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_context);
116	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_context);
117	ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context);
118	ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context);
119	ALLOC1_SC_SIGNAL(out_DEPTH_FULL ,"out_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context);
120	ALLOC1_SC_SIGNAL( in_SPR_SR_IEE ," in_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_context);
121	ALLOC1_SC_SIGNAL( in_SPR_SR_EPH ," in_SPR_SR_EPH ",Tcontrol_t ,_param->_nb_context);
122	ALLOC1_SC_SIGNAL( in_INTERRUPT_ENABLE ," in_INTERRUPT_ENABLE ",Tcontrol_t ,_param->_nb_context);
123
124	/********************************************************
125	* Instanciation
126	********************************************************/
127
128	msg(_("<%s> : Instanciation of _Front_end.\n"),name.c_str());
129
130	((_Front_end->in_CLOCK)) ((in_CLOCK));
131	((_Front_end->in_NRESET)) ((in_NRESET));
132
133	INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_VAL ,_param->_nb_context);
134	INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_REQ_ACK ,_param->_nb_context);
135	//INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_THREAD_ID ,_param->_nb_context);
136	if (_param->_have_port_ifetch_queue_ptr)
137	INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_PACKET_ID ,_param->_nb_context);
138	INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_ADDRESS ,_param->_nb_context);
139	INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_TYPE ,_param->_nb_context);
140	INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_VAL ,_param->_nb_context);
141	INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_RSP_ACK ,_param->_nb_context);
142	//INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_THREAD_ID ,_param->_nb_context);
143	if (_param->_have_port_ifetch_queue_ptr)
144	INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_PACKET_ID ,_param->_nb_context);
145	INSTANCE2_SC_SIGNAL(_Front_end, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
146	INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_ERROR ,_param->_nb_context);
147	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_VAL ,_param->_sum_inst_decod);
148	INSTANCE1_SC_SIGNAL(_Front_end, in_DECOD_ACK ,_param->_sum_inst_decod);
149	if (_param->_have_port_context_id)
150	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_CONTEXT_ID ,_param->_sum_inst_decod);
151	if (_param->_have_port_depth)
152	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_DEPTH ,_param->_sum_inst_decod);
153	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_TYPE ,_param->_sum_inst_decod);
154	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_OPERATION ,_param->_sum_inst_decod);
155	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod);
156	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod);
157	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_ADDRESS ,_param->_sum_inst_decod);
158	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod);
159	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_IMMEDIAT ,_param->_sum_inst_decod);
160	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_READ_RA ,_param->_sum_inst_decod);
161	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RA ,_param->_sum_inst_decod);
162	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_READ_RB ,_param->_sum_inst_decod);
163	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RB ,_param->_sum_inst_decod);
164	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_READ_RC ,_param->_sum_inst_decod);
165	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RC ,_param->_sum_inst_decod);
166	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_WRITE_RD ,_param->_sum_inst_decod);
167	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RD ,_param->_sum_inst_decod);
168	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_WRITE_RE ,_param->_sum_inst_decod);
169	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RE ,_param->_sum_inst_decod);
170	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_EXCEPTION_USE ,_param->_sum_inst_decod);
171	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_EXCEPTION ,_param->_sum_inst_decod);
172	INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
173	INSTANCE1_SC_SIGNAL(_Front_end,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
174	if (_param->_have_port_context_id)
175	INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
176	if (_param->_have_port_depth)
177	INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
178	INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
179	INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete);
180	INSTANCE1_SC_SIGNAL(_Front_end,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
181	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_VAL );
182	INSTANCE0_SC_SIGNAL(_Front_end,out_COMMIT_EVENT_ACK );
183	if (_param->_have_port_context_id)
184	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_CONTEXT_ID );
185	if (_param->_have_port_depth)
186	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_DEPTH );
187	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_TYPE );
188	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_IS_DELAY_SLOT );
189	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS );
190	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EPCR );
191	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
192	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EEAR );
193	INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_VAL ,_param->_nb_context);
194	INSTANCE1_SC_SIGNAL(_Front_end, in_EVENT_ACK ,_param->_nb_context);
195	INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_ADDRESS ,_param->_nb_context);
196	INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_ADDRESS_NEXT ,_param->_nb_context);
197	INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context);
198	INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_IS_DS_TAKE ,_param->_nb_context);
199	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_VAL ,_param->_nb_context);
200	INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_EVENT_ACK ,_param->_nb_context);
201	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_EPCR ,_param->_nb_context);
202	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_EEAR_WEN ,_param->_nb_context);
203	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_EEAR ,_param->_nb_context);
204	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_SR_DSX ,_param->_nb_context);
205	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context);
206	INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_ALL ,_param->_nb_context);
207	INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_MEM ,_param->_nb_context);
208	if (_param->_have_port_depth)
209	{
210	INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_MIN ,_param->_nb_context);
211	INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_MAX ,_param->_nb_context);
212	}
213	INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_FULL ,_param->_nb_context);
214	INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_SR_IEE ,_param->_nb_context);
215	INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_SR_EPH ,_param->_nb_context);
216	INSTANCE1_SC_SIGNAL(_Front_end, in_INTERRUPT_ENABLE ,_param->_nb_context);
217
218	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
219
220	Time * _time = new Time();
221
222	/********************************************************
223	* Simulation - Begin
224	********************************************************/
225
226	// Initialisation
227
228	const uint32_t seed = 0;
229	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
230
231	srand(seed);
232
233	SC_START(0);
234	LABEL("Initialisation");
235
236	for (uint32_t i=0; i<_param->_nb_context; ++i)
237	{
238	in_ICACHE_REQ_ACK [i]->write(0);
239	in_ICACHE_RSP_VAL [i]->write(0);
240	in_EVENT_ACK [i]->write(0);
241	in_SPR_EVENT_ACK [i]->write(0);
242	in_NB_INST_COMMIT_ALL [i]->write(0); // no inst
243	in_NB_INST_COMMIT_MEM [i]->write(0); // no inst
244	in_SPR_SR_IEE [i]->write(0); // interrupt disable
245	in_SPR_SR_EPH [i]->write(0); // exception msb = 0
246	in_INTERRUPT_ENABLE [i]->write(0); // no interrupt
247	}
248	for (uint32_t i=0; i<_param->_sum_inst_decod; ++i)
249	in_DECOD_ACK [i]->write(0);
250	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
251	in_BRANCH_COMPLETE_VAL [i]->write(0);
252	in_COMMIT_EVENT_VAL->write(0);
253
254
255	for (uint32_t i=0; i<_param->_nb_context; ++i)
256	{
257	TEST(Tcontrol_t,out_ICACHE_REQ_VAL [i]->read(),0);
258	TEST(Tcontrol_t,out_ICACHE_RSP_ACK [i]->read(),1); // Can accept a respons
259	TEST(Tcontrol_t,out_EVENT_VAL [i]->read(),0);
260	TEST(Tcontrol_t,out_SPR_EVENT_VAL [i]->read(),0);
261	TEST(Tdepth_t ,out_DEPTH_MIN [i]->read(),0); // no branch speculated
262	TEST(Tdepth_t ,out_DEPTH_MAX [i]->read(),0); // no branch speculated
263	TEST(Tdepth_t ,out_DEPTH_FULL [i]->read(),0); // no branch speculated
264	}
265	for (uint32_t i=0; i<_param->_sum_inst_decod; ++i)
266	TEST(Tcontrol_t,out_DECOD_VAL [i]->read(),0);
267	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
268	TEST(Tcontrol_t,out_BRANCH_COMPLETE_ACK [i]->read(),0); // can't accept (interactive)
269	TEST(Tcontrol_t,out_COMMIT_EVENT_ACK ->read(),1); // can accept
270
271	LABEL("Reset");
272	in_NRESET->write(0);
273	SC_START(5);
274	in_NRESET->write(1);
275
276	LABEL("Loop of Test");
277
278	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
279	{
280	LABEL("Iteration %d",iteration);
281
282	SC_START(1);
283	}
284
285	/********************************************************
286	* Simulation - End
287	********************************************************/
288
289	TEST_OK ("End of Simulation");
290	delete _time;
291
292	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
293
294	delete in_CLOCK;
295	delete in_NRESET;
296
297	DELETE1_SC_SIGNAL(out_ICACHE_REQ_VAL ,_param->_nb_context);
298	DELETE1_SC_SIGNAL( in_ICACHE_REQ_ACK ,_param->_nb_context);
299	//DELETE1_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,_param->_nb_context);
300	DELETE1_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,_param->_nb_context);
301	DELETE1_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,_param->_nb_context);
302	DELETE1_SC_SIGNAL(out_ICACHE_REQ_TYPE ,_param->_nb_context);
303	DELETE1_SC_SIGNAL( in_ICACHE_RSP_VAL ,_param->_nb_context);
304	DELETE1_SC_SIGNAL(out_ICACHE_RSP_ACK ,_param->_nb_context);
305	//DELETE1_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ,_param->_nb_context);
306	DELETE1_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ,_param->_nb_context);
307	DELETE2_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
308	DELETE1_SC_SIGNAL( in_ICACHE_RSP_ERROR ,_param->_nb_context);
309	DELETE1_SC_SIGNAL(out_DECOD_VAL ,_param->_sum_inst_decod);
310	DELETE1_SC_SIGNAL( in_DECOD_ACK ,_param->_sum_inst_decod);
311	DELETE1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,_param->_sum_inst_decod);
312	DELETE1_SC_SIGNAL(out_DECOD_DEPTH ,_param->_sum_inst_decod);
313	DELETE1_SC_SIGNAL(out_DECOD_TYPE ,_param->_sum_inst_decod);
314	DELETE1_SC_SIGNAL(out_DECOD_OPERATION ,_param->_sum_inst_decod);
315	DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod);
316	DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod);
317	DELETE1_SC_SIGNAL(out_DECOD_ADDRESS ,_param->_sum_inst_decod);
318	DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod);
319	DELETE1_SC_SIGNAL(out_DECOD_IMMEDIAT ,_param->_sum_inst_decod);
320	DELETE1_SC_SIGNAL(out_DECOD_READ_RA ,_param->_sum_inst_decod);
321	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,_param->_sum_inst_decod);
322	DELETE1_SC_SIGNAL(out_DECOD_READ_RB ,_param->_sum_inst_decod);
323	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,_param->_sum_inst_decod);
324	DELETE1_SC_SIGNAL(out_DECOD_READ_RC ,_param->_sum_inst_decod);
325	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,_param->_sum_inst_decod);
326	DELETE1_SC_SIGNAL(out_DECOD_WRITE_RD ,_param->_sum_inst_decod);
327	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,_param->_sum_inst_decod);
328	DELETE1_SC_SIGNAL(out_DECOD_WRITE_RE ,_param->_sum_inst_decod);
329	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,_param->_sum_inst_decod);
330	DELETE1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,_param->_sum_inst_decod);
331	DELETE1_SC_SIGNAL(out_DECOD_EXCEPTION ,_param->_sum_inst_decod);
332	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
333	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
334	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
335	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
336	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
337	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete);
338	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
339	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_VAL );
340	DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ACK );
341	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID );
342	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_DEPTH );
343	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_TYPE );
344	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT );
345	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS );
346	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR );
347	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
348	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR );
349	DELETE1_SC_SIGNAL(out_EVENT_VAL ,_param->_nb_context);
350	DELETE1_SC_SIGNAL( in_EVENT_ACK ,_param->_nb_context);
351	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context);
352	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context);
353	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context);
354	DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context);
355	DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context);
356	DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context);
357	DELETE1_SC_SIGNAL(out_SPR_EVENT_EPCR ,_param->_nb_context);
358	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,_param->_nb_context);
359	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR ,_param->_nb_context);
360	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,_param->_nb_context);
361	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context);
362	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context);
363	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context);
364	DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context);
365	DELETE1_SC_SIGNAL(out_DEPTH_MAX ,_param->_nb_context);
366	DELETE1_SC_SIGNAL(out_DEPTH_FULL ,_param->_nb_context);
367	DELETE1_SC_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context);
368	DELETE1_SC_SIGNAL( in_SPR_SR_EPH ,_param->_nb_context);
369	DELETE1_SC_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_context);
370	}
371	#endif
372
373	delete _Front_end;
374	#ifdef STATISTICS
375	delete _parameters_statistics;
376	#endif
377	}

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