Context Navigation

source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp @ 104

Last change on this file since 104 was 104, checked in by rosiere, 15 years ago
Fix Bug : 1) Load Store Unit : check big endian 2) Commit unit & RAT : add retire_event interface
Property svn:keywords set to `Id`
File size: 28.8 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Commit_unit_transition.cpp 104 2009-01-21 21:53:13Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_ooo_engine {
15	namespace ooo_engine {
16	namespace commit_unit {
17
18
19	#undef FUNCTION
20	#define FUNCTION "Commit_unit::transition"
21	void Commit_unit::transition (void)
22	{
23	log_begin(Commit_unit,FUNCTION);
24	log_function(Commit_unit,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	// Clear all bank
29	for (uint32_t i=0; i<_param->_nb_bank; i++)
30	{
31	_rob [i].clear();
32	reg_BANK_PTR [i] = 0;
33	}
34
35	// Reset pointer
36	reg_NUM_BANK_HEAD = 0;
37	reg_NUM_BANK_TAIL = 0;
38
39	// Reset counter
40	for (uint32_t i=0; i<_param->_nb_front_end; i++)
41	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
42	{
43	reg_NB_INST_COMMIT_ALL [i][j] = 0;
44	reg_NB_INST_COMMIT_MEM [i][j] = 0;
45
46	reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT;
47	reg_EVENT_FLUSH [i][j] = false;
48
49	// reg_PC_PREVIOUS [i][j] = (0x100-4)>>2;
50	reg_PC_CURRENT [i][j] = (0x100 )>>2;
51	reg_PC_CURRENT_IS_DS [i][j] = 0;
52	reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0;
53	// reg_PC_NEXT [i][j] = (0x100+4)>>2;
54	}
55
56	// Reset priority algorithm
57	_priority_insert->reset();
58	}
59	else
60	{
61	// Compute next priority
62	_priority_insert->transition();
63
64	// ===================================================================
65	// =====[ GARBAGE COLLECTOR ]=========================================
66	// ===================================================================
67	for (uint32_t i=0; i<_param->_nb_front_end; i++)
68	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
69	switch (reg_EVENT_STATE [i][j])
70	{
71	case EVENT_STATE_EVENT :
72	{
73	if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j])
74	reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ;
75	break;
76	}
77	case EVENT_STATE_WAITEND :
78	{
79	if (reg_NB_INST_COMMIT_ALL [i][j] == 0)
80	{
81	reg_EVENT_STATE [i][j] = EVENT_STATE_END;
82	reg_EVENT_FLUSH [i][j] = false;
83	}
84	break;
85	}
86	case EVENT_STATE_END :
87	{
88	reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT;
89	break;
90	}
91	// case EVENT_STATE_NO_EVENT :
92	default : break;
93	}
94
95	// ===================================================================
96	// =====[ INSERT ]====================================================
97	// ===================================================================
98	for (uint32_t i=0; i<_param->_nb_bank; i++)
99	if (internal_BANK_INSERT_VAL [i])
100	{
101	// get rename unit source and instruction.
102	uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i];
103	uint32_t y = internal_BANK_INSERT_NUM_INST [i];
104
105	if (PORT_READ(in_INSERT_VAL [x][y]))
106	{
107	log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y);
108
109	#ifdef STATISTICS
110	if (usage_is_set(_usage,USE_STATISTICS))
111	(*_stat_nb_inst_insert [x]) ++;
112	#endif
113
114	// get information
115	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0;
116	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0;
117	Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]);
118	Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]);
119	bool is_store = is_operation_memory_store(operation);
120
121	Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]);
122
123	log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id);
124	log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id);
125	log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str());
126	log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation );
127	log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception );
128
129	// Create new entry.
130	entry_t * entry = new entry_t;
131
132	entry->ptr = reg_BANK_PTR [i];
133	entry->front_end_id = front_end_id;
134	entry->context_id = context_id ;
135	entry->rename_unit_id = x;
136	entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0;
137	entry->type = type;
138	entry->operation = operation;
139	entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]);
140	entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]);
141	entry->exception = exception;
142	entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]);
143	entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store);
144	entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store);
145	entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]);
146	entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0;
147	entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]);
148	entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]);
149	entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]);
150	entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]);
151	entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]);
152	entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]);
153	entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]);
154	entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]);
155	entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]);
156	entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]);
157	entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]);
158	entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]);
159	entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]);
160	entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]);
161	entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]);
162	entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]);
163	entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]);
164
165	// Test if exception :
166	// * yes : no execute instruction, wait ROB Head
167	// * no : test type
168	// * BRANCH : l.j -> branch is ended
169	// other -> wait the execution end of branchment
170	// * MEMORY : store -> wait store is at head of ROB
171	// other -> wait end of instruction
172	// * OTHER
173	if (exception == EXCEPTION_NONE)
174	{
175	Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]);
176	// no_execute : l.j, l.nop, l.rfe
177
178	log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute);
179
180	switch (type)
181	{
182	case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END; break;}
183	case TYPE_MEMORY : {entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;}
184	default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
185	}
186	}
187	else
188	{
189	// Have an exception : wait head of ROB
190
191	// in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap
192
193	entry->state = ROB_END_EXCEPTION_WAIT_HEAD;
194	}
195
196	// Push in rob
197	_rob[i].push_back(entry);
198
199	// Update counter and pointer
200	reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++;
201	if (type == TYPE_MEMORY)
202	reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++;
203
204	reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+1)%_param->_nb_bank;
205	reg_BANK_PTR [i] = (reg_BANK_PTR [i]+1)%_param->_size_bank;
206	}
207	}
208
209	// ===================================================================
210	// =====[ COMMIT ]====================================================
211	// ===================================================================
212
213	#ifdef STATISTICS
214	if (usage_is_set(_usage,USE_STATISTICS))
215	(*_stat_nb_inst_commit_conflit_access) += internal_BANK_COMMIT_CONFLIT_ACCESS;
216	#endif
217
218	for (uint32_t i=0; i<_param->_nb_bank; i++)
219	for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++)
220	if (internal_BANK_COMMIT_VAL [i][j])
221	{
222	// An instruction is executed. Change state of this instruction
223
224	uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j];
225
226	if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x]))
227	{
228	log_printf(TRACE,Commit_unit,FUNCTION," * COMMIT [%d]",x);
229
230	#ifdef STATISTICS
231	if (usage_is_set(_usage,USE_STATISTICS))
232	(*_stat_nb_inst_commit) ++;
233	#endif
234
235	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i);
236
237	// find the good entry !!!
238	entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j];
239
240	//Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]);
241	//Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]);
242	Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]);
243
244	rob_state_t state = entry->state;
245	Tcontext_t front_end_id = entry->front_end_id;
246	Tcontext_t context_id = entry->context_id;
247
248	// change state : test exception_use
249	// * test if exception : exception and mask
250
251	bool have_exception = false;
252	bool have_miss_speculation = false;
253
254	if (exception != EXCEPTION_NONE)
255	{
256	// Test if the instruction is a load and is a miss speculation (load is commit, but they have an dependence with a previous store)
257	have_miss_speculation = (exception == EXCEPTION_MEMORY_MISS_SPECULATION);
258
259	switch (entry->exception_use)
260	{
261	// Have overflow exception if bit overflow enable is set.
262	case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;}
263	case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
264	(exception == EXCEPTION_DATA_TLB ) or
265	(exception == EXCEPTION_DATA_PAGE) or
266	(exception == EXCEPTION_ALIGNMENT)); break;};
267	case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
268	(exception == EXCEPTION_DATA_TLB ) or
269	(exception == EXCEPTION_DATA_PAGE)); break;};
270	case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;};
271	case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;};
272	case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;};
273	case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;};
274	case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;};
275	case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;};
276	case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;};
277	// Case already manage (decod stage -> in insert in ROB)
278	case EXCEPTION_USE_TRAP : {have_exception = false; exception = EXCEPTION_NONE; break;};
279	case EXCEPTION_USE_NONE : {have_exception = false; exception = EXCEPTION_NONE; break;};
280	case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; exception = EXCEPTION_NONE; break;};
281	case EXCEPTION_USE_SYSCALL : {have_exception = false; exception = EXCEPTION_NONE; break;};
282	default :
283	{
284	throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n"));
285	break;
286	}
287	}
288	}
289
290	switch (state)
291	{
292	// Branch ...
293	case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;}
294	// Store KO
295	case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;}
296	// Store OK, Load and other instruction
297	case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_MISS:ROB_END_OK_SPECULATIVE); break;}
298	default :
299	{
300	throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str()));
301	break;
302	}
303	}
304
305	// update Re Order Buffer
306	entry->state = state;
307	entry->exception = exception;
308	entry->flags = PORT_READ(in_COMMIT_FLAGS [x]);
309	entry->no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]);
310	entry->data_commit = PORT_READ(in_COMMIT_ADDRESS [x]);
311	}
312	}
313
314	// ===================================================================
315	// =====[ RETIRE ]====================================================
316	// ===================================================================
317	for (uint32_t i=0; i<_param->_nb_bank; i++)
318	if (internal_BANK_RETIRE_VAL [i])
319	{
320	uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [i];
321	uint32_t y = internal_BANK_RETIRE_NUM_INST [i];
322
323	log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y);
324
325	#ifdef DEBUG_TEST
326	if (not PORT_READ(in_RETIRE_ACK [x][y]))
327	throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n"));
328	#endif
329
330	entry_t * entry = _rob [i].front();
331	rob_state_t state = entry->state;
332
333	#ifdef STATISTICS
334	if (usage_is_set(_usage,USE_STATISTICS))
335	{
336	if (state == ROB_END_OK)
337	(*_stat_nb_inst_retire_ok [x]) ++;
338	else
339	(*_stat_nb_inst_retire_ko [x]) ++;
340	}
341	#endif
342
343	Tcontext_t front_end_id = entry->front_end_id;
344	Tcontext_t context_id = entry->context_id ;
345	Ttype_t type = entry->type ;
346
347	if (state == ROB_END_BRANCH_MISS)
348	{
349	reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT;
350	reg_EVENT_FLUSH [front_end_id][context_id] = true;
351
352	// TODO Compute address !!!!!!!!!!!
353	}
354
355	// Update nb_inst
356	reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --;
357	if (type == TYPE_MEMORY)
358	reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --;
359
360	reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank;
361
362	_rob [i].pop_front();
363	delete entry;
364	}
365
366	// ===================================================================
367	// =====[ REEXECUTE ]=================================================
368	// ===================================================================
369	if (internal_REEXECUTE_VAL [0] and PORT_READ(in_REEXECUTE_ACK [0]))
370	{
371	log_printf(TRACE,Commit_unit,FUNCTION," * REEXECUTE [0]");
372
373	uint32_t num_bank = internal_REEXECUTE_NUM_BANK [0];
374
375	entry_t * entry = _rob [num_bank].front();
376	rob_state_t state = entry->state;
377
378	switch (state)
379	{
380	case ROB_STORE_HEAD_OK : {state = ROB_OTHER_WAIT_END; break; }
381	case ROB_STORE_HEAD_KO : {state = ROB_MISS_WAIT_END ; break; }
382	default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));}
383	}
384
385	entry->state = state;
386	}
387
388	// ===================================================================
389	// =====[ BRANCH_COMPLETE ]===========================================
390	// ===================================================================
391	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
392	if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i]))
393	{
394	log_printf(TRACE,Commit_unit,FUNCTION," * BRANCH_COMPLETE [%d]",i);
395	log_printf(TRACE,Commit_unit,FUNCTION," * miss_prediction : %d",PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]));
396
397	uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i];
398
399	entry_t * entry = _rob [num_bank].front();
400
401	#ifdef DEBUG_TEST
402	rob_state_t state = entry->state;
403	if (state != ROB_BRANCH_COMPLETE)
404	throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n"));
405	#endif
406
407	entry->state = (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE;
408	// entry->state = ROB_END_OK_SPECULATIVE;
409	}
410
411	// ===================================================================
412	// =====[ UPDATE ]====================================================
413	// ===================================================================
414	{
415	// Not yet implemented
416	}
417
418	// ===================================================================
419	// =====[ EVENT ]=====================================================
420	// ===================================================================
421	{
422	// Not yet implemented
423	}
424
425	// ===================================================================
426	// =====[ DEPTH - HEAD ]==============================================
427	// ===================================================================
428	for (uint32_t i=0; i<_param->_nb_bank; i++)
429	if (not _rob[i].empty())
430	{
431	// Scan all instruction in windows and test if instruction is speculative
432	entry_t * entry = _rob [i].front();
433
434	Tcontext_t front_end_id = entry->front_end_id;
435	Tcontext_t context_id = entry->context_id ;
436	rob_state_t state = entry->state;
437	Tdepth_t depth = entry->depth;
438
439	Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0;
440	// Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0;
441	// Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]);
442
443	// is a valid instruction ?
444	// If DEPTH_CURRENT :
445	// equal at DEPTH_MIN -> not speculative
446	// not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss
447	// include ]DEPTH_MIN:DEPTH_MAX] -> speculative
448
449	// All case
450	// ....... min ...X... max ....... OK
451	// ....... min ....... max ...X... KO
452	// ...X... min ....... max ....... KO
453	// ....... max ....... min ...X... OK
454	// ...X... max ....... min ....... OK
455	// ....... max ...X... min ....... KO
456
457	// Tcontrol_t is_valid = ((depth == depth_min) or
458	// depth_full or
459	// ((depth_min <= depth_max)?
460	// ((depth >= depth_min) and (depth <=depth_max)):
461	// ((depth >= depth_min) or (depth <=depth_max))));
462
463	bool flush = reg_EVENT_FLUSH [front_end_id][context_id];
464	Tcontrol_t is_valid = ((depth == depth_min) and not flush);
465
466	log_printf(TRACE,Commit_unit,FUNCTION," * HEAD [%d]",i);
467	log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d",is_valid);
468	log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth );
469	log_printf(TRACE,Commit_unit,FUNCTION," * depth_min : %d",depth_min);
470	// log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max);
471	log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush);
472
473	//------------------------------------------------------
474	// test if instruction is miss speculative
475	//------------------------------------------------------
476	if (not is_valid)
477	{
478	switch (state)
479	{
480	case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;}
481	case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;}
482	case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;}
483	case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;}
484	//case ROB_STORE_WAIT_HEAD_KO : {state = ; break;}
485	case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;}
486	case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;}
487	case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;}
488	case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;}
489
490	// don't change
491	case ROB_STORE_HEAD_KO : {break;}
492	case ROB_MISS_WAIT_END : {break;}
493	case ROB_END_MISS : {break;}
494
495	// can't have miss speculation
496	case ROB_STORE_HEAD_OK :
497	case ROB_END_OK :
498	case ROB_END_KO :
499	case ROB_END_BRANCH_MISS :
500	case ROB_END_EXCEPTION :
501	default :
502	{
503	throw ERRORMORPHEO(FUNCTION,_("Miss Speculation : Invalide state.\n"));
504	break;
505	}
506	}
507	}
508
509	//------------------------------------------------------
510	// test if instruction is not speculative
511	//------------------------------------------------------
512	if (entry->depth == depth_min)
513	{
514	switch (state)
515	{
516	case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;}
517	case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;}
518	case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;}
519	default : {break;}
520	}
521	}
522
523	//------------------------------------------------------
524	// test if instruction is store and head
525	//------------------------------------------------------
526	if (i == reg_NUM_BANK_HEAD)
527	{
528	switch (state)
529	{
530	case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;}
531	case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION; break;}
532	default : {break;}
533	}
534	}
535
536	entry->state = state;
537	}
538	}
539
540	// ===================================================================
541	// =====[ OTHER ]=====================================================
542	// ===================================================================
543
544	log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)");
545	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD);
546	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL);
547
548	for (uint32_t i=0; i<_param->_nb_front_end; i++)
549	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
550	{
551	log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] num_inst_all : %d, num_inst_mem : %d",i,j,reg_NB_INST_COMMIT_ALL[i][j],reg_NB_INST_COMMIT_MEM[i][j]);
552	log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] state : %s",i,j,toString(reg_EVENT_STATE [i][j]).c_str());
553	}
554
555	for (uint32_t i=0; i<_param->_nb_bank; i++)
556	{
557	log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",i,(int)_rob[i].size(), reg_BANK_PTR [i]);
558
559	#ifdef STATISTICS
560	if (usage_is_set(_usage,USE_STATISTICS))
561	*(_stat_bank_nb_inst [i]) += _rob[i].size();
562	#endif
563
564	uint32_t x=0;
565	for (std::list<entry_t*>::iterator it=_rob[i].begin();
566	it!=_rob[i].end();
567	it++)
568	{
569	log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.8x (%.8x) %.1d, %.1d %.4d, %.1d %.4d, %s - %d",
570	x,
571	(*it)->front_end_id ,
572	(*it)->context_id ,
573	(*it)->rename_unit_id ,
574	(*it)->depth ,
575	(*it)->type ,
576	(*it)->operation ,
577	(*it)->address ,
578	(*it)->address << 2 ,
579	(*it)->is_delay_slot ,
580	(*it)->use_store_queue ,
581	(*it)->store_queue_ptr_write ,
582	(*it)->use_load_queue ,
583	(*it)->load_queue_ptr_write ,
584	toString((*it)->state).c_str() ,
585	(*it)->ptr );
586	log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ",
587	(*it)->read_ra ,
588	(*it)->num_reg_ra_log ,
589	(*it)->num_reg_ra_phy ,
590	(*it)->read_rb ,
591	(*it)->num_reg_rb_log ,
592	(*it)->num_reg_rb_phy ,
593	(*it)->read_rc ,
594	(*it)->num_reg_rc_log ,
595	(*it)->num_reg_rc_phy ,
596	(*it)->write_rd ,
597	(*it)->num_reg_rd_log ,
598	(*it)->num_reg_rd_phy_old ,
599	(*it)->num_reg_rd_phy_new ,
600	(*it)->write_re ,
601	(*it)->num_reg_re_log ,
602	(*it)->num_reg_re_phy_old ,
603	(*it)->num_reg_re_phy_new );
604
605	log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x",
606	(*it)->exception_use ,
607	(*it)->exception ,
608	(*it)->flags ,
609	(*it)->no_sequence ,
610	(*it)->data_commit
611	);
612
613	x++;
614	}
615	}
616
617	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
618	end_cycle ();
619	#endif
620
621	log_end(Commit_unit,FUNCTION);
622	};
623
624	}; // end namespace commit_unit
625	}; // end namespace ooo_engine
626	}; // end namespace multi_ooo_engine
627	}; // end namespace core
628
629	}; // end namespace behavioural
630	}; // end namespace morpheo
631	#endif

Note: See TracBrowser for help on using the repository browser.

Download in other formats: