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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp @ 114

Last change on this file since 114 was 114, checked in by rosiere, 15 years ago
1) Fix bug with previous commit 2) Add test libc 3) Change Dhrystone
Property svn:keywords set to `Id`
File size: 41.4 KB

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1	#ifdef SYSTEMC
2	/*
3	* $Id: Commit_unit_transition.cpp 114 2009-04-16 22:35:37Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h"
10	#include "Behavioural/include/Simulation.h"
11
12	namespace morpheo {
13	namespace behavioural {
14	namespace core {
15	namespace multi_ooo_engine {
16	namespace ooo_engine {
17	namespace commit_unit {
18
19
20	#undef FUNCTION
21	#define FUNCTION "Commit_unit::transition"
22	void Commit_unit::transition (void)
23	{
24	log_begin(Commit_unit,FUNCTION);
25	log_function(Commit_unit,FUNCTION,_name.c_str());
26
27	if (PORT_READ(in_NRESET) == 0)
28	{
29	// Clear all bank
30	for (uint32_t i=0; i<_param->_nb_bank; i++)
31	{
32	_rob [i].clear();
33	reg_BANK_PTR [i] = 0;
34	}
35
36	// Reset pointer
37	reg_NUM_BANK_HEAD = 0;
38	reg_NUM_BANK_TAIL = 0;
39
40	// Reset counter
41	for (uint32_t i=0; i<_param->_nb_front_end; i++)
42	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
43	{
44	_nb_cycle_idle [i][j] = 0;
45
46	reg_NB_INST_COMMIT_ALL [i][j] = 0;
47	reg_NB_INST_COMMIT_MEM [i][j] = 0;
48
49	reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT;
50	reg_EVENT_FLUSH [i][j] = false;
51	reg_EVENT_STOP [i][j] = false;
52
53	// reg_PC_PREVIOUS [i][j] = (0x100-4)>>2;
54	reg_PC_CURRENT [i][j] = (0x100 )>>2;
55	reg_PC_CURRENT_IS_DS [i][j] = 0;
56	reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0;
57	reg_PC_NEXT [i][j] = (0x100+4)>>2;
58	}
59
60	// Reset priority algorithm
61	_priority_insert->reset();
62	}
63	else
64	{
65	// Increase number idle cycle
66	for (uint32_t i=0; i<_param->_nb_front_end; i++)
67	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
68	_nb_cycle_idle [i][j] ++;
69
70	// Compute next priority
71	_priority_insert->transition();
72
73	// ===================================================================
74	// =====[ GARBAGE COLLECTOR ]=========================================
75	// ===================================================================
76	for (uint32_t i=0; i<_param->_nb_front_end; i++)
77	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
78	switch (reg_EVENT_STATE [i][j])
79	{
80	case EVENT_STATE_EVENT :
81	{
82	if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j])
83	reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ;
84	break;
85	}
86	case EVENT_STATE_WAITEND :
87	{
88	Tcounter_t nb_inst_all = PORT_READ(in_NB_INST_DECOD_ALL [i][j]) + reg_NB_INST_COMMIT_ALL [i][j];
89	if (nb_inst_all == 0)
90	{
91	reg_EVENT_STATE [i][j] = EVENT_STATE_END;
92	reg_EVENT_FLUSH [i][j] = false;
93	//reg_EVENT_STOP [i][j] = false;
94	}
95	break;
96	}
97	case EVENT_STATE_END :
98	{
99	reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT;
100	break;
101	}
102	// case EVENT_STATE_NO_EVENT :
103	default : break;
104	}
105
106	// ===================================================================
107	// =====[ INSERT ]====================================================
108	// ===================================================================
109	for (uint32_t i=0; i<_param->_nb_bank; i++)
110	if (internal_BANK_INSERT_VAL [i])
111	{
112	// get rename unit source and instruction.
113	uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i];
114	uint32_t y = internal_BANK_INSERT_NUM_INST [i];
115
116	if (PORT_READ(in_INSERT_VAL [x][y]))
117	{
118	log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y);
119
120	// get information
121	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0;
122	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0;
123	Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]);
124	Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]);
125	bool is_store = is_operation_memory_store(operation);
126
127	Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]);
128
129	log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id);
130	log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id);
131	log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str());
132	log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation );
133	log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception );
134
135	// Create new entry.
136	entry_t * entry = new entry_t;
137
138	entry->ptr = reg_BANK_PTR [i];
139	entry->front_end_id = front_end_id;
140	entry->context_id = context_id ;
141	entry->rename_unit_id = x;
142	entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0;
143	entry->type = type;
144	entry->operation = operation;
145	entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]);
146	// entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]);
147	entry->exception = exception;
148	entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]);
149	entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store);
150	entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store);
151	entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]);
152	entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0;
153	entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]);
154	entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]);
155	entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]);
156	entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]);
157	entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]);
158	entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]);
159	entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]);
160	entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]);
161	entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]);
162	entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]);
163	entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]);
164	entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]);
165	entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]);
166	entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]);
167	entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]);
168	entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]);
169	entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]);
170	entry->no_sequence = type == TYPE_BRANCH;
171	entry->speculative = true;
172	#ifdef DEBUG
173	entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]);
174	#endif
175	entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]);
176	#ifdef DEBUG
177	entry->cycle_rob_in = simulation_cycle();
178	entry->cycle_commit = simulation_cycle();
179	#endif
180
181	// Test if exception :
182	// * yes : no execute instruction, wait ROB Head
183	// * no : test type
184	// * BRANCH : l.j -> branch is ended
185	// other -> wait the execution end of branchment
186	// * MEMORY : store -> wait store is at head of ROB
187	// other -> wait end of instruction
188	// * OTHER
189
190	// bool flush = reg_EVENT_FLUSH [front_end_id][context_id];
191
192	// log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush);
193
194	// if (flush)
195	// {
196	// entry->state = ROB_END_MISS; // All type (branch, memory and others), because, is not execute
197	// }
198	// else
199	{
200	if (exception == EXCEPTION_NONE)
201	{
202	Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]);
203	// no_execute : l.j, l.nop, l.rfe
204
205	log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute);
206
207	switch (type)
208	{
209	case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END ; break;}
210	case TYPE_MEMORY : {entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;}
211	default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
212	}
213	}
214	else
215	{
216	// Have an exception : wait head of ROB
217
218	// in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap
219
220	entry->state = ROB_END_EXCEPTION_WAIT_HEAD;
221	}
222	}
223
224	#ifdef STATISTICS
225	if (usage_is_set(_usage,USE_STATISTICS))
226	(*_stat_nb_inst_insert [x]) ++;
227	#endif
228
229	// Push in rob
230	_rob[i].push_back(entry);
231
232	// Update counter and pointer
233	reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++;
234	if (type == TYPE_MEMORY)
235	reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++;
236
237	reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+1)%_param->_nb_bank;
238	reg_BANK_PTR [i] = (reg_BANK_PTR [i]+1)%_param->_size_bank;
239	}
240	}
241
242	// ===================================================================
243	// =====[ COMMIT ]====================================================
244	// ===================================================================
245
246	#ifdef STATISTICS
247	if (usage_is_set(_usage,USE_STATISTICS))
248	(*_stat_nb_inst_commit_conflit_access) += internal_BANK_COMMIT_CONFLIT_ACCESS;
249	#endif
250
251	for (uint32_t i=0; i<_param->_nb_bank; i++)
252	for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++)
253	if (internal_BANK_COMMIT_VAL [i][j])
254	{
255	// An instruction is executed. Change state of this instruction
256
257	uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j];
258
259	if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x]))
260	{
261	log_printf(TRACE,Commit_unit,FUNCTION," * COMMIT [%d]",x);
262
263	#ifdef STATISTICS
264	if (usage_is_set(_usage,USE_STATISTICS))
265	(*_stat_nb_inst_commit) ++;
266	#endif
267
268	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i);
269
270	// find the good entry !!!
271	entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j];
272
273	//Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]);
274	//Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]);
275	Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]);
276
277	rob_state_t state = entry->state;
278	Tcontext_t front_end_id = entry->front_end_id;
279	Tcontext_t context_id = entry->context_id;
280
281	// change state : test exception_use
282	// * test if exception : exception and mask
283
284	bool have_exception = false;
285	bool have_miss_speculation = false;
286
287	if (exception != EXCEPTION_NONE)
288	{
289	// Test if the instruction is a load and is a miss speculation (load is commit, but they have an dependence with a previous store)
290	have_miss_speculation = (exception == EXCEPTION_MEMORY_MISS_SPECULATION);
291
292	switch (entry->exception_use)
293	{
294	// Have overflow exception if bit overflow enable is set.
295	case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;}
296	case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
297	(exception == EXCEPTION_DATA_TLB ) or
298	(exception == EXCEPTION_DATA_PAGE) or
299	(exception == EXCEPTION_ALIGNMENT)); break;};
300	case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
301	(exception == EXCEPTION_DATA_TLB ) or
302	(exception == EXCEPTION_DATA_PAGE)); break;};
303	case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;};
304	case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;};
305	case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;};
306	case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;};
307	case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;};
308	case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;};
309	case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;};
310	// Case already manage (decod stage -> in insert in ROB)
311	case EXCEPTION_USE_TRAP : {have_exception = false; exception = EXCEPTION_NONE; break;};
312	case EXCEPTION_USE_NONE : {have_exception = false; exception = EXCEPTION_NONE; break;};
313	case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; exception = EXCEPTION_NONE; break;};
314	case EXCEPTION_USE_SYSCALL : {have_exception = false; exception = EXCEPTION_NONE; break;};
315	default :
316	{
317	throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n"));
318	break;
319	}
320	}
321	}
322
323	switch (state)
324	{
325	// Branch ...
326	case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;}
327	// Store KO
328	case ROB_EVENT_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;}
329	// Store OK, Load and other instruction
330	case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_LOAD_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE); break;}
331	default :
332	{
333	throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str()));
334	break;
335	}
336	}
337
338	if ((have_exception or have_miss_speculation) and
339	(reg_EVENT_FLUSH [entry->front_end_id][entry->context_id] == 0))
340	reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true;
341
342	// update Re Order Buffer
343	entry->state = state;
344	entry->exception = exception;
345	entry->flags = PORT_READ(in_COMMIT_FLAGS [x]);
346	entry->no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]);
347	// jalr, jr : address_dest is in register
348	if ((entry->type == TYPE_BRANCH) and
349	(entry->operation == OPERATION_BRANCH_L_JALR) and
350	(entry->read_rb))
351	entry->address_next = PORT_READ(in_COMMIT_ADDRESS [x]);
352
353	#ifdef DEBUG
354	entry->cycle_commit = simulation_cycle();
355	#endif
356	}
357	}
358
359	// ===================================================================
360	// =====[ RETIRE ]====================================================
361	// ===================================================================
362	for (uint32_t i=0; i<_param->_nb_bank; i++)
363	{
364	uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank;
365
366	if (internal_BANK_RETIRE_VAL [num_bank])
367	{
368	uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank];
369	uint32_t y = internal_BANK_RETIRE_NUM_INST [num_bank];
370
371	log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y);
372	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",num_bank );
373
374	#ifdef DEBUG_TEST
375	if (not PORT_READ(in_RETIRE_ACK [x][y]))
376	throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n"));
377	#endif
378
379	entry_t * entry = _rob [num_bank].front();
380	rob_state_t state = entry->state;
381
382	Tcontext_t front_end_id = entry->front_end_id;
383	Tcontext_t context_id = entry->context_id ;
384	uint32_t num_thread = _param->_translate_num_context_to_num_thread [front_end_id][context_id];
385	Ttype_t type = entry->type ;
386	bool retire_ok = false;
387
388	log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id );
389	log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id );
390	log_printf(TRACE,Commit_unit,FUNCTION," * rob_ptr : %d",((num_bank << _param->_shift_num_bank) \| entry->ptr));
391	log_printf(TRACE,Commit_unit,FUNCTION," * num_thread : %d",num_thread );
392	log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str());
393	log_printf(TRACE,Commit_unit,FUNCTION," * state : %s",toString(state).c_str());
394
395	if ((state == ROB_END_OK ) or
396	// (state == ROB_END_KO ) or
397	(state == ROB_END_BRANCH_MISS) or
398	(state == ROB_END_LOAD_MISS )// or
399	// (state == ROB_END_MISS ) or
400	// (state == ROB_END_EXCEPTION )
401	)
402	{
403	log_printf(TRACE,Commit_unit,FUNCTION," * retire_ok");
404
405	retire_ok = true;
406
407	// reg_PC_PREVIOUS [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id];
408	reg_PC_CURRENT [front_end_id][context_id] = reg_PC_NEXT [front_end_id][context_id];
409	reg_PC_CURRENT_IS_DS [front_end_id][context_id] = entry->type == TYPE_BRANCH;
410	reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence;
411	reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1);
412
413	// if (entry->address_next != reg_PC_NEXT [front_end_id][context_id])
414	// throw ERRORMORPHEO(FUNCTION,toString(_("Retire : Instruction's address_next (%.8x) is different of commit_unit's address_next (%.8x)"),entry->address_next,reg_PC_NEXT [front_end_id][context_id]));
415	}
416
417	if ((state == ROB_END_BRANCH_MISS) or
418	(state == ROB_END_LOAD_MISS))
419	{
420	reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT;
421	reg_EVENT_FLUSH [front_end_id][context_id] = true;
422	reg_EVENT_STOP [front_end_id][context_id] = false;
423	}
424
425	#if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true)
426	// log file
427	instruction_log_file [num_thread]
428	<< "[" << simulation_cycle() << "] "
429	<< std::hex
430	<< (entry->address<<2) << " (" << (entry->address) << ") "
431	<< std::dec
432	<< "[" << entry->cycle_rob_in << ", " << entry->cycle_commit << "] "
433	<< "{" << ((retire_ok)?" OK ":"!KO!") << "} "
434	<< std::endl;
435	#endif
436
437	// Update nb_inst
438	reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --;
439	if (type == TYPE_MEMORY)
440	reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --;
441
442	reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank;
443
444	_rob [num_bank].pop_front();
445	delete entry;
446
447	// Transaction on retire interface : reset watch dog timer.
448	_nb_cycle_idle [front_end_id][context_id] = 0;
449
450	// Increase stop condition
451	if (retire_ok)
452	_simulation_nb_instruction_commited [num_thread] ++;
453
454	#ifdef STATISTICS
455	if (usage_is_set(_usage,USE_STATISTICS))
456	{
457	(*_stat_nb_inst_retire [x]) ++;
458
459	if (retire_ok)
460	{
461	(*_stat_nb_inst_retire_ok [num_thread]) ++;
462	(*_stat_nb_inst_type [type] ) ++;
463	}
464	else
465	(*_stat_nb_inst_retire_ko [num_thread]) ++;
466	}
467	#endif
468	}
469	}
470
471	// ===================================================================
472	// =====[ REEXECUTE ]=================================================
473	// ===================================================================
474	if (internal_REEXECUTE_VAL [0] and PORT_READ(in_REEXECUTE_ACK [0]))
475	{
476	log_printf(TRACE,Commit_unit,FUNCTION," * REEXECUTE [0]");
477
478	uint32_t num_bank = internal_REEXECUTE_NUM_BANK [0];
479
480	entry_t * entry = _rob [num_bank].front();
481	rob_state_t state = entry->state;
482
483	switch (state)
484	{
485	case ROB_STORE_HEAD_OK : {state = ROB_OTHER_WAIT_END; break; }
486	case ROB_STORE_HEAD_KO : {state = ROB_EVENT_WAIT_END; break; }
487	default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));}
488	}
489
490	entry->state = state;
491	}
492
493	// ===================================================================
494	// =====[ BRANCH_COMPLETE ]===========================================
495	// ===================================================================
496	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
497	if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i]))
498	{
499	log_printf(TRACE,Commit_unit,FUNCTION," * BRANCH_COMPLETE [%d]",i);
500	log_printf(TRACE,Commit_unit,FUNCTION," * miss_prediction : %d",PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]));
501
502	uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i];
503
504	entry_t * entry = _rob [num_bank].front();
505
506	#ifdef DEBUG_TEST
507	rob_state_t state = entry->state;
508	if (state != ROB_BRANCH_COMPLETE)
509	throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n"));
510	#endif
511	Tcontrol_t miss = PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]);
512
513	entry->state = (miss)?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE;
514
515	if (miss and (reg_EVENT_FLUSH [entry->front_end_id][entry->context_id] == 0))
516	reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true;
517
518
519	// entry->state = ROB_END_OK_SPECULATIVE;
520	}
521
522	// ===================================================================
523	// =====[ UPDATE ]====================================================
524	// ===================================================================
525	if (internal_UPDATE_VAL and PORT_READ(in_UPDATE_ACK))
526	{
527	log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE");
528
529	entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front();
530
531	switch (entry->state)
532	{
533	// case ROB_END_EXCEPTION_UPDATE :
534	// {
535	// entry->state = ROB_END_KO;
536	// throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n"));
537	// break;
538	// }
539	case ROB_END_LOAD_MISS_UPDATE :
540	{
541	log_printf(TRACE,Commit_unit,FUNCTION," * ROB_END_LOAD_MISS_UPDATE");
542
543	entry->state = ROB_END_LOAD_MISS;
544	break;
545	}
546	default :
547	{
548	throw ERRORMORPHEO(FUNCTION,_("Update : invalid state.\n"));
549	break;
550	}
551	}
552
553	}
554
555	// ===================================================================
556	// =====[ EVENT ]=====================================================
557	// ===================================================================
558	// for (uint32_t i=0; i < _param->_nb_front_end; ++i)
559	// for (uint32_t j=0; j < _param->_nb_context[i]; ++j)
560	// if (PORT_READ(in_EVENT_VAL [i][j]) and internal_EVENT_ACK [i][j])
561	// {
562	// log_printf(TRACE,Commit_unit,FUNCTION," * EVENT [%d][%d]",i,j);
563
564	// reg_PC_CURRENT [i][j] = PORT_READ(in_EVENT_ADDRESS [i][j]);
565	// reg_PC_CURRENT_IS_DS [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); // ??
566	// reg_PC_CURRENT_IS_DS_TAKE [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]);
567	// reg_PC_NEXT [i][j] = PORT_READ(in_EVENT_ADDRESS_NEXT [i][j]);
568	// // PORT_READ(in_EVENT_ADDRESS_NEXT_VAL [i][j]);
569	// }
570
571	// ===================================================================
572	// =====[ DEPTH - HEAD ]==============================================
573	// ===================================================================
574	for (uint32_t i=0; i<_param->_nb_bank; i++)
575	if (not _rob[i].empty())
576	{
577	// Scan all instruction in windows and test if instruction is speculative
578	entry_t * entry = _rob [i].front();
579
580	Tcontext_t front_end_id = entry->front_end_id;
581	Tcontext_t context_id = entry->context_id ;
582	rob_state_t state = entry->state;
583	Tdepth_t depth = entry->depth;
584
585	Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0;
586	Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0;
587	Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]);
588
589	// is a valid instruction ?
590	// If DEPTH_CURRENT :
591	// equal at DEPTH_MIN -> not speculative
592	// not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss
593	// include ]DEPTH_MIN:DEPTH_MAX] -> speculative
594
595	// All case
596	// ....... min ...X... max ....... OK
597	// ....... min ....... max ...X... KO
598	// ...X... min ....... max ....... KO
599	// ....... max ....... min ...X... OK
600	// ...X... max ....... min ....... OK
601	// ....... max ...X... min ....... KO
602
603	bool flush = reg_EVENT_FLUSH [front_end_id][context_id];
604	bool speculative = entry->speculative and not (depth == depth_min);
605	Tcontrol_t is_valid = ((not speculative or
606	(speculative and (depth_full or // all is valid
607	((depth_min <= depth_max)? // test if depth is overflow
608	((depth >= depth_min) and (depth <=depth_max)):
609	((depth >= depth_min) or (depth <=depth_max))))))
610	and not flush);
611
612	// Tcontrol_t is_valid = ((depth == depth_min) and not flush);
613
614	log_printf(TRACE,Commit_unit,FUNCTION," * HEAD [%d]",i);
615	log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d ((depth == depth_min) and not flush)",is_valid);
616	log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth );
617	log_printf(TRACE,Commit_unit,FUNCTION," * depth_min : %d",depth_min);
618	log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max);
619	log_printf(TRACE,Commit_unit,FUNCTION," * depth_full : %d",depth_full);
620	log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush);
621
622	//------------------------------------------------------
623	// test if instruction is miss speculative
624	//------------------------------------------------------
625	if (not is_valid)
626	{
627	switch (state)
628	{
629	case ROB_BRANCH_WAIT_END : {state = ROB_EVENT_WAIT_END; break;}
630	case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;}
631	case ROB_END_BRANCH_MISS :
632	case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;}
633	case ROB_END_LOAD_MISS_UPDATE :
634	case ROB_END_LOAD_MISS :
635	case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;}
636	case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO ; break;}
637	//case ROB_STORE_WAIT_HEAD_KO : {state = ; break;}
638	case ROB_OTHER_WAIT_END : {state = ROB_EVENT_WAIT_END; break;}
639	case ROB_END_OK :
640	case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;}
641	case ROB_END_KO :
642	case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;}
643	case ROB_END_EXCEPTION_UPDATE :
644	case ROB_END_EXCEPTION :
645	case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;}
646
647	// don't change
648	case ROB_STORE_HEAD_KO : {break;}
649	case ROB_EVENT_WAIT_END : {break;}
650	case ROB_END_MISS : {break;}
651
652	// can't have miss speculation
653	case ROB_STORE_HEAD_OK :
654	default :
655	{
656	throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str()));
657	break;
658	}
659	}
660	}
661
662	//------------------------------------------------------
663	// test if instruction is not speculative
664	//------------------------------------------------------
665	entry->speculative = speculative;
666	// if (entry->depth == depth_min)
667	if (not speculative)
668	{
669	switch (state)
670	{
671	case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;}
672	case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;}
673	case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;}
674	case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;}
675	default : {break;} // else, no change
676	}
677	}
678
679	//------------------------------------------------------
680	// test if instruction is store and head
681	//------------------------------------------------------
682	if (i == reg_NUM_BANK_HEAD)
683	{
684	switch (state)
685	{
686	case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;}
687	case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;}
688	default : {break;} // else, no change
689	}
690	}
691
692	entry->state = state;
693	}
694	}
695
696	// ===================================================================
697	// =====[ OTHER ]=====================================================
698	// ===================================================================
699
700	#ifdef STATISTICS
701	for (uint32_t i=0; i<_param->_nb_bank; i++)
702	if (usage_is_set(_usage,USE_STATISTICS))
703	*(_stat_bank_nb_inst [i]) += _rob[i].size();
704	#endif
705
706	#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Commit_unit == true)
707	{
708	log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)");
709	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD);
710	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL);
711
712	for (uint32_t i=0; i<_param->_nb_front_end; i++)
713	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
714	{
715	log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] - %d",i,j,_param->_translate_num_context_to_num_thread [i][j]);
716	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s",toString(reg_EVENT_STATE [i][j]).c_str());
717	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]);
718	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STOP : %d",reg_EVENT_STOP [i][j]);
719	log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_ALL : %d",reg_NB_INST_COMMIT_ALL[i][j]);
720	log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_MEM : %d",reg_NB_INST_COMMIT_MEM[i][j]);
721	log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]);
722	log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2);
723	}
724
725	for (uint32_t i=0; i<_param->_nb_bank; i++)
726	{
727	uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank;
728
729	log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]);
730
731	for (std::list<entry_t*>::iterator it=_rob[num_bank].begin();
732	it!=_rob[num_bank].end();
733	it++)
734	{
735	log_printf(TRACE,Commit_unit,FUNCTION," [%.4d][%.4d] (%.4d) %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s",
736	num_bank ,
737	(*it)->ptr ,
738	((num_bank << _param->_shift_num_bank) \| (*it)->ptr),
739	(*it)->front_end_id ,
740	(*it)->context_id ,
741	(*it)->rename_unit_id ,
742	(*it)->depth ,
743	(*it)->type ,
744	(*it)->operation ,
745	(*it)->is_delay_slot ,
746	(*it)->use_store_queue ,
747	(*it)->store_queue_ptr_write ,
748	(*it)->use_load_queue ,
749	(*it)->load_queue_ptr_write ,
750	toString((*it)->state).c_str() );
751	log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ",
752	(*it)->read_ra ,
753	(*it)->num_reg_ra_log ,
754	(*it)->num_reg_ra_phy ,
755	(*it)->read_rb ,
756	(*it)->num_reg_rb_log ,
757	(*it)->num_reg_rb_phy ,
758	(*it)->read_rc ,
759	(*it)->num_reg_rc_log ,
760	(*it)->num_reg_rc_phy ,
761	(*it)->write_rd ,
762	(*it)->num_reg_rd_log ,
763	(*it)->num_reg_rd_phy_old ,
764	(*it)->num_reg_rd_phy_new ,
765	(*it)->write_re ,
766	(*it)->num_reg_re_log ,
767	(*it)->num_reg_re_phy_old ,
768	(*it)->num_reg_re_phy_new );
769
770	log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)",
771	(*it)->exception_use ,
772	(*it)->exception ,
773	(*it)->flags ,
774	(*it)->no_sequence ,
775	(*it)->speculative ,
776	(*it)->address ,
777	(*it)->address<<2 ,
778	(*it)->address_next ,
779	(*it)->address_next<<2
780	);
781	}
782	}
783	}
784	#endif
785
786	#ifdef DEBUG_TEST
787	{
788	uint32_t x=reg_NUM_BANK_HEAD;
789	if (not _rob[x].empty())
790	{
791	entry_t * entry = _rob [x].front();
792
793	if (false
794	// or (entry->state == ROB_EMPTY )
795	// or (entry->state == ROB_BRANCH_WAIT_END )
796	// or (entry->state == ROB_BRANCH_COMPLETE )
797	// or (entry->state == ROB_STORE_WAIT_HEAD_OK )
798	// //or (entry->state == ROB_STORE_WAIT_HEAD_KO )
799	// or (entry->state == ROB_STORE_HEAD_OK )
800	// or (entry->state == ROB_STORE_HEAD_KO )
801	// or (entry->state == ROB_OTHER_WAIT_END )
802	// or (entry->state == ROB_EVENT_WAIT_END )
803	// or (entry->state == ROB_END_OK_SPECULATIVE )
804	or (entry->state == ROB_END_OK )
805	// or (entry->state == ROB_END_KO_SPECULATIVE )
806	// or (entry->state == ROB_END_KO )
807	// or (entry->state == ROB_END_BRANCH_MISS_SPECULATIVE)
808	or (entry->state == ROB_END_BRANCH_MISS )
809	// or (entry->state == ROB_END_LOAD_MISS_SPECULATIVE )
810	// or (entry->state == ROB_END_LOAD_MISS_UPDATE )
811	or (entry->state == ROB_END_LOAD_MISS )
812	// or (entry->state == ROB_END_MISS )
813	// or (entry->state == ROB_END_EXCEPTION_WAIT_HEAD )
814	// or (entry->state == ROB_END_EXCEPTION_UPDATE )
815	// or (entry->state == ROB_END_EXCEPTION )
816	)
817	if (entry->address != reg_PC_CURRENT[entry->front_end_id][entry->context_id])
818	throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (%x) is different of reg_PC_CURRENT[%d][%d] (%x).\n"),
819	entry->address,
820	entry->front_end_id,
821	entry->context_id,
822	reg_PC_CURRENT[entry->front_end_id][entry->context_id]));
823	}
824	}
825	#endif
826
827	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
828	end_cycle ();
829	#endif
830
831	// Stop Condition
832	for (uint32_t i=0; i<_param->_nb_front_end; i++)
833	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
834	if (_nb_cycle_idle [i][j] >= debug_idle_cycle)
835	throw ERRORMORPHEO(FUNCTION,toString(_("Thread [%d] is idle since %.0f cycles.\n"),_param->_translate_num_context_to_num_thread[i][j],_nb_cycle_idle [i][j]));
836
837	log_end(Commit_unit,FUNCTION);
838	};
839
840	}; // end namespace commit_unit
841	}; // end namespace ooo_engine
842	}; // end namespace multi_ooo_engine
843	}; // end namespace core
844
845	}; // end namespace behavioural
846	}; // end namespace morpheo
847	#endif

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