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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp @ 142

Last change on this file since 142 was 142, checked in by rosiere, 14 years ago
1) Full parallel compilation 2) Add statistics in ROB : list instruction affinity
Property svn:keywords set to `Id`
File size: 80.6 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Commit_unit_transition.cpp 142 2010-08-04 20:09:03Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h"
10	#include "Behavioural/include/Simulation.h"
11
12	namespace morpheo {
13	namespace behavioural {
14	namespace core {
15	namespace multi_ooo_engine {
16	namespace ooo_engine {
17	namespace commit_unit {
18
19	#undef FUNCTION
20	#define FUNCTION "Commit_unit::transition"
21	void Commit_unit::transition (void)
22	{
23	log_begin(Commit_unit,FUNCTION);
24	log_function(Commit_unit,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	// Clear all bank
29	for (uint32_t i=0; i<_param->_nb_bank; ++i)
30	{
31	while(not _rob[i].empty())
32	{
33	delete _rob[i].front();
34	_rob[i].pop_front();
35	}
36	reg_BANK_PTR [i] = 0;
37	}
38
39	// Reset pointer
40	reg_NUM_BANK_HEAD = 0;
41	reg_NUM_BANK_TAIL = 0;
42	reg_NUM_PTR_TAIL = 0;
43
44	// Reset counter
45	for (uint32_t i=0; i<_param->_nb_front_end; i++)
46	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
47	{
48	_nb_cycle_idle [i][j] = 0;
49
50	reg_NB_INST_COMMIT_ALL [i][j] = 0;
51	reg_NB_INST_COMMIT_MEM [i][j] = 0;
52
53	reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT;
54	// reg_EVENT_FLUSH [i][j] = false;
55	// reg_EVENT_STOP [i][j] = false;
56	// reg_EVENT_NUM_BANK [i][j] = 0; // not necessary
57	// reg_EVENT_NUM_PTR [i][j] = 0; // not necessary
58	// reg_EVENT_CAN_RESTART [i][j] = 0; // not necessary
59	reg_EVENT_PACKET [i][j] = 0; // not necessary
60	reg_EVENT_DEPTH [i][j] = 0; // not necessary
61	reg_EVENT_NB_INST [i][j] = 0;
62	reg_EVENT_LAST [i][j] = false;
63	reg_EVENT_LAST_NUM_BANK [i][j] = 0; // not necessary
64	reg_EVENT_LAST_NUM_PTR [i][j] = 0; // not necessary
65
66	reg_EVENT_NEXT_STOP [i][j] = false;
67	reg_EVENT_NEXT_PACKET [i][j] = 0; // not necessary
68
69	// reg_PC_PREVIOUS [i][j] = (0x100-4)>>2;
70	reg_PC_CURRENT [i][j] = (0x100 )>>2;
71	reg_PC_CURRENT_IS_DS [i][j] = 0;
72	reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0;
73	reg_PC_NEXT [i][j] = (0x100+4)>>2;
74	}
75
76	// Resert RAT_UPDATE_TABLE
77	for (uint32_t i=0; i<_param->_nb_front_end; i++)
78	for (uint32_t j=0; j<_param->_nb_context[i]; j++)
79	{
80	for (uint32_t k=0; k<_param->_nb_general_register_logic; k++)
81	rat_gpr_update_table [i][j][k] = false; // not necessary
82	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
83	rat_spr_update_table [i][j][k] = false; // not necessary
84	}
85
86	// Reset priority algorithm
87	_priority_insert->reset();
88	}
89	else
90	{
91	#ifdef STATISTICS
92	uint32_t stat_nb_inst_insert [_param->_nb_rename_unit];
93	uint32_t stat_nb_inst_retire [_param->_nb_rename_unit];
94	uint32_t stat_nb_inst_commit [_param->_nb_rename_unit];
95
96	if (usage_is_set(_usage,USE_STATISTICS))
97	for (uint32_t i=0; i<_param->_nb_rename_unit; ++i)
98	{
99	stat_nb_inst_insert [i] = 0;
100	stat_nb_inst_retire [i] = 0;
101	stat_nb_inst_commit [i] = 0;
102	}
103	#endif
104
105	// Increase number idle cycle
106	for (uint32_t i=0; i<_param->_nb_front_end; i++)
107	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
108	_nb_cycle_idle [i][j] ++;
109
110	// Compute next priority
111	_priority_insert->transition();
112
113	// ===================================================================
114	// =====[ GARBAGE COLLECTOR ]=========================================
115	// ===================================================================
116	for (uint32_t i=0; i<_param->_nb_front_end; i++)
117	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
118	{
119	// Test if can_restart : (can_restart is to signal at the state than the decod_queue is empty)
120	// * no previous can_restart (trap for one)
121	// * and decod_queue is empty
122	// * and have an event or have a futur event
123	// if (not reg_EVENT_CAN_RESTART [i][j] and
124	// (PORT_READ(in_NB_INST_DECOD_ALL [i][j]) == 0) and
125	// (reg_EVENT_STOP [i][j] or (reg_EVENT_STATE [i][j] != COMMIT_EVENT_STATE_NO_EVENT)))
126	// reg_EVENT_CAN_RESTART [i][j] = true;
127
128	// Test event state
129	switch (reg_EVENT_STATE [i][j])
130	{
131	case COMMIT_EVENT_STATE_EVENT :
132	{
133	// Have an event, test if all composant have ack
134	if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j])
135	{
136	// A minor optimisation : test if wait_decod is previously empty.
137	// if (not reg_EVENT_CAN_RESTART [i][j])
138	// reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_DECOD;
139	// else
140	reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END;
141
142	// Reset update_table
143	for (uint32_t k=0; k<_param->_nb_general_register_logic; k++)
144	rat_gpr_update_table [i][j][k] = false;
145	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
146	rat_spr_update_table [i][j][k] = false;
147	}
148
149	break;
150	}
151	// case COMMIT_EVENT_STATE_WAIT_DECOD :
152	// {
153	// // Wait flush of decod_queue.
154	// // Test if can restart now
155	// if (reg_EVENT_CAN_RESTART [i][j])
156	// {
157	// //reg_EVENT_FLUSH [i][j] = false;
158
159	// // A minor optimisation : test if the last element is already retire
160	// if (not reg_EVENT_LAST [i][j])
161	// reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END;
162	// else
163	// reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END;
164	// }
165	// break;
166	// }
167
168	// case COMMIT_EVENT_STATE_WAIT_END :
169	// {
170	// // Wait the flush of Re Order Buffer.
171	// // Test if the last element is retire
172	// if (reg_EVENT_LAST [i][j])
173	// reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END ;
174
175	// break;
176	// }
177	// case COMMIT_EVENT_STATE_END :
178	// {
179	// // Just one cycle
180
181	// // flush of re order buffer is finish
182	// reg_EVENT_LAST [i][j] = false;
183
184	// if (not reg_EVENT_NEXT_STOP [i][j])
185	// reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT;
186	// else
187	// {
188	// reg_EVENT_NEXT_STOP [i][j] = false;
189	// reg_EVENT_PACKET [i][j] = reg_EVENT_NEXT_PACKET [i][j];
190	// reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NOT_YET_EVENT;
191	// // reg_EVENT_STOP [i][j] = true;
192	// reg_EVENT_LAST_NUM_BANK [i][j] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
193	// reg_EVENT_LAST_NUM_PTR [i][j] = reg_NUM_PTR_TAIL;
194	// }
195
196	// break;
197	// }
198
199
200	case COMMIT_EVENT_STATE_WAIT_END :
201	{
202	// Wait the flush of Re Order Buffer.
203	// Test if the last element is retire
204	if (reg_EVENT_LAST [i][j])
205	{
206	// flush of re order buffer is finish
207	reg_EVENT_LAST [i][j] = false;
208
209	if (not reg_EVENT_NEXT_STOP [i][j])
210	reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT;
211	else
212	{
213	uint32_t next_packet = reg_EVENT_NEXT_PACKET [i][j];
214
215	reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NOT_YET_EVENT;
216
217	reg_EVENT_NEXT_STOP [i][j] = false;
218	reg_EVENT_PACKET [i][j] = next_packet;
219	// reg_EVENT_DEPTH [i][j] = _rob[next_packet].depth;
220	reg_EVENT_NB_INST [i][j] = reg_NB_INST_COMMIT_ALL [i][j];
221	//reg_EVENT_STOP [i][j] = true;
222	reg_EVENT_LAST_NUM_BANK [i][j] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
223	reg_EVENT_LAST_NUM_PTR [i][j] = reg_NUM_PTR_TAIL;
224	}
225	}
226	break;
227	}
228
229	//case COMMIT_EVENT_STATE_NO_EVENT :
230	//case COMMIT_EVENT_STATE_NOT_YET_EVENT :
231	default : break;
232	}
233	}
234
235	// ===================================================================
236	// =====[ INSERT ]====================================================
237	// ===================================================================
238	{
239	// for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
240	// for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++)
241	// log_printf(TRACE,Commit_unit,FUNCTION," * INSERT_VAL [%d][%d] : %d",i,j,PORT_READ(in_INSERT_VAL [i][j]));
242
243	// variable to count instruction insert
244	uint32_t nb_insert = 0;
245
246	for (uint32_t i=0; i<_param->_nb_bank; i++)
247	{
248	// compute first bank number
249	uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank;
250
251	if (internal_BANK_INSERT_VAL [num_bank])
252	{
253	// get rename unit source and instruction.
254	uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank];
255	uint32_t y = internal_BANK_INSERT_NUM_INST [num_bank];
256
257	// Test if an instruction is valid
258	// (all in_order insert combinatory is in rename_unit )
259	if (PORT_READ(in_INSERT_VAL [x][y]))
260	{
261	log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y);
262
263	// get information
264	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0;
265	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0;
266	Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]);
267	Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]);
268	bool is_store = is_operation_memory_store(operation);
269
270	Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]);
271	Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]);
272
273	log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id);
274	log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id);
275	log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str());
276	log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation );
277	log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception );
278
279	// Create new entry and write information
280	entry_t * entry = new entry_t;
281	uint32_t ptr = reg_BANK_PTR [num_bank];
282
283	entry->ptr = ptr;
284	entry->front_end_id = front_end_id;
285	entry->context_id = context_id ;
286	entry->rename_unit_id = x;
287	entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0;
288	#ifdef STATISTICS
289	entry->instruction = PORT_READ(in_INSERT_INSTRUCTION [x][y]);
290	#endif
291	entry->type = type;
292	entry->operation = operation;
293	entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]);
294	// entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]);
295	entry->exception = exception;
296	entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]);
297	entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store) and (not no_execute);
298	entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store) and (not no_execute);
299	entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]);
300	entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0;
301	#ifdef DEBUG
302	entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]);
303	entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]);
304	entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]);
305	#endif
306	entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]);
307	#ifdef DEBUG
308	entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]);
309	entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]);
310	entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]);
311	entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]);
312	entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]);
313	#endif
314	entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]);
315	entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]);
316	entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]);
317	entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]);
318	entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]);
319	entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]);
320	entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]);
321	entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]);
322
323	entry->flags = 0; // not necessary
324	entry->no_sequence = type == TYPE_BRANCH;
325	// entry->speculative = true;
326	#ifdef DEBUG
327	entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]);
328	#endif
329	entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]);
330	#ifdef DEBUG
331	entry->cycle_rob_in = simulation_cycle();
332	entry->cycle_commit = simulation_cycle();
333	#endif
334
335	// Test if exception :
336	// * yes : no execute instruction, wait ROB Head
337	// * no : test if no_execute (== instruction is flushed)
338	// else test type
339	// * BRANCH : l.j -> branch is ended
340	// other -> wait the execution end of branchment
341	// * MEMORY : store -> wait store is at head of ROB
342	// other -> wait end of instruction
343	// * OTHER
344
345	{
346	if (exception == EXCEPTION_NONE)
347	{
348	// no_execute : l.j, l.nop, l.rfe
349
350	log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute);
351
352	switch (type)
353	{
354	case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END ; break;}
355	case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store ==1)?ROB_STORE_WAIT_END_OK:ROB_OTHER_WAIT_END); break;}
356	default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
357	}
358	}
359	else
360	{
361	// Have an exception : wait head of ROB
362	// in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap
363
364	entry->state = ROB_END_EXCEPTION_WAIT_HEAD;
365	}
366	}
367
368	#ifdef STATISTICS
369	if (usage_is_set(_usage,USE_STATISTICS))
370	stat_nb_inst_insert [x] ++;
371	#endif
372
373	// Push entry in rob
374	_rob[num_bank].push_back(entry);
375
376	// Update counter and pointer
377	reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++;
378	if (type == TYPE_MEMORY)
379	reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++;
380
381
382	// flush = present event or future event.
383	// * present event = don't can restart
384
385	// bool flush = reg_EVENT_FLUSH [front_end_id][context_id];
386
387	// bool flush = (((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
388	// (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD)) or
389	// (reg_EVENT_STOP [front_end_id][context_id]));
390
391	// New instruction from decod_queue. Flush if :
392	// * future event (instruction don't need execute because they are a previous event (miss load/branch or exception))
393	// * or present_event
394	// * and not can_restart (previous empty decod queue), because between the event_stop (branch_complete) and the state event (miss in head), many cycle is occured.
395	// bool flush = ((// present event
396	// ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
397	// (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD)
398	// ) or
399	// futur event
400	// reg_EVENT_STOP [front_end_id][context_id])
401	// // can't restart
402	// and not reg_EVENT_CAN_RESTART[front_end_id][context_id]
403	// );
404
405	// if (flush)
406	// {
407	// // A new invalid instruction is push in rob -> new last instruction
408	// reg_EVENT_LAST [front_end_id][context_id] = false;
409	// reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = num_bank;
410	// reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = ptr;
411	// }
412
413	// Update pointer
414	reg_NUM_PTR_TAIL = ptr;
415	reg_BANK_PTR [num_bank] = (reg_BANK_PTR [num_bank]+1)%_param->_size_bank;
416	nb_insert ++;
417	}
418	}
419	}
420	// Update pointer
421	reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+nb_insert)%_param->_nb_bank;
422	}
423
424	// ===================================================================
425	// =====[ COMMIT ]====================================================
426	// ===================================================================
427
428	#ifdef STATISTICS
429	if (usage_is_set(_usage,USE_STATISTICS))
430	(*_stat_nb_inst_commit_conflit_access) += internal_BANK_COMMIT_CONFLIT_ACCESS;
431	#endif
432
433	// For each commit instruction ...
434	for (uint32_t i=0; i<_param->_nb_bank; i++)
435	for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++)
436	// ... test if an instruction have finish this execution
437	if (internal_BANK_COMMIT_VAL [i][j])
438	{
439	// An instruction is executed -> Change state of this instruction
440
441	// Get information
442	uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j];
443
444	// Test if instruction is valid and is enable
445	// (can be disable if this instruction is reexecute)
446	if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x]))
447	{
448	log_printf(TRACE,Commit_unit,FUNCTION," * COMMIT [%d]",x);
449	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i);
450
451	// find the good entry !!!
452	entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j];
453
454	#ifdef STATISTICS
455	if (usage_is_set(_usage,USE_STATISTICS))
456	stat_nb_inst_commit [entry->rename_unit_id] ++;
457	#endif
458
459	log_printf(TRACE,Commit_unit,FUNCTION," * ptr : %d",entry->ptr);
460
461	//Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]);
462	Ttype_t type = entry->type;
463	Tcontrol_t no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]);
464	// Tcontrol_t cancel = PORT_READ(in_COMMIT_CANCEL [x]);
465
466	#if 0
467	if ((type == TYPE_MEMORY) and no_sequence)
468	continue;
469	#endif
470
471	Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]);
472
473	rob_state_t state = entry->state;
474	Tcontext_t front_end_id = entry->front_end_id;
475	Tcontext_t context_id = entry->context_id;
476
477	// change state : test exception_use
478
479	bool have_exception = false;
480	bool have_miss_speculation = false;
481
482	// Test if have an exception ...
483	if (exception != EXCEPTION_NONE)
484	{
485	// Test if the instruction is a load and is a miss speculation
486	// (load is commit, but they have an dependence with a previous store -> need restart pipeline)
487
488	have_miss_speculation = (exception == EXCEPTION_MEMORY_MISS_SPECULATION);
489
490	// * Test if the exception generated can be trap by this exception
491	switch (entry->exception_use)
492	{
493	// Have overflow exception if bit overflow enable is set.
494	case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;}
495	case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
496	(exception == EXCEPTION_DATA_TLB ) or
497	(exception == EXCEPTION_DATA_PAGE) or
498	(exception == EXCEPTION_ALIGNMENT)); break;};
499	case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
500	(exception == EXCEPTION_DATA_TLB ) or
501	(exception == EXCEPTION_DATA_PAGE)); break;};
502	case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;};
503	case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;};
504	case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;};
505	case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;};
506	case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;};
507	case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;};
508	case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;};
509	// Case already manage (decod stage -> in insert in ROB)
510	case EXCEPTION_USE_TRAP : {have_exception = false; exception = EXCEPTION_NONE; break;};
511	case EXCEPTION_USE_NONE : {have_exception = false; exception = EXCEPTION_NONE; break;};
512	case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; exception = EXCEPTION_NONE; break;};
513	case EXCEPTION_USE_SYSCALL : {have_exception = false; exception = EXCEPTION_NONE; break;};
514	default :
515	{
516	throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n"));
517	break;
518	}
519	}
520	}
521
522	log_printf(TRACE,Commit_unit,FUNCTION," * have_exception : %d",have_exception );
523	log_printf(TRACE,Commit_unit,FUNCTION," * have_miss_speculation : %d",have_miss_speculation);
524
525
526	// Next state depends of previous state
527	switch (state)
528	{
529	// Branch : if no exception, the branchement can be completed
530	case ROB_BRANCH_WAIT_END :
531	{
532	if (not have_exception)
533	state = ROB_BRANCH_COMPLETE;
534	else
535	state = ROB_END_EXCEPTION_WAIT_HEAD;
536	break;
537	}
538	// Previous event -> set state as execute
539	case ROB_STORE_KO_WAIT_END :
540	case ROB_EVENT_WAIT_END :
541	{
542	state = ROB_END_KO_SPECULATIVE;
543	break;
544	}
545	// No previous event - Load and other instruction
546	case ROB_STORE_OK_WAIT_END :
547	case ROB_OTHER_WAIT_END :
548	{
549	if (not have_exception)
550	{
551	if (not have_miss_speculation)
552	state = ROB_END_OK_SPECULATIVE;
553	else
554	state = ROB_END_LOAD_MISS_SPECULATIVE;
555	}
556	else
557	state = ROB_END_EXCEPTION_WAIT_HEAD;
558	break;
559	}
560	case ROB_STORE_WAIT_END_OK :
561	{
562	if (not have_exception)
563	state = ROB_STORE_OK;
564	else
565	state = ROB_STORE_EVENT;
566	break;
567	}
568	case ROB_STORE_WAIT_END_KO :
569	{
570	// if (not have_exception)
571	state = ROB_STORE_KO;
572	// else
573	// state = ROB_END_EXCEPTION_WAIT_HEAD;
574	break;
575	}
576
577
578	default :
579	{
580	throw ERRORMORPHEO(FUNCTION,toString(_("Commit [%d] : Bank [%d][%d], invalid state value (%s).\n"),x,i,j,toString(state).c_str()));
581	break;
582	}
583	}
584
585	// Commit an instruction ...
586	// Test if have an event (miss_speculation or exception)
587
588	if (have_exception or have_miss_speculation)
589	{
590	// Two case :
591	// if no previous manage event -> generate an event
592	// if previous manage event -> next generate an event
593
594	// bool flush = reg_EVENT_FLUSH [front_end_id][context_id];
595	bool flush = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
596	// (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or
597	(reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END)// or
598	// (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_END)
599	);
600
601	uint32_t packet = ((entry->ptr << _param->_shift_num_slot) \| i);
602	uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) \| reg_NUM_BANK_HEAD);
603
604	log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush);
605	log_printf(TRACE,Commit_unit,FUNCTION," * packet : %d",packet);
606
607	if (not flush)
608	{
609	bool can = true;
610	// test have a previous event detected (event_stop = 1)
611	// if yes, test if the actual event if "before (in order)" that the previous event
612	if (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT)
613	{
614	// Compare packet_id (by construction instruction is insert in order by increase packet_id)
615
616	uint32_t _old = reg_EVENT_PACKET [front_end_id][context_id];
617	uint32_t _new = packet;
618	if (_old < _top) _old = _old+_param->_size_queue;
619	if (_new < _top) _new = _new+_param->_size_queue;
620	if (_new < _old) reg_EVENT_PACKET [front_end_id][context_id] = packet;
621	else can = false;
622	}
623	else
624	reg_EVENT_PACKET [front_end_id][context_id] = packet;
625
626	if (can)
627	{
628	// have an error, stop issue instruction
629	reg_EVENT_STATE [front_end_id][context_id] = COMMIT_EVENT_STATE_NOT_YET_EVENT;
630
631	// reg_EVENT_DEPTH [front_end_id][context_id] = _rob[packet].depth;
632	reg_EVENT_NB_INST [front_end_id][context_id] = reg_NB_INST_COMMIT_ALL [front_end_id][context_id];
633
634	//reg_EVENT_STOP [front_end_id][context_id] = true;
635
636	reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
637	reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = reg_NUM_PTR_TAIL;
638	}
639	}
640	else
641	{
642	bool find = true;
643
644	log_printf(TRACE,Commit_unit,FUNCTION," * reg_EVENT_NEXT_STOP : %d",reg_EVENT_NEXT_STOP [front_end_id][context_id]);
645	log_printf(TRACE,Commit_unit,FUNCTION," * reg_EVENT_NEXT_PACKET : %d",reg_EVENT_NEXT_PACKET[front_end_id][context_id]);
646
647	// already manage an event.
648	if (reg_EVENT_NEXT_STOP [front_end_id][context_id])
649	{
650	// after last ?
651	uint32_t _old = reg_EVENT_NEXT_PACKET [front_end_id][context_id];
652	uint32_t _new = packet;
653
654	log_printf(TRACE,Commit_unit,FUNCTION," * _top : %d",_top );
655	log_printf(TRACE,Commit_unit,FUNCTION," * _old (before) : %d",_old );
656	log_printf(TRACE,Commit_unit,FUNCTION," * _new (before) : %d",_new );
657
658	if (_old < _top) _old = _old+_param->_size_queue;
659	if (_new < _top) _new = _new+_param->_size_queue;
660	if (_new > _old) reg_EVENT_NEXT_PACKET [front_end_id][context_id] = packet;
661	else find = false;
662
663	log_printf(TRACE,Commit_unit,FUNCTION," * _old (after) : %d",_old );
664	log_printf(TRACE,Commit_unit,FUNCTION," * _new (after) : %d",_new );
665	}
666	else
667	{
668	// after last ?
669	uint32_t _old = ((reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] << _param->_shift_num_slot) \| reg_EVENT_LAST_NUM_BANK [front_end_id][context_id]);
670	uint32_t _new = packet;
671
672	log_printf(TRACE,Commit_unit,FUNCTION," * _top : %d",_top );
673	log_printf(TRACE,Commit_unit,FUNCTION," * _old (before) : %d",_old );
674	log_printf(TRACE,Commit_unit,FUNCTION," * _new (before) : %d",_new );
675
676	if (_old < _top) _old = _old+_param->_size_queue;
677	if (_new < _top) _new = _new+_param->_size_queue;
678	if (_new > _old) reg_EVENT_NEXT_PACKET [front_end_id][context_id] = packet;
679	else find = false;
680
681	log_printf(TRACE,Commit_unit,FUNCTION," * _old (after) : %d",_old );
682	log_printf(TRACE,Commit_unit,FUNCTION," * _new (after) : %d",_new );
683	}
684
685	log_printf(TRACE,Commit_unit,FUNCTION," * find : %d",find);
686
687	if (find)
688	reg_EVENT_NEXT_STOP [front_end_id][context_id] = true; // in all case : need stop
689	}
690	}
691
692	// Update Re Order Buffer
693	entry->state = state;
694	entry->exception = exception;
695	entry->flags = PORT_READ(in_COMMIT_FLAGS [x]);
696	entry->no_sequence = no_sequence;
697	// jalr, jr : address_dest is in register
698	if (( type == TYPE_BRANCH) and
699	(entry->operation == OPERATION_BRANCH_L_JALR) and
700	(entry->read_rb))
701	entry->address_next = PORT_READ(in_COMMIT_ADDRESS [x]);
702
703	#ifdef DEBUG
704	entry->load_data = PORT_READ(in_COMMIT_ADDRESS [x]);
705	entry->cycle_commit = simulation_cycle();
706	#endif
707	}
708	}
709
710	// ===================================================================
711	// =====[ RETIRE ]====================================================
712	// ===================================================================
713	for (uint32_t i=0; i<_param->_nb_bank; i++)
714	{
715	// Compute bank number
716	uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank;
717
718	// Test if have an request
719	if (internal_BANK_RETIRE_VAL [num_bank])
720	{
721	// Take num instruction
722	uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank];
723	uint32_t y = internal_BANK_RETIRE_NUM_INST [num_bank];
724
725	log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y);
726	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",num_bank );
727
728	#ifdef DEBUG_TEST
729	if (not PORT_READ(in_RETIRE_ACK [x][y]))
730	throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n"));
731	#endif
732
733	#ifdef STATISTICS
734	if (usage_is_set(_usage,USE_STATISTICS))
735	stat_nb_inst_retire [x] ++;
736	#endif
737
738	// Read information
739	entry_t * entry = _rob [num_bank].front();
740
741	entry->state_old = entry->state;
742	entry->state = ROB_END;
743
744
745	// Update RAT_UPDATE_TABLE
746	Tcontext_t front_end_id = entry->front_end_id;
747	Tcontext_t context_id = entry->context_id ;
748
749	if (entry->write_rd and internal_BANK_RETIRE_RESTORE_RD_PHY_OLD [num_bank])
750	rat_gpr_update_table [front_end_id][context_id][entry->num_reg_rd_log] = true;
751	if (entry->write_re and internal_BANK_RETIRE_RESTORE_RE_PHY_OLD [num_bank])
752	rat_spr_update_table [front_end_id][context_id][entry->num_reg_re_log] = true;
753	}
754	}
755
756	for (uint32_t i=0; i<_param->_nb_bank; i++)
757	{
758	// Compute bank number
759	bool can_continue = false;
760	uint32_t num_bank = reg_NUM_BANK_HEAD;
761
762	if (not _rob [num_bank].empty ())
763	{
764	entry_t * entry = _rob [num_bank].front();
765
766	if (entry->state == ROB_END)
767	{
768	log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE_ROB [%d]",num_bank);
769
770	can_continue = true;
771
772	Tcontext_t front_end_id = entry->front_end_id;
773	Tcontext_t context_id = entry->context_id ;
774	uint32_t num_thread = _param->_translate_num_context_to_num_thread [front_end_id][context_id];
775	rob_state_t state = entry->state_old;
776	Ttype_t type = entry->type ;
777	Toperation_t operation = entry->operation ;
778	bool retire_ok = false;
779	uint32_t packet_id = ((entry->ptr << _param->_shift_num_slot) \| num_bank);
780
781	log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id );
782	log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id );
783	log_printf(TRACE,Commit_unit,FUNCTION," * rob_ptr : %d",packet_id );
784	log_printf(TRACE,Commit_unit,FUNCTION," * num_thread : %d",num_thread );
785	log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str());
786	log_printf(TRACE,Commit_unit,FUNCTION," * state : %s",toString(state).c_str());
787
788	// Test if the instruction is valid
789	// (BRANCH_MISS = instruction branch is valid, but have make an invalid prediction)
790	// (LOAD_MISS = instruction load is valid, but have make an invalid result)
791	if ((state == ROB_END_OK ) or
792	// (state == ROB_END_KO ) or
793	(state == ROB_END_BRANCH_MISS) or
794	(state == ROB_END_LOAD_MISS )// or
795	// (state == ROB_END_MISS ) or
796	// (state == ROB_END_EXCEPTION )
797	)
798	{
799	log_printf(TRACE,Commit_unit,FUNCTION," * retire_ok");
800
801	retire_ok = true;
802
803	// Update PC information
804	// reg_PC_PREVIOUS [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id];
805	reg_PC_CURRENT [front_end_id][context_id] = reg_PC_NEXT [front_end_id][context_id];
806	reg_PC_CURRENT_IS_DS [front_end_id][context_id] = type == TYPE_BRANCH;
807	reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence;
808	reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1);
809	}
810
811	// Test if have an event
812	if ((state == ROB_END_BRANCH_MISS) or
813	(state == ROB_END_LOAD_MISS))
814	{
815	reg_EVENT_STATE [front_end_id][context_id] = COMMIT_EVENT_STATE_EVENT;
816	reg_EVENT_TYPE [front_end_id][context_id] = rob_state_to_event_type(state);
817	// reg_EVENT_STOP [front_end_id][context_id] = false; // instruction flow can continue
818	reg_EVENT_LAST [front_end_id][context_id] = false;
819	// it the head !
820	reg_EVENT_PACKET [front_end_id][context_id] = packet_id;
821	reg_EVENT_DEPTH [front_end_id][context_id] = entry->depth;
822
823	// // If event is an load_miss, many instruction can be inserted.
824	// // -> new last instruction
825	// if (state == ROB_END_LOAD_MISS)
826	// {
827	// // reg_EVENT_CAN_RESTART [front_end_id][context_id] = false;
828
829	// reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
830	// reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = reg_NUM_PTR_TAIL;
831	// }
832	}
833
834	// Test if this instruction is the last instruction of an event
835	// * need event
836	// * packet id = last packet id
837	// for (uint32_t x=0; x<_param->_nb_front_end; x++)
838	// for (uint32_t y=0; y<_param->_nb_context [x]; y++)
839	// if (((reg_EVENT_STATE [x][y] != COMMIT_EVENT_STATE_NO_EVENT ) and
840	// (reg_EVENT_STATE [x][y] != COMMIT_EVENT_STATE_NOT_YET_EVENT)) and
841	// (reg_EVENT_LAST_NUM_BANK [x][y] == num_bank ) and
842	// (reg_EVENT_LAST_NUM_PTR [x][y] == entry->ptr ))
843	// reg_EVENT_LAST [x][y] = true;
844
845
846	if (reg_EVENT_NB_INST [front_end_id][context_id] > 0)
847	{
848	reg_EVENT_NB_INST [front_end_id][context_id] --;
849	if (reg_EVENT_NB_INST [front_end_id][context_id] == 0)
850	reg_EVENT_LAST [front_end_id][context_id] = true;
851	}
852
853	// Update nb_inst
854	reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --;
855	if (type == TYPE_MEMORY)
856	reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --;
857
858	// Update pointer
859	reg_NUM_BANK_HEAD = (num_bank+1)%_param->_nb_bank;
860
861	// Reset watch dog timer because have transaction on retire interface
862	_nb_cycle_idle [front_end_id][context_id] = 0;
863
864	// Increase stop condition
865	if (retire_ok)
866	_simulation_nb_instruction_commited [num_thread] ++;
867
868	#ifdef STATISTICS
869	if (usage_is_set(_usage,USE_STATISTICS))
870	{
871	if (retire_ok)
872	{
873	uint32_t instruction = entry->instruction;
874
875	(*_stat_nb_inst_retire_ok [num_thread] ) ++;
876	(*_stat_nb_inst_instruction [instruction]) ++;
877	(*_stat_nb_inst_type [type] ) ++;
878
879	//uint32_t index = (_stat_last_inst [num_thread] << SIZE_INSTRUCTION) \| instruction;
880	uint32_t index = ((_stat_last_inst_type [num_thread] << (SIZE_TYPE+2*SIZE_OPERATION)) \|
881	(_stat_last_inst_operation [num_thread] << (SIZE_TYPE+ SIZE_OPERATION)) \|
882	( type << ( SIZE_OPERATION)) \|
883	( operation ));
884
885	_stat_inst_fusion [num_thread][index] ++;
886
887	//_stat_last_inst [num_thread] = instruction;
888	_stat_last_inst_type [num_thread] = type ;
889	_stat_last_inst_operation [num_thread] = operation ;
890	}
891	else
892	(*_stat_nb_inst_retire_ko [num_thread]) ++;
893	}
894	#endif
895
896	#if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true)
897	if (log_file_generate)
898	{
899	// log file
900	instruction_log_file [num_thread]
901	<< "[" << simulation_cycle() << "] "
902	<< std::hex
903	<< (entry->address<<2) << " (" << (entry->address) << ") "
904	<< std::dec
905	<< "[" << entry->cycle_rob_in << ", " << entry->cycle_commit << "] "
906	<< "{" << ((retire_ok)?"OK":"KO") << "} ";
907
908	if ((type == TYPE_MEMORY) and is_operation_memory_load(operation))
909	instruction_log_file [num_thread] << std::hex << entry->load_data << std::dec;
910
911	instruction_log_file [num_thread] << std::endl;
912	}
913	#endif
914
915	// Remove entry
916	delete entry;
917	_rob [num_bank].pop_front();
918	}
919	}
920
921	if (not can_continue)
922	break; // stop scan
923	}
924
925	// ===================================================================
926	// =====[ REEXECUTE ]=================================================
927	// ===================================================================
928	// Test if have an reexecute instruction (an store in head of rob)
929	for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i)
930	if (internal_REEXECUTE_VAL [i] and PORT_READ(in_REEXECUTE_ACK [i]))
931	{
932	log_printf(TRACE,Commit_unit,FUNCTION," * REEXECUTE [%d]",i);
933
934	uint32_t num_bank = internal_REEXECUTE_NUM_BANK [i];
935
936	entry_t * entry = _rob [num_bank].front();
937	rob_state_t state = entry->state;
938
939	// Change state
940	switch (state)
941	{
942	case ROB_STORE_OK : {state = ROB_STORE_OK_WAIT_END; break; }
943	case ROB_STORE_KO : {state = ROB_STORE_KO_WAIT_END; break; }
944	case ROB_STORE_EVENT : {state = ROB_EVENT_WAIT_END; break; }
945	default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));}
946	}
947
948	entry->state = state;
949	}
950
951	// ===================================================================
952	// =====[ BRANCH_COMPLETE ]===========================================
953	// ===================================================================
954	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
955	// Test if the prediction_unit have accept the branch complete transaction
956	if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i]))
957	{
958	log_printf(TRACE,Commit_unit,FUNCTION," * BRANCH_COMPLETE [%d]",i);
959
960	// Read information
961	uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i];
962
963	entry_t * entry = _rob [num_bank].front();
964
965	#ifdef DEBUG_TEST
966	rob_state_t state = entry->state;
967	if (state != ROB_BRANCH_COMPLETE)
968	throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n"));
969	#endif
970	Tcontrol_t miss = PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]);
971
972	log_printf(TRACE,Commit_unit,FUNCTION," * miss_prediction : %d",miss);
973
974	entry->state = (miss)?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE;
975
976	// bool flush = reg_EVENT_FLUSH [entry->front_end_id][entry->context_id];
977
978	// Branch_complete can be execute if
979	// * no present event
980	// * futur event and most not speculative that the event
981
982	// Also, test if in this cycle, they have not an most recently event !!!
983	if (miss)
984	{
985	bool can = true;
986	uint32_t packet = ((entry->ptr << _param->_shift_num_slot) \| num_bank);
987
988	// test if this packet is before previous event
989	if (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT)
990	{
991	uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) \| reg_NUM_BANK_HEAD);
992	uint32_t _old = reg_EVENT_PACKET [entry->front_end_id][entry->context_id];
993	uint32_t _new = packet;
994	if (_old < _top) _old = _old+_param->_size_queue;
995	if (_new < _top) _new = _new+_param->_size_queue;
996	if (_new < _old) reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet;
997	else can = false;
998	}
999	else
1000	reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet;
1001
1002	if (can)
1003	{
1004	// In all case, stop instruction flow
1005	reg_EVENT_STATE [entry->front_end_id][entry->context_id] = COMMIT_EVENT_STATE_NOT_YET_EVENT;
1006	// reg_EVENT_DEPTH [entry->front_end_id][entry->context_id] = _rob[packet]._depth;
1007	reg_EVENT_NB_INST [entry->front_end_id][entry->context_id] = reg_NB_INST_COMMIT_ALL [entry->front_end_id][entry->context_id];
1008	// reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true;
1009
1010	// reg_EVENT_CAN_RESTART [entry->front_end_id][entry->context_id] = false;
1011
1012	reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
1013	reg_EVENT_LAST_NUM_PTR [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL;
1014	}
1015	}
1016	}
1017
1018	// ===================================================================
1019	// =====[ UPDATE ]====================================================
1020	// ===================================================================
1021	// Update when exception or load_miss
1022	if (internal_UPDATE_VAL and PORT_READ(in_UPDATE_ACK))
1023	{
1024	log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE");
1025
1026	// Change state
1027	entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front();
1028
1029	switch (entry->state)
1030	{
1031	// case ROB_END_EXCEPTION_UPDATE :
1032	// {
1033	// entry->state = ROB_END_KO;
1034	// throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n"));
1035	// break;
1036	// }
1037	case ROB_END_LOAD_MISS_UPDATE :
1038	{
1039	log_printf(TRACE,Commit_unit,FUNCTION," * ROB_END_LOAD_MISS_UPDATE");
1040
1041	entry->state = ROB_END_LOAD_MISS;
1042	break;
1043	}
1044	default :
1045	{
1046	throw ERRORMORPHEO(FUNCTION,_("Update : invalid state.\n"));
1047	break;
1048	}
1049	}
1050	}
1051
1052	// ===================================================================
1053	// =====[ EVENT ]=====================================================
1054	// ===================================================================
1055	// for (uint32_t i=0; i < _param->_nb_front_end; ++i)
1056	// for (uint32_t j=0; j < _param->_nb_context[i]; ++j)
1057	// if (PORT_READ(in_EVENT_VAL [i][j]) and internal_EVENT_ACK [i][j])
1058	// {
1059	// log_printf(TRACE,Commit_unit,FUNCTION," * EVENT [%d][%d]",i,j);
1060
1061	// reg_PC_CURRENT [i][j] = PORT_READ(in_EVENT_ADDRESS [i][j]);
1062	// reg_PC_CURRENT_IS_DS [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); // ??
1063	// reg_PC_CURRENT_IS_DS_TAKE [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]);
1064	// reg_PC_NEXT [i][j] = PORT_READ(in_EVENT_ADDRESS_NEXT [i][j]);
1065	// // PORT_READ(in_EVENT_ADDRESS_NEXT_VAL [i][j]);
1066	// }
1067
1068	// ===================================================================
1069	// =====[ DEPTH - HEAD ]==============================================
1070	// ===================================================================
1071
1072	{
1073	bool can_continue [_param->_nb_front_end][_param->_max_nb_context];
1074	uint32_t event_nb_inst [_param->_nb_front_end][_param->_max_nb_context];
1075	bool is_speculative [_param->_nb_front_end][_param->_max_nb_context];
1076	for (uint32_t i=0; i<_param->_nb_front_end; i++)
1077	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
1078	{
1079	event_nb_inst [i][j] = 0;
1080	is_speculative[i][j] = false;
1081	can_continue [i][j] = (((reg_EVENT_NB_INST [i][j] == 0) or
1082	( event_nb_inst [i][j] < reg_EVENT_NB_INST [i][j])) and
1083	not reg_EVENT_LAST [i][j]);
1084	}
1085
1086	// Read all instruction of all top bank
1087	for (uint32_t i=0; i<_param->_nb_bank; i++)
1088	{
1089	uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank;
1090
1091	// Test if have an instruction
1092	if (not _rob[num_bank].empty())
1093	{
1094	// Scan all instruction in windows and test if instruction is speculative
1095	entry_t * entry = _rob [num_bank].front();
1096
1097	uint32_t num_packet = ((entry->ptr << _param->_shift_num_slot) \| num_bank);
1098	Tcontext_t front_end_id = entry->front_end_id;
1099	Tcontext_t context_id = entry->context_id ;
1100
1101	log_printf(TRACE,Commit_unit,FUNCTION," * HEAD [%d] - %d",num_bank,num_packet);
1102	log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id);
1103	log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id);
1104	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_LAST : %d",reg_EVENT_LAST [front_end_id][context_id]);
1105	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_NB_INST : %d",reg_EVENT_NB_INST [front_end_id][context_id]);
1106	log_printf(TRACE,Commit_unit,FUNCTION," * event_nb_inst : %d", event_nb_inst [front_end_id][context_id]);
1107
1108	// scan while last event instruction is not retire
1109	if (can_continue [front_end_id][context_id])
1110	{
1111	// Read information
1112	rob_state_t state = entry->state;
1113	// Tdepth_t depth = entry->depth;
1114
1115	// Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0;
1116	// Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0;
1117	// Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]);
1118
1119	// is a valid instruction ?
1120	// If DEPTH_CURRENT :
1121	// equal at DEPTH_MIN -> not speculative
1122	// not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss
1123	// include ]DEPTH_MIN:DEPTH_MAX] -> speculative
1124
1125	// All case
1126	// ....... min ...X... max ....... OK
1127	// ....... min ....... max ...X... KO
1128	// ...X... min ....... max ....... KO
1129	// ....... max ....... min ...X... OK
1130	// ...X... max ....... min ....... OK
1131	// ....... max ...X... min ....... KO
1132
1133	bool flush = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
1134	// (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or
1135	(reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END));
1136	bool speculative = is_speculative [front_end_id][context_id];
1137
1138	// bool speculative = entry->speculative and not (depth == depth_min);
1139	// Tcontrol_t is_valid = ((not speculative or
1140	// (speculative and (depth_full or // all is valid
1141	// ((depth_min <= depth_max)? // test if depth is overflow
1142	// ((depth >= depth_min) and (depth <=depth_max)):
1143	// ((depth >= depth_min) or (depth <=depth_max))))))
1144	// and not flush); // no event
1145
1146	Tcontrol_t is_valid = not flush;
1147
1148
1149	//Tcontrol_t is_valid = ((depth == depth_min) and not flush);
1150
1151
1152	log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d ((depth == depth_min) and not flush)",is_valid);
1153	// log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth );
1154	// log_printf(TRACE,Commit_unit,FUNCTION," * depth_min : %d",depth_min);
1155	// log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max);
1156	// log_printf(TRACE,Commit_unit,FUNCTION," * depth_full : %d",depth_full);
1157	log_printf(TRACE,Commit_unit,FUNCTION," * speculative : %d",speculative);
1158	log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush);
1159	log_printf(TRACE,Commit_unit,FUNCTION," * state (before) : %s",toString(state).c_str());
1160
1161	// //------------------------------------------------------
1162	// // Event ?
1163	// //------------------------------------------------------
1164
1165	// if ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and
1166	// (reg_EVENT_PACKET [front_end_id][context_id] == num_packet))
1167	// {
1168	// switch (state)
1169	// {
1170	// case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;}
1171	// case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;}
1172	// case ROB_END_BRANCH_MISS :
1173	// case ROB_END_LOAD_MISS :
1174	// case ROB_END :
1175	// {break;}
1176	// default :
1177	// {
1178	// throw ERRORMORPHEO(FUNCTION,toString(_("Head [%d] : invalid state (%s)"),num_packet,toString(state).c_str()));
1179	// break;
1180	// }
1181	// }
1182	// }
1183
1184	//------------------------------------------------------
1185	// test if instruction is miss speculative
1186	//------------------------------------------------------
1187	if (not is_valid)
1188	{
1189	// Change state
1190	switch (state)
1191	{
1192	case ROB_BRANCH_WAIT_END : {state = ROB_EVENT_WAIT_END; break;}
1193	case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;}
1194	case ROB_END_BRANCH_MISS :
1195	case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;}
1196	case ROB_END_LOAD_MISS :
1197	case ROB_END_LOAD_MISS_UPDATE :
1198	case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;}
1199	case ROB_STORE_OK : {state = ROB_STORE_KO ; break;}
1200	case ROB_STORE_WAIT_END_OK : {state = ROB_STORE_WAIT_END_KO; break;}
1201	case ROB_STORE_OK_WAIT_END : {state = ROB_STORE_KO_WAIT_END; break;}
1202	case ROB_OTHER_WAIT_END : {state = ROB_EVENT_WAIT_END; break;}
1203	case ROB_END_OK :
1204	case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;}
1205	case ROB_END_KO :
1206	case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;}
1207	case ROB_END_EXCEPTION_UPDATE :
1208	case ROB_END_EXCEPTION :
1209	case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;}
1210
1211	// don't change state -> wait
1212	case ROB_STORE_WAIT_END_KO : {break;}
1213	case ROB_STORE_KO : {break;}
1214	case ROB_STORE_KO_WAIT_END : {break;}
1215	case ROB_STORE_EVENT : {break;}
1216	case ROB_EVENT_WAIT_END : {break;}
1217	case ROB_END_MISS : {break;}
1218	case ROB_END : {break;}
1219
1220	// can't have miss speculation -> invalid state
1221	default :
1222	{
1223	throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str()));
1224	break;
1225	}
1226	}
1227	}
1228
1229	//------------------------------------------------------
1230	// test if instruction is branch not finish
1231	//------------------------------------------------------
1232	switch (state)
1233	{
1234	case ROB_BRANCH_WAIT_END :
1235	case ROB_BRANCH_COMPLETE :
1236	{
1237	is_speculative [front_end_id][context_id] = true;
1238	break;
1239	}
1240	default : break;
1241	}
1242
1243	//------------------------------------------------------
1244	// test if instruction is not speculative
1245	//------------------------------------------------------
1246	// entry->speculative = speculative;
1247	// if (entry->depth == depth_min)
1248	// test if instruction is speculative (depth != depth_min)
1249	if (not speculative)
1250	{
1251	switch (state)
1252	{
1253	case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;}
1254	case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;}
1255	case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;}
1256	case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;}
1257	default : {break;} // else, no change
1258	}
1259	}
1260
1261	//------------------------------------------------------
1262	// test if instruction wait head and is the top of rob
1263	//------------------------------------------------------
1264	// TODO : retire OOO
1265	if (i == 0)
1266	{
1267	switch (state)
1268	{
1269	// case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;}
1270	case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;}
1271	default : {break;} // else, no change
1272	}
1273	}
1274
1275	// Write new state
1276	entry->state = state;
1277
1278	log_printf(TRACE,Commit_unit,FUNCTION," * state (after ) : %s",toString(state).c_str());
1279
1280	// log_printf(TRACE,Commit_unit,FUNCTION," * Stop Scan !!!");
1281
1282	event_nb_inst [front_end_id][context_id] ++;
1283
1284	// stop if :
1285	// * begin event
1286	// * end event
1287	if (((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and
1288	(reg_EVENT_PACKET[front_end_id][context_id] == num_packet)) or
1289	((reg_EVENT_NB_INST [front_end_id][context_id] > 0) and
1290	( event_nb_inst [front_end_id][context_id] >= reg_EVENT_NB_INST [front_end_id][context_id])))
1291	can_continue [front_end_id][context_id] = false;
1292	}
1293	}
1294	}
1295	}
1296
1297
1298
1299	#ifdef STATISTICS
1300	if (usage_is_set(_usage,USE_STATISTICS))
1301	{
1302	for (uint32_t i=0; i<_param->_nb_bank; i++)
1303	*(_stat_bank_nb_inst [i]) += _rob[i].size();
1304
1305	for (uint32_t i=0; i<_param->_nb_front_end; i++)
1306	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
1307	{
1308	uint32_t num_thread = _param->_translate_num_context_to_num_thread [i][j];
1309
1310	switch (reg_EVENT_STATE [i][j])
1311	{
1312	case COMMIT_EVENT_STATE_NO_EVENT : (*_stat_nb_cycle_state_no_event [num_thread])++; break;
1313	case COMMIT_EVENT_STATE_NOT_YET_EVENT : (*_stat_nb_cycle_state_not_yet_event [num_thread])++; break;
1314	case COMMIT_EVENT_STATE_EVENT : (*_stat_nb_cycle_state_event [num_thread])++; break;
1315	case COMMIT_EVENT_STATE_WAIT_END : (*_stat_nb_cycle_state_wait_end [num_thread])++; break;
1316	}
1317	}
1318
1319	for (uint32_t i=0; i<_param->_nb_rename_unit; ++i)
1320	{
1321	(*_stat_nb_inst_insert [i]) += stat_nb_inst_insert [i];
1322	(*_stat_nb_inst_retire [i]) += stat_nb_inst_retire [i];
1323	(*_stat_nb_inst_commit [i]) += stat_nb_inst_commit [i];
1324	}
1325	}
1326	#endif
1327	}
1328
1329	// ===================================================================
1330	// =====[ OTHER ]=====================================================
1331	// ===================================================================
1332
1333	#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Commit_unit == true)
1334	{
1335	log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)");
1336	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD);
1337	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL);
1338	log_printf(TRACE,Commit_unit,FUNCTION," * num_ptr_tail : %d",reg_NUM_PTR_TAIL );
1339
1340	for (uint32_t i=0; i<_param->_nb_front_end; i++)
1341	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
1342	{
1343	log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] - %d",i,j,_param->_translate_num_context_to_num_thread [i][j]);
1344	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s - %s",toString(reg_EVENT_STATE [i][j]).c_str(),toString(commit_event_state_to_event_state(reg_EVENT_STATE [i][j])).c_str());
1345	// log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]);
1346	// log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STOP : %d",reg_EVENT_STOP [i][j]);
1347	// log_printf(TRACE,Commit_unit,FUNCTION," * EVENT : %d (bank %d, ptr %d)",((reg_EVENT_NUM_PTR [i][j] << _param->_shift_num_slot) \| reg_EVENT_NUM_BANK [i][j]), reg_EVENT_NUM_BANK [i][j],reg_EVENT_NUM_PTR [i][j]);
1348	// log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_CAN_RESTART : %d",reg_EVENT_CAN_RESTART [i][j]);
1349	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_DEPTH : %d - type %s",reg_EVENT_DEPTH [i][j],toString(reg_EVENT_TYPE [i][j]).c_str());
1350	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_LAST : %d - packet %d - ptr %d (bank %d, ptr %d)",reg_EVENT_LAST [i][j],reg_EVENT_PACKET[i][j],((reg_EVENT_LAST_NUM_PTR [i][j] << _param->_shift_num_slot) \| reg_EVENT_LAST_NUM_BANK [i][j]), reg_EVENT_LAST_NUM_BANK [i][j],reg_EVENT_LAST_NUM_PTR [i][j]);
1351	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_NEXT : stop : %d - packet : %d",reg_EVENT_NEXT_STOP [i][j],reg_EVENT_NEXT_PACKET[i][j]);
1352	log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_ALL : all : %d - mem : %d - event : %d",reg_NB_INST_COMMIT_ALL[i][j], reg_NB_INST_COMMIT_MEM[i][j],reg_EVENT_NB_INST[i][j]);
1353	log_printf(TRACE,Commit_unit,FUNCTION," * PC : %.8x (%.8x) - %d %d - %.8x (%.8x)",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j],reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2);
1354	}
1355
1356	std::list<entry_t*>::iterator iter [_param->_nb_bank];
1357	for (uint32_t i=0; i<_param->_nb_bank; i++)
1358	{
1359	uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank;
1360	// log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]);
1361
1362	iter [num_bank] = _rob[num_bank].begin();
1363	}
1364
1365	bool all_empty = false;
1366	uint32_t nb_write_rd = 0;
1367	uint32_t nb_write_re = 0;
1368
1369	while (not all_empty)
1370	{
1371	all_empty = true;
1372
1373	for (uint32_t i=0; i<_param->_nb_bank; i++)
1374	{
1375	uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank;
1376
1377	std::list<entry_t*>::iterator it = iter[num_bank];
1378	if (it != _rob[num_bank].end())
1379	{
1380	all_empty = false;
1381
1382	nb_write_rd += ((*it)->write_rd)?1:0;
1383	nb_write_re += ((*it)->write_re)?1:0;
1384
1385	log_printf(TRACE,Commit_unit,FUNCTION," [%.4d][%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s",
1386	num_bank ,
1387	(*it)->ptr ,
1388	(*it)->front_end_id ,
1389	(*it)->context_id ,
1390	(*it)->rename_unit_id ,
1391	(*it)->depth ,
1392	(*it)->type ,
1393	(*it)->operation ,
1394	(*it)->is_delay_slot ,
1395	(*it)->use_store_queue ,
1396	(*it)->store_queue_ptr_write ,
1397	(*it)->use_load_queue ,
1398	(*it)->load_queue_ptr_write ,
1399	toString((*it)->state).c_str() );
1400	log_printf(TRACE,Commit_unit,FUNCTION," (%.4d) %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ",
1401	(((*it)->ptr << _param->_shift_num_slot) \| num_bank),
1402	(*it)->read_ra ,
1403	(*it)->num_reg_ra_log ,
1404	(*it)->num_reg_ra_phy ,
1405	(*it)->read_rb ,
1406	(*it)->num_reg_rb_log ,
1407	(*it)->num_reg_rb_phy ,
1408	(*it)->read_rc ,
1409	(*it)->num_reg_rc_log ,
1410	(*it)->num_reg_rc_phy ,
1411	(*it)->write_rd ,
1412	(*it)->num_reg_rd_log ,
1413	(*it)->num_reg_rd_phy_old ,
1414	(*it)->num_reg_rd_phy_new ,
1415	(*it)->write_re ,
1416	(*it)->num_reg_re_log ,
1417	(*it)->num_reg_re_phy_old ,
1418	(*it)->num_reg_re_phy_new );
1419
1420	log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)",
1421	(*it)->exception_use ,
1422	(*it)->exception ,
1423	(*it)->flags ,
1424	(*it)->no_sequence ,
1425	// (*it)->speculative ,
1426	(*it)->address ,
1427	(*it)->address<<2 ,
1428	(*it)->address_next ,
1429	(*it)->address_next<<2
1430	);
1431
1432	iter [num_bank] ++;
1433	}
1434	}
1435	}
1436
1437	log_printf(TRACE,Commit_unit,FUNCTION," * Dump RAT Update Table");
1438	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
1439	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
1440	{
1441	{
1442	std::string str = "";
1443	for (uint32_t k=0; k<_param->_nb_general_register_logic; k++)
1444	str+=toString("%.1d ",rat_gpr_update_table[i][j][k]);
1445
1446	log_printf(TRACE,Commit_unit,FUNCTION," * GPR [%d][%d] %s",i,j,str.c_str());
1447	}
1448
1449	{
1450	std::string str = "";
1451	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
1452	str+=toString("%.1d ",rat_spr_update_table[i][j][k]);
1453
1454	log_printf(TRACE,Commit_unit,FUNCTION," * GPR [%d][%d] %s",i,j,str.c_str());
1455	}
1456	}
1457
1458	log_printf(TRACE,Commit_unit,FUNCTION," * nb_write_rd : %d",nb_write_rd);
1459	log_printf(TRACE,Commit_unit,FUNCTION," * nb_write_re : %d",nb_write_re);
1460	}
1461	#endif
1462
1463	#ifdef DEBUG_TEST
1464	{
1465	uint32_t x=reg_NUM_BANK_HEAD;
1466	if (not _rob[x].empty())
1467	{
1468	entry_t * entry = _rob [x].front();
1469
1470	if (false
1471	// or (entry->state == ROB_EMPTY )
1472	// or (entry->state == ROB_BRANCH_WAIT_END )
1473	// or (entry->state == ROB_BRANCH_COMPLETE )
1474	// or (entry->state == ROB_STORE_WAIT_HEAD_OK )
1475	// //or (entry->state == ROB_STORE_WAIT_HEAD_KO )
1476	// or (entry->state == ROB_STORE_HEAD_OK )
1477	// or (entry->state == ROB_STORE_HEAD_KO )
1478	// or (entry->state == ROB_OTHER_WAIT_END )
1479	// or (entry->state == ROB_EVENT_WAIT_END )
1480	// or (entry->state == ROB_END_OK_SPECULATIVE )
1481	or (entry->state == ROB_END_OK )
1482	// or (entry->state == ROB_END_KO_SPECULATIVE )
1483	// or (entry->state == ROB_END_KO )
1484	// or (entry->state == ROB_END_BRANCH_MISS_SPECULATIVE)
1485	or (entry->state == ROB_END_BRANCH_MISS )
1486	// or (entry->state == ROB_END_LOAD_MISS_SPECULATIVE )
1487	// or (entry->state == ROB_END_LOAD_MISS_UPDATE )
1488	or (entry->state == ROB_END_LOAD_MISS )
1489	// or (entry->state == ROB_END_MISS )
1490	// or (entry->state == ROB_END_EXCEPTION_WAIT_HEAD )
1491	// or (entry->state == ROB_END_EXCEPTION_UPDATE )
1492	// or (entry->state == ROB_END_EXCEPTION )
1493	)
1494	if (entry->address != reg_PC_CURRENT[entry->front_end_id][entry->context_id])
1495	throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (0x%x) is different of reg_PC_CURRENT[%d][%d] (0x%x).\n"),
1496	entry->address,
1497	entry->front_end_id,
1498	entry->context_id,
1499	reg_PC_CURRENT[entry->front_end_id][entry->context_id]));
1500	}
1501	}
1502	{
1503	uint32_t NB_INST [_param->_nb_front_end][_param->_max_nb_context];
1504	for (uint32_t i=0; i<_param->_nb_front_end; i++)
1505	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
1506	NB_INST [i][j] = 0; //reg_EVENT_NB_INST [i][j];
1507
1508	for (uint32_t i=0; i<_param->_nb_bank; ++i)
1509	for (std::list<entry_t*>::iterator it=_rob[i].begin();
1510	it!=_rob [i].end();
1511	++it)
1512	NB_INST [(it)->front_end_id][(it)->context_id] ++;
1513
1514	for (uint32_t i=0; i<_param->_nb_front_end; i++)
1515	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
1516	if (NB_INST [i][j] != reg_NB_INST_COMMIT_ALL [i][j])
1517	throw ERRORMORPHEO(FUNCTION,toString(_("Context [%d][%d] have not the good nb_inst (%d in rob, %d in register).\n"),i,j,NB_INST[i][j], reg_NB_INST_COMMIT_ALL [i][j]));
1518	}
1519	#endif
1520
1521	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
1522	end_cycle ();
1523	#endif
1524
1525	// Stop Condition
1526	for (uint32_t i=0; i<_param->_nb_front_end; i++)
1527	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
1528	if (_nb_cycle_idle [i][j] >= debug_idle_cycle)
1529	throw ERRORMORPHEO(FUNCTION,toString(_("Thread [%d] is idle since %.0f cycles.\n"),_param->_translate_num_context_to_num_thread[i][j],_nb_cycle_idle [i][j]));
1530
1531	log_end(Commit_unit,FUNCTION);
1532	};
1533
1534	}; // end namespace commit_unit
1535	}; // end namespace ooo_engine
1536	}; // end namespace multi_ooo_engine
1537	}; // end namespace core
1538
1539	}; // end namespace behavioural
1540	}; // end namespace morpheo
1541	#endif

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