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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp @ 97

Last change on this file since 97 was 97, checked in by rosiere, 15 years ago
1) Update Prediction Table : statistics 2) Size instruction address on 30 bits 3) Change Log File 4) Add debug_level in simulation configuration file
Property svn:keywords set to `Id`
File size: 22.6 KB

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1	#ifdef SYSTEMC
2	/*
3	* $Id: Commit_unit_transition.cpp 97 2008-12-19 15:34:00Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_ooo_engine {
15	namespace ooo_engine {
16	namespace commit_unit {
17
18
19	#undef FUNCTION
20	#define FUNCTION "Commit_unit::transition"
21	void Commit_unit::transition (void)
22	{
23	log_begin(Commit_unit,FUNCTION);
24	log_function(Commit_unit,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	for (uint32_t i=0; i<_param->_nb_bank; i++)
29	{
30	_rob [i].clear();
31	reg_BANK_PTR [i] = 0;
32	}
33
34	reg_NUM_BANK_HEAD = 0;
35	reg_NUM_BANK_TAIL = 0;
36
37	for (uint32_t i=0; i<_param->_nb_front_end; i++)
38	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
39	{
40	reg_NB_INST_COMMIT_ALL [i][j] = 0;
41	reg_NB_INST_COMMIT_MEM [i][j] = 0;
42	}
43
44	_priority_insert->reset();
45	}
46	else
47	{
48	// next priority
49	_priority_insert->transition();
50
51	// ===================================================================
52	// =====[ INSERT ]====================================================
53	// ===================================================================
54	for (uint32_t i=0; i<_param->_nb_bank; i++)
55	if (internal_BANK_INSERT_VAL [i])
56	{
57	uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i];
58	uint32_t y = internal_BANK_INSERT_NUM_INST [i];
59
60	if (PORT_READ(in_INSERT_VAL [x][y]))
61	{
62	log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y);
63
64	#ifdef STATISTICS
65	if (usage_is_set(_usage,USE_STATISTICS))
66	(*_stat_nb_inst_insert [x]) ++;
67	#endif
68
69	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0;
70	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0;
71	Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]);
72	Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]);
73	Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]);
74
75	log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id);
76	log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id);
77	log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str());
78	log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation );
79	log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception );
80
81	entry_t * entry = new entry_t;
82
83	entry->ptr = reg_BANK_PTR [i];
84	entry->front_end_id = front_end_id;
85	entry->context_id = context_id ;
86	entry->rename_unit_id = x;
87	entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0;
88	entry->type = type;
89	entry->operation = operation;
90	entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]);
91	entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]);
92	entry->exception = exception;
93	entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]);
94	entry->use_store_queue = (type == TYPE_MEMORY) and ( is_operation_memory_store(operation));
95	entry->use_load_queue = (type == TYPE_MEMORY) and (not is_operation_memory_store(operation));
96	entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]);
97	entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0;
98	entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]);
99	entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]);
100	entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]);
101	entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]);
102	entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]);
103	entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]);
104	entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]);
105	entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]);
106	entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]);
107	entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]);
108	entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]);
109	entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]);
110	entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]);
111	entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]);
112	entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]);
113	entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]);
114	entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]);
115
116	if (exception == EXCEPTION_NONE)
117	{
118	Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]);
119	// no_execute : l.j, l.nop, l.rfe
120
121	log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute);
122
123	switch (type)
124	{
125	case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END; break;}
126	case TYPE_MEMORY : {entry->state=ROB_STORE_WAIT_HEAD_OK; break;}
127	default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
128	}
129	}
130	else
131	{
132	// in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap
133
134	entry->state = ROB_END_EXCEPTION_WAIT_HEAD;
135	}
136
137	_rob[i].push_back(entry);
138
139	// Update nb_inst
140	reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++;
141	if (type == TYPE_MEMORY)
142	reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++;
143
144	reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+1)%_param->_nb_bank;
145	reg_BANK_PTR [i] = (reg_BANK_PTR [i]+1)%_param->_size_bank;
146	}
147	}
148
149	// ===================================================================
150	// =====[ COMMIT ]====================================================
151	// ===================================================================
152
153	#ifdef STATISTICS
154	if (usage_is_set(_usage,USE_STATISTICS))
155	(*_stat_nb_inst_commit_conflit_access) += internal_BANK_COMMIT_CONFLIT_ACCESS;
156	#endif
157
158	for (uint32_t i=0; i<_param->_nb_bank; i++)
159	for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++)
160	if (internal_BANK_COMMIT_VAL [i][j])
161	{
162	uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j];
163
164	if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x]))
165	{
166	log_printf(TRACE,Commit_unit,FUNCTION," * COMMIT [%d]",x);
167
168	#ifdef STATISTICS
169	if (usage_is_set(_usage,USE_STATISTICS))
170	(*_stat_nb_inst_commit) ++;
171	#endif
172
173	// Tpacket_t packet_id = (_param->_have_port_rob_ptr )?(PORT_READ(in_COMMIT_PACKET_ID [x])&_param->_mask_size_bank):0;
174
175	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i);
176	// log_printf(TRACE,Commit_unit,FUNCTION," * packet_id : %d",(_param->_have_port_rob_ptr )?(PORT_READ(in_COMMIT_PACKET_ID [x])):0);
177	// log_printf(TRACE,Commit_unit,FUNCTION," * num_entry : %d",packet_id);
178
179	// test pandex with ptr_write.
180	// Tpacket_t index = (packet_id<reg_BANK_PTR [i])?(reg_BANK_PTR [i]-packet_id):(_param->_size_bank+reg_BANK_PTR [i]-packet_id);
181
182	// find the good entry !!!
183	entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j];
184
185	//Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]);
186	//Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]);
187	Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]);
188
189	rob_state_t state = entry->state;
190	Tcontext_t front_end_id = entry->front_end_id;
191	Tcontext_t context_id = entry->context_id;
192
193	// change state
194	// * test if exception : exception and mask
195
196	bool have_exception = false;
197
198	if (exception != EXCEPTION_NONE)
199	switch (entry->exception_use)
200	{
201	case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;}
202	case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
203	(exception == EXCEPTION_DATA_TLB ) or
204	(exception == EXCEPTION_DATA_PAGE) or
205	(exception == EXCEPTION_ALIGNMENT)); break;};
206	case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
207	(exception == EXCEPTION_DATA_TLB ) or
208	(exception == EXCEPTION_DATA_PAGE)); break;};
209	case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;};
210	case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;};
211	case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;};
212	case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;};
213	case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;};
214	case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;};
215	case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;};
216	case EXCEPTION_USE_TRAP : {have_exception = false; break;};
217	case EXCEPTION_USE_NONE : {have_exception = false; break;};
218	case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; break;};
219	case EXCEPTION_USE_SYSCALL : {have_exception = false; break;};
220	default :
221	{
222	throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n"));
223	break;
224	}
225	}
226
227	if (not have_exception)
228	{
229	switch (state)
230	{
231	case ROB_OTHER_WAIT_END : {state = ROB_END_OK_SPECULATIVE; break;}
232	case ROB_BRANCH_WAIT_END : {state = ROB_BRANCH_COMPLETE ; break;}
233	case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;}
234	default :
235	{
236	throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str()));
237	break;
238	}
239	}
240	// can have an exception, but this instruction is not sensible a this exception
241	exception = EXCEPTION_NONE;
242	}
243	else
244	{
245	#ifdef DEBUG_TEST
246	if ((entry->type == TYPE_MEMORY) and (exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
247	throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception.\n"));
248	#endif
249
250	switch (state)
251	{
252	case ROB_OTHER_WAIT_END :
253	case ROB_BRANCH_WAIT_END : {state = ROB_END_EXCEPTION_WAIT_HEAD; break;}
254	case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE ; break;}
255	default :
256	{
257	throw ERRORMORPHEO(FUNCTION,_("Commit : invalid state value.\n"));
258	break;
259	}
260	}
261	}
262
263	// update Re Order Buffer
264	entry->state = state;
265	entry->exception = exception;
266	entry->flags = PORT_READ(in_COMMIT_FLAGS [x]);
267	entry->no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]);
268	entry->data_commit = PORT_READ(in_COMMIT_ADDRESS [x]);
269	}
270	}
271
272	// ===================================================================
273	// =====[ RETIRE ]====================================================
274	// ===================================================================
275	for (uint32_t i=0; i<_param->_nb_bank; i++)
276	if (internal_BANK_RETIRE_VAL [i])
277	{
278	uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [i];
279	uint32_t y = internal_BANK_RETIRE_NUM_INST [i];
280
281	log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y);
282
283	#ifdef STATISTICS
284	if (usage_is_set(_usage,USE_STATISTICS))
285	(*_stat_nb_inst_retire [x]) ++;
286	#endif
287
288	#ifdef DEBUG_TEST
289	if (not PORT_READ(in_RETIRE_ACK [x][y]))
290	throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n"));
291	#endif
292
293
294	entry_t * entry = _rob [i].front();
295
296	Tcontext_t front_end_id = entry->front_end_id;
297	Tcontext_t context_id = entry->context_id ;
298	Ttype_t type = entry->type ;
299
300	// Update nb_inst
301	reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --;
302	if (type == TYPE_MEMORY)
303	reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --;
304
305	reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank;
306
307	_rob [i].pop_front();
308	delete entry;
309	}
310
311	// ===================================================================
312	// =====[ REEXECUTE ]=================================================
313	// ===================================================================
314	if (internal_REEXECUTE_VAL [0] and PORT_READ(in_REEXECUTE_ACK [0]))
315	{
316	uint32_t num_bank = internal_REEXECUTE_NUM_BANK [0];
317
318	entry_t * entry = _rob [num_bank].front();
319	rob_state_t state = entry->state;
320
321	switch (state)
322	{
323	case ROB_STORE_HEAD_OK : {state = ROB_OTHER_WAIT_END; break; }
324	case ROB_STORE_HEAD_KO : {state = ROB_MISS_WAIT_END ; break; }
325	default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));}
326	}
327
328	entry->state = state;
329	}
330
331	// ===================================================================
332	// =====[ BRANCH_COMPLETE ]===========================================
333	// ===================================================================
334	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
335	if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i]))
336	{
337	uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i];
338
339	entry_t * entry = _rob [num_bank].front();
340
341	#ifdef DEBUG_TEST
342	rob_state_t state = entry->state;
343	if (state != ROB_BRANCH_COMPLETE)
344	throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n"));
345	#endif
346
347	entry->state = ROB_END_OK_SPECULATIVE;
348	}
349
350	// ===================================================================
351	// =====[ EVENT ]=====================================================
352	// ===================================================================
353
354	// ===================================================================
355	// =====[ DEPTH - HEAD ]==============================================
356	// ===================================================================
357	for (uint32_t i=0; i<_param->_nb_bank; i++)
358	if (not _rob[i].empty())
359	{
360	// Scan all instruction in windows and test if instruction is speculative
361	entry_t * entry = _rob [i].front();
362
363	Tcontext_t front_end_id = entry->front_end_id;
364	Tcontext_t context_id = entry->context_id ;
365	rob_state_t state = entry->state;
366	Tdepth_t depth = entry->depth;
367
368	Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [front_end_id][context_id]):0;
369	Tdepth_t depth_max = PORT_READ(in_DEPTH_MAX[front_end_id][context_id]);
370
371	// is a valid instruction ?
372	// If DEPTH_CURRENT :
373	// equal at DEPTH_MIN -> not speculative
374	// not include ]DEPTH_MIN:DEPTH_MAX[ -> previous branch miss
375	// include ]DEPTH_MIN:DEPTH_MAX[ -> speculative
376
377	// All case
378	// ....... min ...X... max ....... OK
379	// ....... min ....... max ...X... KO
380	// ...X... min ....... max ....... KO
381	// ....... max ....... min ...X... OK
382	// ...X... max ....... min ....... OK
383	// ....... max ...X... min ....... KO
384
385	Tcontrol_t is_valid = ((depth == depth_min) or
386	((depth_min < depth_max)?
387	(depth<depth_max):
388	((depth > depth_min) or (depth < depth_max))));
389
390	//------------------------------------------------------
391	// test if instruction is miss speculative
392	//------------------------------------------------------
393	if (not is_valid)
394	{
395	switch (state)
396	{
397	case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;}
398	case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;}
399	case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;}
400	//case ROB_STORE_WAIT_HEAD_KO : {state = ; break;}
401	case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;}
402	case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;}
403	case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;}
404	case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;}
405
406	// don't change
407	case ROB_STORE_HEAD_KO : {break;}
408	case ROB_MISS_WAIT_END : {break;}
409	case ROB_END_MISS : {break;}
410
411	// can't have miss speculation
412	case ROB_STORE_HEAD_OK :
413	case ROB_END_OK :
414	case ROB_END_KO :
415	case ROB_END_EXCEPTION :
416	default :
417	{
418	throw ERRORMORPHEO(FUNCTION,_("Miss Speculation : Invalide state.\n"));
419	break;
420	}
421	}
422	}
423
424	//------------------------------------------------------
425	// test if instruction is not speculative
426	//------------------------------------------------------
427	if (entry->depth == depth_min)
428	{
429	switch (state)
430	{
431	case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;}
432	case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;}
433	default : {break;}
434	}
435	}
436
437	//------------------------------------------------------
438	// test if instruction is store and head
439	//------------------------------------------------------
440	if (i == reg_NUM_BANK_HEAD)
441	{
442	switch (state)
443	{
444	case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;}
445	case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION; break;}
446	default : {break;}
447	}
448	}
449
450	entry->state = state;
451	}
452	}
453
454	// ===================================================================
455	// =====[ OTHER ]=====================================================
456	// ===================================================================
457
458	log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)");
459	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD);
460	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL);
461
462	for (uint32_t i=0; i<_param->_nb_front_end; i++)
463	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
464	log_printf(TRACE,Commit_unit,FUNCTION," * num_inst[%d][%d] all : %d, mem : %d",i,j,reg_NB_INST_COMMIT_ALL[i][j],reg_NB_INST_COMMIT_MEM[i][j]);
465
466	for (uint32_t i=0; i<_param->_nb_bank; i++)
467	{
468	log_printf(TRACE,Commit_unit,FUNCTION," * Bank[%d] size : %d, ptr : %d",i,(int)_rob[i].size(), reg_BANK_PTR [i]);
469
470	#ifdef STATISTICS
471	if (usage_is_set(_usage,USE_STATISTICS))
472	*(_stat_bank_nb_inst [i]) += _rob[i].size();
473	#endif
474
475	uint32_t x=0;
476	for (std::list<entry_t*>::iterator it=_rob[i].begin();
477	it!=_rob[i].end();
478	it++)
479	{
480	log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.8x %.1d, %.1d %.4d, %.1d %.4d, %s - %d",
481	x,
482	(*it)->front_end_id ,
483	(*it)->context_id ,
484	(*it)->rename_unit_id ,
485	(*it)->depth ,
486	(*it)->type ,
487	(*it)->operation ,
488	(*it)->address ,
489	(*it)->is_delay_slot ,
490	(*it)->use_store_queue ,
491	(*it)->store_queue_ptr_write ,
492	(*it)->use_load_queue ,
493	(*it)->load_queue_ptr_write ,
494	toString((*it)->state).c_str() ,
495	(*it)->ptr );
496	log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.5d %.6d, %.1d %.5d %.6d, %.1d %.5d %.6d, %.1d %.1d %.6d %.6d, %.1d %.1d %.6d %.6d ",
497	(*it)->read_ra ,
498	(*it)->num_reg_ra_log ,
499	(*it)->num_reg_ra_phy ,
500	(*it)->read_rb ,
501	(*it)->num_reg_rb_log ,
502	(*it)->num_reg_rb_phy ,
503	(*it)->read_rc ,
504	(*it)->num_reg_rc_log ,
505	(*it)->num_reg_rc_phy ,
506	(*it)->write_rd ,
507	(*it)->num_reg_rd_log ,
508	(*it)->num_reg_rd_phy_old ,
509	(*it)->num_reg_rd_phy_new ,
510	(*it)->write_re ,
511	(*it)->num_reg_re_log ,
512	(*it)->num_reg_re_phy_old ,
513	(*it)->num_reg_re_phy_new );
514
515	log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x %s",
516	(*it)->exception ,
517	(*it)->exception_use ,
518	(*it)->flags ,
519	(*it)->no_sequence ,
520	(*it)->data_commit ,
521	toString((*it)->event_state).c_str()
522	);
523
524	x++;
525	}
526	}
527
528	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
529	end_cycle ();
530	#endif
531
532	log_end(Commit_unit,FUNCTION);
533	};
534
535	}; // end namespace commit_unit
536	}; // end namespace ooo_engine
537	}; // end namespace multi_ooo_engine
538	}; // end namespace core
539
540	}; // end namespace behavioural
541	}; // end namespace morpheo
542	#endif

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