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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp @ 106

Last change on this file since 106 was 106, checked in by rosiere, 15 years ago
1) RAT : Fix bug when update and event in same cycle 2) Context State : Compute depth 3) Load Store Unit : In check logic, translate all access in little endian. More easy to check 4) UFPT : End Event
Property svn:keywords set to `Id`
File size: 10.6 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Register_Address_Translation_unit_transition.cpp 106 2009-02-09 22:55:26Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_ooo_engine {
15	namespace ooo_engine {
16	namespace rename_unit {
17	namespace register_translation_unit {
18	namespace register_address_translation_unit {
19
20
21	#undef FUNCTION
22	#define FUNCTION "Register_Address_Translation_unit::transition"
23	void Register_Address_Translation_unit::transition (void)
24	{
25	log_begin(Register_Address_Translation_unit,FUNCTION);
26	log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str());
27
28	if (PORT_READ(in_NRESET) == 0)
29	{
30	uint32_t gpr = 1;
31	uint32_t spr = 0;
32
33	for (uint32_t i=0; i<_param->_nb_front_end; i++)
34	for (uint32_t j=0; j<_param->_nb_context[i]; j++)
35	{
36	rat_gpr [i][j][0] = 0;
37
38	for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
39	{
40	rat_gpr [i][j][k] = gpr++;
41	// rat_gpr_update_table[i][j][k] = 0;
42	}
43	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
44	{
45	rat_spr [i][j][k] = spr++;
46	// rat_spr_update_table[i][j][k] = 0;
47	}
48	}
49	}
50	else
51	{
52	// Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0)
53
54	// =====================================================
55	// ====[ INSERT ]=======================================
56	// =====================================================
57	// First : interface insert
58	for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
59	// Test transaction
60	if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK [i])
61	{
62	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * INSERT [%d]",i);
63
64	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
65	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0;
66
67	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id);
68	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id);
69
70	// Test if write
71	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",PORT_READ(in_INSERT_WRITE_RD [i]));
72	if (PORT_READ(in_INSERT_WRITE_RD [i]) == 1)
73	{
74	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]));
75	rat_gpr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RD_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]);
76	}
77
78	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",PORT_READ(in_INSERT_WRITE_RE [i]));
79	if (PORT_READ(in_INSERT_WRITE_RE [i]) == 1)
80	{
81	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]));
82	rat_spr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RE_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]);
83	}
84	}
85
86	// =====================================================
87	// ====[ RETIRE_EVENT ]=================================
88	// =====================================================
89	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
90	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
91	if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j])
92	// Test if event have just occure
93	if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)
94	{
95	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Reset Update Table");
96
97	// Reset update_table
98	for (uint32_t k=0; k<_param->_nb_general_register_logic; k++)
99	rat_gpr_update_table [i][j][k] = 0;
100	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
101	rat_spr_update_table [i][j][k] = 0;
102	}
103
104	// =====================================================
105	// ====[ RETIRE ]=======================================
106	// =====================================================
107	// Second : interface retire
108	// (because if an event on the same thread : the instruction is already renamed)
109	for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
110	if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i])
111	{
112	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE [%d]",i);
113
114	// if no event : no effect, because the RAT content the most recently register
115	// but if they have a event (exception or miss speculation), the rat must restore the oldest value
116	// To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register
117	// the retire interface became of the Re Order Buffer, also is in program sequence !
118
119	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0;
120	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0;
121	Tevent_state_t event_state = PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]);
122
123	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id);
124	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id);
125	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * event_state : %d",event_state);
126
127	if (event_state != EVENT_STATE_NO_EVENT)
128	{
129	// Test if write and have not a previous update
130	if (PORT_READ(in_RETIRE_WRITE_RD [i]) == 1)
131	{
132	Tgeneral_address_t rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]);
133
134	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * retire RD");
135	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * rd_log : %d",rd_log);
136
137	// if (RETIRE_RESTORE_RD_PHY_OLD [i])
138	if (rat_gpr_update_table [front_end_id][context_id][rd_log] == 0)
139	{
140	rat_gpr [front_end_id][context_id][rd_log] = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]);
141	rat_gpr_update_table [front_end_id][context_id][rd_log] = 1;
142	}
143	}
144
145	if (PORT_READ(in_RETIRE_WRITE_RE [i]) == 1)
146	{
147	Tspecial_address_t re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]);
148
149	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * retire RE");
150	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * re_log : %d",re_log);
151
152	// if (RETIRE_RESTORE_RE_PHY_OLD [i])
153	if (rat_spr_update_table [front_end_id][context_id][re_log] == 0)
154	{
155	rat_spr [front_end_id][context_id][re_log] = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]);
156	rat_spr_update_table [front_end_id][context_id][re_log] = 1;
157	}
158	}
159	}
160	}
161	}
162
163	#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true)
164	{
165	uint32_t limit = 4;
166
167	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)");
168	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
169	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
170	{
171	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d]",i,j);
172
173	for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)
174	{
175	std::string str = "";
176	for (uint32_t x=0; x<limit; x++)
177	{
178	uint32_t index = k+x;
179	if (index >= _param->_nb_general_register_logic)
180	break;
181	else
182	str+=toString("GPR[%.4d] - %.5d %.1d \| ",index,rat_gpr[i][j][index],rat_gpr_update_table[i][j][index]);
183	}
184	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str());
185	}
186
187	for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit)
188	{
189	std::string str = "";
190
191	for (uint32_t x=0; x<limit; x++)
192	{
193	uint32_t index = k+x;
194	if (index >= _param->_nb_special_register_logic)
195	break;
196	else
197	str+=toString("SPR[%.4d] - %.5d %.1d \| ",index,rat_spr[i][j][index],rat_spr_update_table[i][j][index]);
198	}
199	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str());
200	}
201	}
202	}
203	#endif
204
205	#ifdef DEBUG_TEST
206	if (1)
207	{
208	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
209	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
210	{
211	for (uint32_t x=0; x<_param->_nb_general_register_logic; ++x)
212	for (uint32_t y=x+1; y<_param->_nb_general_register_logic; ++y)
213	if (rat_gpr[i][j][x] == rat_gpr[i][j][y])
214	throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr[%d][%d][%d] == rat_gpr[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr[i][j][x]));
215	for (uint32_t x=0; x<_param->_nb_special_register_logic; ++x)
216	for (uint32_t y=x+1; y<_param->_nb_special_register_logic; ++y)
217	if (rat_spr[i][j][x] == rat_spr[i][j][y])
218	throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr[%d][%d][%d] == rat_spr[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr[i][j][x]));
219	}
220
221	}
222	#endif
223
224	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
225	end_cycle ();
226	#endif
227
228	log_end(Register_Address_Translation_unit,FUNCTION);
229	};
230
231	}; // end namespace register_address_translation_unit
232	}; // end namespace register_translation_unit
233	}; // end namespace rename_unit
234	}; // end namespace ooo_engine
235	}; // end namespace multi_ooo_engine
236	}; // end namespace core
237
238	}; // end namespace behavioural
239	}; // end namespace morpheo
240	#endif

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