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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp @ 57

Last change on this file since 57 was 57, checked in by rosiere, 17 years ago
VHDL - RegisterFile_Multi_Banked (only partial_crossbar) SystemC - modif Component, interface and co -> ajout du type Tusage_T pour instancier un coposant mais ne demander que le VHDL ou le systemC. Séminaire interne
File size: 9.5 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 1
10
11	#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h"
12	#include "Common/include/Test.h"
13
14	void test (string name,
15	morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * _param)
16	{
17	cout << "<" << name << "> : Simulation SystemC" << endl;
18
19	try
20	{
21	cout << _param->print(1);
22	_param->test();
23	}
24	catch (morpheo::ErrorMorpheo & error)
25	{
26	cout << "<" << name << "> : " << error.what ();
27	return;
28	}
29	catch (...)
30	{
31	cerr << "<" << name << "> : This test must generate a error" << endl;
32	exit (EXIT_FAILURE);
33	}
34
35	#ifdef STATISTICS
36	morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics (5,1000);
37	#endif
38	RegisterFile_Monolithic * registerfile = new RegisterFile_Monolithic (name.c_str()
39	#ifdef STATISTICS
40	,_param_stat
41	#endif
42	,_param);
43
44	#ifdef SYSTEMC
45	/*********************************************************************
46	* Déclarations des signaux
47	*********************************************************************/
48	sc_clock CLOCK ("clock", 1.0, 0.5);
49	sc_signal<Tcontrol_t> NRESET;
50
51	sc_signal<Tcontrol_t> READ_VAL [_param->_nb_port_read];
52	sc_signal<Tcontrol_t> READ_ACK [_param->_nb_port_read];
53	sc_signal<Taddress_t> READ_ADDRESS [_param->_nb_port_read];
54	sc_signal<Tdata_t> READ_DATA [_param->_nb_port_read];
55
56	sc_signal<Tcontrol_t> WRITE_VAL [_param->_nb_port_write];
57	sc_signal<Tcontrol_t> WRITE_ACK [_param->_nb_port_write];
58	sc_signal<Taddress_t> WRITE_ADDRESS [_param->_nb_port_write];
59	sc_signal<Tdata_t> WRITE_DATA [_param->_nb_port_write];
60
61	sc_signal<Tcontrol_t> READ_WRITE_VAL [_param->_nb_port_read_write];
62	sc_signal<Tcontrol_t> READ_WRITE_ACK [_param->_nb_port_read_write];
63	sc_signal<Tcontrol_t> READ_WRITE_RW [_param->_nb_port_read_write];
64	sc_signal<Taddress_t> READ_WRITE_ADDRESS [_param->_nb_port_read_write];
65	sc_signal<Tdata_t> READ_WRITE_RDATA [_param->_nb_port_read_write];
66	sc_signal<Tdata_t> READ_WRITE_WDATA [_param->_nb_port_read_write];
67
68	/********************************************************
69	* Instanciation
70	********************************************************/
71
72	cout << "<" << name << "> Instanciation of registerfile" << endl;
73
74	(*(registerfile->in_CLOCK)) (CLOCK);
75	(*(registerfile->in_NRESET)) (NRESET);
76
77	for (uint32_t i=0; i<_param->_nb_port_read; i++)
78	{
79	(*(registerfile-> in_READ_VAL [i])) (READ_VAL [i]);
80	(*(registerfile->out_READ_ACK [i])) (READ_ACK [i]);
81	(*(registerfile-> in_READ_ADDRESS [i])) (READ_ADDRESS [i]);
82	(*(registerfile->out_READ_DATA [i])) (READ_DATA [i]);
83	}
84	for (uint32_t i=0; i<_param->_nb_port_write; i++)
85	{
86	(*(registerfile-> in_WRITE_VAL [i])) (WRITE_VAL [i]);
87	(*(registerfile->out_WRITE_ACK [i])) (WRITE_ACK [i]);
88	(*(registerfile-> in_WRITE_ADDRESS [i])) (WRITE_ADDRESS [i]);
89	(*(registerfile-> in_WRITE_DATA [i])) (WRITE_DATA [i]);
90	}
91	for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
92	{
93	(*(registerfile-> in_READ_WRITE_VAL [i])) (READ_WRITE_VAL [i]);
94	(*(registerfile->out_READ_WRITE_ACK [i])) (READ_WRITE_ACK [i]);
95	(*(registerfile-> in_READ_WRITE_RW [i])) (READ_WRITE_RW [i]);
96	(*(registerfile-> in_READ_WRITE_ADDRESS [i])) (READ_WRITE_ADDRESS [i]);
97	(*(registerfile-> in_READ_WRITE_WDATA [i])) (READ_WRITE_WDATA [i]);
98	(*(registerfile->out_READ_WRITE_RDATA [i])) (READ_WRITE_RDATA [i]);
99	}
100
101	cout << "<" << name << "> Start Simulation ............" << endl;
102	Time * _time = new Time();
103
104	/********************************************************
105	* Simulation - Begin
106	********************************************************/
107
108	// Initialisation
109
110	sc_start(0);
111
112	for (uint32_t i=0; i<_param->_nb_port_write; i++)
113	WRITE_VAL [i] .write (0);
114	for (uint32_t i=0; i<_param->_nb_port_read; i++)
115	READ_VAL [i] .write (0);
116	for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
117	READ_WRITE_VAL [i] .write (0);
118
119	NRESET.write(0);
120
121	sc_start(5);
122
123	NRESET.write(1);
124
125
126	for (uint32_t nb_iteration=0; nb_iteration < NB_ITERATION; nb_iteration ++)
127	{
128	cout << "<" << name << "> 1) Write the RegisterFile (no read)" << endl;
129
130	// random init
131	uint32_t grain = 0;
132	//uint32_t grain = static_cast<uint32_t>(time(NULL));
133
134	srand(grain);
135
136	Tdata_t tab [_param->_nb_word];
137
138	for (uint32_t i=0; i<_param->_nb_word; i++)
139	tab[i]= rand()%(1<<(_param->_size_word-1));
140
141	Taddress_t address_next = 0;
142	Taddress_t nb_ack = 0;
143
144	while (nb_ack < _param->_nb_word)
145	{
146	cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl;
147
148	for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++)
149	{
150	if ((address_next < _param->_nb_word) and
151	(WRITE_VAL [num_port].read() == 0))
152	{
153	cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl;
154
155	WRITE_VAL [num_port] .write(1);
156	WRITE_DATA [num_port] .write(tab[address_next]);
157	WRITE_ADDRESS [num_port] .write(address_next++);
158
159	// Address can be not a multiple of nb_port_write
160	if (address_next >= _param->_nb_word)
161	break;
162	}
163	}
164
165	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
166	{
167	if ((address_next < _param->_nb_word) and
168	(READ_WRITE_VAL [num_port].read() == 0))
169	{
170	cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl;
171
172	READ_WRITE_VAL [num_port] .write(1);
173	READ_WRITE_RW [num_port] .write(RW_WRITE);
174	READ_WRITE_WDATA [num_port] .write(tab[address_next]);
175	READ_WRITE_ADDRESS [num_port] .write(address_next++);
176
177	// Address can be not a multiple of nb_port_write
178	if (address_next >= _param->_nb_word)
179	break;
180	}
181	}
182
183	sc_start(1);
184
185	// reset write_val port
186	for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++)
187	{
188	if ((WRITE_ACK [num_port].read() == 1) and
189	(WRITE_VAL [num_port].read() == 1))
190	{
191	WRITE_VAL [num_port] .write(0);
192	nb_ack ++;
193	}
194	}
195	// reset write_val port
196	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
197	{
198	if ((READ_WRITE_ACK [num_port].read() == 1) and
199	(READ_WRITE_VAL [num_port].read() == 1))
200	{
201	READ_WRITE_VAL [num_port] .write(0);
202	nb_ack ++;
203	}
204	}
205
206	sc_start(0);
207	}
208
209	address_next = 0;
210	nb_ack = 0;
211
212	cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl;
213
214	Tdata_t read_address [_param->_nb_port_read];
215	Tdata_t read_write_address [_param->_nb_port_read_write];
216
217	while (nb_ack < _param->_nb_word)
218	{
219	cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl;
220
221	for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
222	{
223	if ((address_next < _param->_nb_word) and
224	(READ_VAL [num_port].read() == 0))
225	{
226	read_address [num_port] = address_next++;
227
228	READ_VAL [num_port].write(1);
229	READ_ADDRESS [num_port].write(read_address [num_port]);
230
231	if (address_next >= _param->_nb_word)
232	break;
233	}
234	}
235
236	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
237	{
238	if ((address_next < _param->_nb_word) and
239	(READ_WRITE_VAL [num_port].read() == 0))
240	{
241	read_write_address [num_port] = address_next++;
242
243	READ_WRITE_VAL [num_port].write(1);
244	READ_WRITE_RW [num_port].write(RW_READ);
245	READ_WRITE_ADDRESS [num_port].write(read_write_address [num_port]);
246
247	if (address_next >= _param->_nb_word)
248	break;
249	}
250	}
251
252
253	sc_start(1);
254
255	// reset write_val port
256	for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
257	{
258	if ((READ_ACK [num_port].read() == 1) and
259	(READ_VAL [num_port].read() == 1))
260	{
261	READ_VAL [num_port] .write(0);
262
263	cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl;
264
265	TEST(Tdata_t,READ_DATA [num_port].read(), tab[read_address [num_port]]);
266	nb_ack ++;
267	}
268	}
269
270	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
271	{
272	if ((READ_WRITE_ACK [num_port].read() == 1) and
273	(READ_WRITE_VAL [num_port].read() == 1))
274	{
275	READ_WRITE_VAL [num_port] .write(0);
276
277	cout << "(" << num_port << ") [" << read_write_address [num_port] << "] => " << READ_WRITE_RDATA [num_port].read() << endl;
278
279	TEST(Tdata_t,READ_WRITE_RDATA [num_port].read(), tab[read_write_address [num_port]]);
280	nb_ack ++;
281	}
282	}
283
284	sc_start(0);
285	}
286	}
287
288	/********************************************************
289	* Simulation - End
290	********************************************************/
291
292	TEST_STR(bool,true,true, "End of Simulation");
293	delete _time;
294	cout << "<" << name << "> ............ Stop Simulation" << endl;
295
296	#endif
297
298	delete registerfile;
299	}

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