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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp @ 71

Last change on this file since 71 was 71, checked in by rosiere, 16 years ago
Modification of Statisctics Add a new systemC component : Load_Store_Queue (tested with one benchmark and one configuration). Store don't supported the Data Buss Error (Load is supported)
File size: 9.6 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 1
10
11	#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h"
12	#include "Common/include/Test.h"
13
14	void test (string name,
15	morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * _param)
16	{
17	cout << "<" << name << "> : Simulation SystemC" << endl;
18
19	try
20	{
21	cout << _param->print(1);
22	_param->test();
23	}
24	catch (morpheo::ErrorMorpheo & error)
25	{
26	cout << "<" << name << "> : " << error.what ();
27	return;
28	}
29	catch (...)
30	{
31	cerr << "<" << name << "> : This test must generate a error" << endl;
32	exit (EXIT_FAILURE);
33	}
34
35	#ifdef STATISTICS
36	morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics (5,100);
37	#endif
38	RegisterFile_Monolithic * registerfile = new RegisterFile_Monolithic (name.c_str()
39	#ifdef STATISTICS
40	,_param_stat
41	#endif
42	,_param);
43
44	#ifdef SYSTEMC
45	/*********************************************************************
46	* Déclarations des signaux
47	*********************************************************************/
48	sc_clock CLOCK ("clock", 1.0, 0.5);
49	sc_signal<Tcontrol_t> NRESET;
50
51	sc_signal<Tcontrol_t> READ_VAL [_param->_nb_port_read];
52	sc_signal<Tcontrol_t> READ_ACK [_param->_nb_port_read];
53	sc_signal<Taddress_t> READ_ADDRESS [_param->_nb_port_read];
54	sc_signal<Tdata_t> READ_DATA [_param->_nb_port_read];
55
56	sc_signal<Tcontrol_t> WRITE_VAL [_param->_nb_port_write];
57	sc_signal<Tcontrol_t> WRITE_ACK [_param->_nb_port_write];
58	sc_signal<Taddress_t> WRITE_ADDRESS [_param->_nb_port_write];
59	sc_signal<Tdata_t> WRITE_DATA [_param->_nb_port_write];
60
61	sc_signal<Tcontrol_t> READ_WRITE_VAL [_param->_nb_port_read_write];
62	sc_signal<Tcontrol_t> READ_WRITE_ACK [_param->_nb_port_read_write];
63	sc_signal<Tcontrol_t> READ_WRITE_RW [_param->_nb_port_read_write];
64	sc_signal<Taddress_t> READ_WRITE_ADDRESS [_param->_nb_port_read_write];
65	sc_signal<Tdata_t> READ_WRITE_RDATA [_param->_nb_port_read_write];
66	sc_signal<Tdata_t> READ_WRITE_WDATA [_param->_nb_port_read_write];
67
68	/********************************************************
69	* Instanciation
70	********************************************************/
71
72	cout << "<" << name << "> Instanciation of registerfile" << endl;
73
74	(*(registerfile->in_CLOCK)) (CLOCK);
75	(*(registerfile->in_NRESET)) (NRESET);
76
77	for (uint32_t i=0; i<_param->_nb_port_read; i++)
78	{
79	(*(registerfile-> in_READ_VAL [i])) (READ_VAL [i]);
80	(*(registerfile->out_READ_ACK [i])) (READ_ACK [i]);
81	if (_param->_have_port_address)
82	(*(registerfile-> in_READ_ADDRESS [i])) (READ_ADDRESS [i]);
83	(*(registerfile->out_READ_DATA [i])) (READ_DATA [i]);
84	}
85	for (uint32_t i=0; i<_param->_nb_port_write; i++)
86	{
87	(*(registerfile-> in_WRITE_VAL [i])) (WRITE_VAL [i]);
88	(*(registerfile->out_WRITE_ACK [i])) (WRITE_ACK [i]);
89	if (_param->_have_port_address)
90	(*(registerfile-> in_WRITE_ADDRESS [i])) (WRITE_ADDRESS [i]);
91	(*(registerfile-> in_WRITE_DATA [i])) (WRITE_DATA [i]);
92	}
93	for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
94	{
95	(*(registerfile-> in_READ_WRITE_VAL [i])) (READ_WRITE_VAL [i]);
96	(*(registerfile->out_READ_WRITE_ACK [i])) (READ_WRITE_ACK [i]);
97	(*(registerfile-> in_READ_WRITE_RW [i])) (READ_WRITE_RW [i]);
98	if (_param->_have_port_address)
99	(*(registerfile-> in_READ_WRITE_ADDRESS [i])) (READ_WRITE_ADDRESS [i]);
100	(*(registerfile-> in_READ_WRITE_WDATA [i])) (READ_WRITE_WDATA [i]);
101	(*(registerfile->out_READ_WRITE_RDATA [i])) (READ_WRITE_RDATA [i]);
102	}
103
104	cout << "<" << name << "> Start Simulation ............" << endl;
105	Time * _time = new Time();
106
107	/********************************************************
108	* Simulation - Begin
109	********************************************************/
110
111	// Initialisation
112
113	sc_start(0);
114
115	for (uint32_t i=0; i<_param->_nb_port_write; i++)
116	WRITE_VAL [i] .write (0);
117	for (uint32_t i=0; i<_param->_nb_port_read; i++)
118	READ_VAL [i] .write (0);
119	for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
120	READ_WRITE_VAL [i] .write (0);
121
122	NRESET.write(0);
123
124	sc_start(5);
125
126	NRESET.write(1);
127
128
129	for (uint32_t nb_iteration=0; nb_iteration < NB_ITERATION; nb_iteration ++)
130	{
131	cout << "<" << name << "> 1) Write the RegisterFile (no read)" << endl;
132
133	// random init
134	uint32_t grain = 0;
135	//uint32_t grain = static_cast<uint32_t>(time(NULL));
136
137	srand(grain);
138
139	Tdata_t tab [_param->_nb_word];
140
141	for (uint32_t i=0; i<_param->_nb_word; i++)
142	tab[i]= rand()%(1<<(_param->_size_word-1));
143
144	Taddress_t address_next = 0;
145	Taddress_t nb_ack = 0;
146
147	while (nb_ack < _param->_nb_word)
148	{
149	cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl;
150
151	for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++)
152	{
153	if ((address_next < _param->_nb_word) and
154	(WRITE_VAL [num_port].read() == 0))
155	{
156	cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl;
157
158	WRITE_VAL [num_port] .write(1);
159	WRITE_DATA [num_port] .write(tab[address_next]);
160	WRITE_ADDRESS [num_port] .write(address_next++);
161
162	// Address can be not a multiple of nb_port_write
163	if (address_next >= _param->_nb_word)
164	break;
165	}
166	}
167
168	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
169	{
170	if ((address_next < _param->_nb_word) and
171	(READ_WRITE_VAL [num_port].read() == 0))
172	{
173	cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl;
174
175	READ_WRITE_VAL [num_port] .write(1);
176	READ_WRITE_RW [num_port] .write(RW_WRITE);
177	READ_WRITE_WDATA [num_port] .write(tab[address_next]);
178	READ_WRITE_ADDRESS [num_port] .write(address_next++);
179
180	// Address can be not a multiple of nb_port_write
181	if (address_next >= _param->_nb_word)
182	break;
183	}
184	}
185
186	sc_start(1);
187
188	// reset write_val port
189	for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++)
190	{
191	if ((WRITE_ACK [num_port].read() == 1) and
192	(WRITE_VAL [num_port].read() == 1))
193	{
194	WRITE_VAL [num_port] .write(0);
195	nb_ack ++;
196	}
197	}
198	// reset write_val port
199	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
200	{
201	if ((READ_WRITE_ACK [num_port].read() == 1) and
202	(READ_WRITE_VAL [num_port].read() == 1))
203	{
204	READ_WRITE_VAL [num_port] .write(0);
205	nb_ack ++;
206	}
207	}
208
209	sc_start(0);
210	}
211
212	address_next = 0;
213	nb_ack = 0;
214
215	cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl;
216
217	Tdata_t read_address [_param->_nb_port_read];
218	Tdata_t read_write_address [_param->_nb_port_read_write];
219
220	while (nb_ack < _param->_nb_word)
221	{
222	cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl;
223
224	for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
225	{
226	if ((address_next < _param->_nb_word) and
227	(READ_VAL [num_port].read() == 0))
228	{
229	read_address [num_port] = address_next++;
230
231	READ_VAL [num_port].write(1);
232	READ_ADDRESS [num_port].write(read_address [num_port]);
233
234	if (address_next >= _param->_nb_word)
235	break;
236	}
237	}
238
239	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
240	{
241	if ((address_next < _param->_nb_word) and
242	(READ_WRITE_VAL [num_port].read() == 0))
243	{
244	read_write_address [num_port] = address_next++;
245
246	READ_WRITE_VAL [num_port].write(1);
247	READ_WRITE_RW [num_port].write(RW_READ);
248	READ_WRITE_ADDRESS [num_port].write(read_write_address [num_port]);
249
250	if (address_next >= _param->_nb_word)
251	break;
252	}
253	}
254
255
256	sc_start(1);
257
258	// reset write_val port
259	for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
260	{
261	if ((READ_ACK [num_port].read() == 1) and
262	(READ_VAL [num_port].read() == 1))
263	{
264	READ_VAL [num_port] .write(0);
265
266	cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl;
267
268	TEST(Tdata_t,READ_DATA [num_port].read(), tab[read_address [num_port]]);
269	nb_ack ++;
270	}
271	}
272
273	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
274	{
275	if ((READ_WRITE_ACK [num_port].read() == 1) and
276	(READ_WRITE_VAL [num_port].read() == 1))
277	{
278	READ_WRITE_VAL [num_port] .write(0);
279
280	cout << "(" << num_port << ") [" << read_write_address [num_port] << "] => " << READ_WRITE_RDATA [num_port].read() << endl;
281
282	TEST(Tdata_t,READ_WRITE_RDATA [num_port].read(), tab[read_write_address [num_port]]);
283	nb_ack ++;
284	}
285	}
286
287	sc_start(0);
288	}
289	}
290
291	/********************************************************
292	* Simulation - End
293	********************************************************/
294
295	TEST_STR(bool,true,true, "End of Simulation");
296	delete _time;
297	cout << "<" << name << "> ............ Stop Simulation" << endl;
298
299	#endif
300
301	delete registerfile;
302	}

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