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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp @ 94

Last change on this file since 94 was 94, checked in by rosiere, 15 years ago
Update document on Vhdl generation.
Property svn:keywords set to `Id`
File size: 10.1 KB

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1	/*
2	* $Id: test.cpp 94 2008-12-15 11:04:03Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 1
10	#define CYCLE_MAX 100000*NB_ITERATION
11	#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h"
12	#include "Common/include/Test.h"
13
14	void test (string name,
15	morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * _param)
16	{
17	cout << "<" << name << "> : Simulation SystemC" << endl;
18
19	try
20	{
21	cout << _param->print(1);
22	_param->test();
23	}
24	catch (morpheo::ErrorMorpheo & error)
25	{
26	cout << "<" << name << "> : " << error.what ();
27	return;
28	}
29	catch (...)
30	{
31	cerr << "<" << name << "> : This test must generate a error" << endl;
32	exit (EXIT_FAILURE);
33	}
34
35	Tusage_t _usage = USE_ALL;
36
37	// _usage = usage_unset(_usage,USE_SYSTEMC );
38	// _usage = usage_unset(_usage,USE_VHDL );
39	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
40	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
41	// _usage = usage_unset(_usage,USE_POSITION );
42	// _usage = usage_unset(_usage,USE_STATISTICS );
43	// _usage = usage_unset(_usage,USE_INFORMATION );
44
45	#ifdef STATISTICS
46	morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics (5,100);
47	#endif
48	RegisterFile_Monolithic * registerfile = new RegisterFile_Monolithic
49	(name.c_str()
50	#ifdef STATISTICS
51	,_param_stat
52	#endif
53	,_param
54	,_usage);
55
56	#ifdef SYSTEMC
57	/*********************************************************************
58	* Déclarations des signaux
59	*********************************************************************/
60	sc_clock CLOCK ("clock", 1.0, 0.5);
61	sc_signal<Tcontrol_t> NRESET;
62
63	sc_signal<Tcontrol_t> READ_VAL [_param->_nb_port_read];
64	sc_signal<Tcontrol_t> READ_ACK [_param->_nb_port_read];
65	sc_signal<Taddress_t> READ_ADDRESS [_param->_nb_port_read];
66	sc_signal<Tdata_t> READ_DATA [_param->_nb_port_read];
67
68	sc_signal<Tcontrol_t> WRITE_VAL [_param->_nb_port_write];
69	sc_signal<Tcontrol_t> WRITE_ACK [_param->_nb_port_write];
70	sc_signal<Taddress_t> WRITE_ADDRESS [_param->_nb_port_write];
71	sc_signal<Tdata_t> WRITE_DATA [_param->_nb_port_write];
72
73	sc_signal<Tcontrol_t> READ_WRITE_VAL [_param->_nb_port_read_write];
74	sc_signal<Tcontrol_t> READ_WRITE_ACK [_param->_nb_port_read_write];
75	sc_signal<Tcontrol_t> READ_WRITE_RW [_param->_nb_port_read_write];
76	sc_signal<Taddress_t> READ_WRITE_ADDRESS [_param->_nb_port_read_write];
77	sc_signal<Tdata_t> READ_WRITE_RDATA [_param->_nb_port_read_write];
78	sc_signal<Tdata_t> READ_WRITE_WDATA [_param->_nb_port_read_write];
79
80	/********************************************************
81	* Instanciation
82	********************************************************/
83
84	cout << "<" << name << "> Instanciation of registerfile" << endl;
85
86	(*(registerfile->in_CLOCK)) (CLOCK);
87	(*(registerfile->in_NRESET)) (NRESET);
88
89	for (uint32_t i=0; i<_param->_nb_port_read; i++)
90	{
91	(*(registerfile-> in_READ_VAL [i])) (READ_VAL [i]);
92	(*(registerfile->out_READ_ACK [i])) (READ_ACK [i]);
93	if (_param->_have_port_address)
94	(*(registerfile-> in_READ_ADDRESS [i])) (READ_ADDRESS [i]);
95	(*(registerfile->out_READ_DATA [i])) (READ_DATA [i]);
96	}
97	for (uint32_t i=0; i<_param->_nb_port_write; i++)
98	{
99	(*(registerfile-> in_WRITE_VAL [i])) (WRITE_VAL [i]);
100	(*(registerfile->out_WRITE_ACK [i])) (WRITE_ACK [i]);
101	if (_param->_have_port_address)
102	(*(registerfile-> in_WRITE_ADDRESS [i])) (WRITE_ADDRESS [i]);
103	(*(registerfile-> in_WRITE_DATA [i])) (WRITE_DATA [i]);
104	}
105	for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
106	{
107	(*(registerfile-> in_READ_WRITE_VAL [i])) (READ_WRITE_VAL [i]);
108	(*(registerfile->out_READ_WRITE_ACK [i])) (READ_WRITE_ACK [i]);
109	(*(registerfile-> in_READ_WRITE_RW [i])) (READ_WRITE_RW [i]);
110	if (_param->_have_port_address)
111	(*(registerfile-> in_READ_WRITE_ADDRESS [i])) (READ_WRITE_ADDRESS [i]);
112	(*(registerfile-> in_READ_WRITE_WDATA [i])) (READ_WRITE_WDATA [i]);
113	(*(registerfile->out_READ_WRITE_RDATA [i])) (READ_WRITE_RDATA [i]);
114	}
115
116	cout << "<" << name << "> Start Simulation ............" << endl;
117	Time * _time = new Time();
118
119	/********************************************************
120	* Simulation - Begin
121	********************************************************/
122
123	// Initialisation
124
125	sc_start(0);
126
127	for (uint32_t i=0; i<_param->_nb_port_write; i++)
128	WRITE_VAL [i] .write (0);
129	for (uint32_t i=0; i<_param->_nb_port_read; i++)
130	READ_VAL [i] .write (0);
131	for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
132	READ_WRITE_VAL [i] .write (0);
133
134	NRESET.write(0);
135
136	sc_start(5);
137
138	NRESET.write(1);
139
140
141	for (uint32_t nb_iteration=0; nb_iteration < NB_ITERATION; nb_iteration ++)
142	{
143	cout << "<" << name << "> 1) Write the RegisterFile (no read)" << endl;
144
145	// random init
146	uint32_t grain = 0;
147	//uint32_t grain = static_cast<uint32_t>(time(NULL));
148
149	srand(grain);
150
151	Tdata_t tab [_param->_nb_word];
152
153	for (uint32_t i=0; i<_param->_nb_word; i++)
154	tab[i]= rand()%(1<<(_param->_size_word-1));
155
156	Taddress_t address_next = 0;
157	Taddress_t nb_ack = 0;
158
159	while (nb_ack < _param->_nb_word)
160	{
161	cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl;
162
163	for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++)
164	{
165	if ((address_next < _param->_nb_word) and
166	(WRITE_VAL [num_port].read() == 0))
167	{
168	cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl;
169
170	WRITE_VAL [num_port] .write(1);
171	WRITE_DATA [num_port] .write(tab[address_next]);
172	WRITE_ADDRESS [num_port] .write(address_next++);
173
174	// Address can be not a multiple of nb_port_write
175	if (address_next >= _param->_nb_word)
176	break;
177	}
178	}
179
180	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
181	{
182	if ((address_next < _param->_nb_word) and
183	(READ_WRITE_VAL [num_port].read() == 0))
184	{
185	cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl;
186
187	READ_WRITE_VAL [num_port] .write(1);
188	READ_WRITE_RW [num_port] .write(RW_WRITE);
189	READ_WRITE_WDATA [num_port] .write(tab[address_next]);
190	READ_WRITE_ADDRESS [num_port] .write(address_next++);
191
192	// Address can be not a multiple of nb_port_write
193	if (address_next >= _param->_nb_word)
194	break;
195	}
196	}
197
198	sc_start(1);
199
200	// reset write_val port
201	for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++)
202	{
203	if ((WRITE_ACK [num_port].read() == 1) and
204	(WRITE_VAL [num_port].read() == 1))
205	{
206	WRITE_VAL [num_port] .write(0);
207	nb_ack ++;
208	}
209	}
210	// reset write_val port
211	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
212	{
213	if ((READ_WRITE_ACK [num_port].read() == 1) and
214	(READ_WRITE_VAL [num_port].read() == 1))
215	{
216	READ_WRITE_VAL [num_port] .write(0);
217	nb_ack ++;
218	}
219	}
220
221	sc_start(0);
222	}
223
224	address_next = 0;
225	nb_ack = 0;
226
227	cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl;
228
229	Tdata_t read_address [_param->_nb_port_read];
230	Tdata_t read_write_address [_param->_nb_port_read_write];
231
232	while (nb_ack < _param->_nb_word)
233	{
234	cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl;
235
236	for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
237	{
238	if ((address_next < _param->_nb_word) and
239	(READ_VAL [num_port].read() == 0))
240	{
241	read_address [num_port] = address_next++;
242
243	READ_VAL [num_port].write(1);
244	READ_ADDRESS [num_port].write(read_address [num_port]);
245
246	if (address_next >= _param->_nb_word)
247	break;
248	}
249	}
250
251	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
252	{
253	if ((address_next < _param->_nb_word) and
254	(READ_WRITE_VAL [num_port].read() == 0))
255	{
256	read_write_address [num_port] = address_next++;
257
258	READ_WRITE_VAL [num_port].write(1);
259	READ_WRITE_RW [num_port].write(RW_READ);
260	READ_WRITE_ADDRESS [num_port].write(read_write_address [num_port]);
261
262	if (address_next >= _param->_nb_word)
263	break;
264	}
265	}
266
267
268	sc_start(1);
269
270	// reset write_val port
271	for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
272	{
273	if ((READ_ACK [num_port].read() == 1) and
274	(READ_VAL [num_port].read() == 1))
275	{
276	READ_VAL [num_port] .write(0);
277
278	cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl;
279
280	TEST(Tdata_t,READ_DATA [num_port].read(), tab[read_address [num_port]]);
281	nb_ack ++;
282	}
283	}
284
285	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
286	{
287	if ((READ_WRITE_ACK [num_port].read() == 1) and
288	(READ_WRITE_VAL [num_port].read() == 1))
289	{
290	READ_WRITE_VAL [num_port] .write(0);
291
292	cout << "(" << num_port << ") [" << read_write_address [num_port] << "] => " << READ_WRITE_RDATA [num_port].read() << endl;
293
294	TEST(Tdata_t,READ_WRITE_RDATA [num_port].read(), tab[read_write_address [num_port]]);
295	nb_ack ++;
296	}
297	}
298
299	sc_start(0);
300	}
301	}
302
303	/********************************************************
304	* Simulation - End
305	********************************************************/
306
307	TEST_STR(bool,true,true, "End of Simulation");
308	delete _time;
309	cout << "<" << name << "> ............ Stop Simulation" << endl;
310
311	#endif
312
313	delete registerfile;
314	}

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