source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info @ 58

Last change on this file since 58 was 58, checked in by rosiere, 17 years ago

Vhdl : RegisterFile_Multi_Banked - "full crossbar"
Correction d'un bug pour le "partial crossbar"
File size: 2.6 KB
Line 
1
2# RegisterFile_Multi_Banked_0
3target_dep      all     RegisterFile_Multi_Banked_0.ngc
4target_dep      RegisterFile_Multi_Banked_0.ngc RegisterFile_Multi_Banked_0.prj
5target_dep      RegisterFile_Multi_Banked_0.prj RegisterFile_Multi_Banked_0_bank_Pack.vhdl RegisterFile_Multi_Banked_0_bank.vhdl RegisterFile_Multi_Banked_0_Pack.vhdl RegisterFile_Multi_Banked_0_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_4_ports.vhdl RegisterFile_Multi_Banked_0.vhdl
6
7# RegisterFile_Multi_Banked_1
8target_dep      all     RegisterFile_Multi_Banked_1.ngc
9target_dep      RegisterFile_Multi_Banked_1.ngc RegisterFile_Multi_Banked_1.prj
10target_dep      RegisterFile_Multi_Banked_1.prj RegisterFile_Multi_Banked_1_bank_Pack.vhdl RegisterFile_Multi_Banked_1_bank.vhdl RegisterFile_Multi_Banked_1_Pack.vhdl RegisterFile_Multi_Banked_1_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_4_ports.vhdl RegisterFile_Multi_Banked_1.vhdl
11
12# RegisterFile_Multi_Banked_2
13target_dep      all     RegisterFile_Multi_Banked_2.ngc
14target_dep      RegisterFile_Multi_Banked_2.ngc RegisterFile_Multi_Banked_2.prj
15target_dep      RegisterFile_Multi_Banked_2.prj RegisterFile_Multi_Banked_2_bank_Pack.vhdl RegisterFile_Multi_Banked_2_bank.vhdl RegisterFile_Multi_Banked_2_Pack.vhdl RegisterFile_Multi_Banked_2_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_2_select_4_ports.vhdl RegisterFile_Multi_Banked_2.vhdl
16
17# RegisterFile_Multi_Banked_3
18target_dep      all     RegisterFile_Multi_Banked_3.ngc
19target_dep      RegisterFile_Multi_Banked_3.ngc RegisterFile_Multi_Banked_3.prj
20target_dep      RegisterFile_Multi_Banked_3.prj RegisterFile_Multi_Banked_3_bank_Pack.vhdl RegisterFile_Multi_Banked_3_bank.vhdl RegisterFile_Multi_Banked_3_Pack.vhdl RegisterFile_Multi_Banked_3_select_8_ports_Pack.vhdl RegisterFile_Multi_Banked_3_select_8_ports.vhdl RegisterFile_Multi_Banked_3.vhdl
21
22# RegisterFile_Multi_Banked_4
23target_dep      all     RegisterFile_Multi_Banked_4.ngc
24target_dep      RegisterFile_Multi_Banked_4.ngc RegisterFile_Multi_Banked_4.prj
25target_dep      RegisterFile_Multi_Banked_4.prj RegisterFile_Multi_Banked_4_bank_Pack.vhdl RegisterFile_Multi_Banked_4_bank.vhdl RegisterFile_Multi_Banked_4_Pack.vhdl RegisterFile_Multi_Banked_4_select_8_ports_Pack.vhdl RegisterFile_Multi_Banked_4_select_8_ports.vhdl RegisterFile_Multi_Banked_4.vhdl
26
27# RegisterFile_Multi_Banked_5
28target_dep      all     RegisterFile_Multi_Banked_5.ngc
29target_dep      RegisterFile_Multi_Banked_5.ngc RegisterFile_Multi_Banked_5.prj
30target_dep      RegisterFile_Multi_Banked_5.prj RegisterFile_Multi_Banked_5_bank_Pack.vhdl RegisterFile_Multi_Banked_5_bank.vhdl RegisterFile_Multi_Banked_5_Pack.vhdl RegisterFile_Multi_Banked_5_select_8_ports_Pack.vhdl RegisterFile_Multi_Banked_5_select_8_ports.vhdl RegisterFile_Multi_Banked_5.vhdl
31
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