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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/Parameters.cpp @ 62

Last change on this file since 62 was 62, checked in by rosiere, 17 years ago
Modification en profondeur de Component-port_map. Compilation ok pour Register_unit ... a tester (systemC et vhdl)
File size: 5.9 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	*/
7
8	#include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Parameters.h"
9	#include "Common/include/BitManipulation.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace generic {
14	namespace registerfile {
15	namespace registerfile_multi_banked {
16
17
18	Parameters::Parameters (uint32_t nb_port_read ,
19	uint32_t nb_port_write ,
20	uint32_t nb_word ,
21	uint32_t size_word ,
22	uint32_t nb_bank ,
23	uint32_t nb_port_read_by_bank ,
24	uint32_t nb_port_write_by_bank,
25	Tcrossbar_t crossbar ):
26	_nb_port_read (nb_port_read ),
27	_nb_port_write (nb_port_write ),
28	_nb_word (nb_word ),
29	_size_word (size_word ),
30	_nb_bank (nb_bank ),
31	_nb_port_read_by_bank (nb_port_read_by_bank ),
32	_nb_port_write_by_bank (nb_port_write_by_bank),
33	_crossbar (crossbar ),
34	_size_address (static_cast<uint32_t>(ceil(log2(_nb_word)))),
35	_size_address_by_bank (_size_address - static_cast<uint32_t>(ceil(log2(_nb_bank)))),
36
37	// Address : [....................] [size_address-1:0]
38	// Bank : [....] [size_address-1:size_address-1-log2(nb_bank)]
39	// num_reg : ]...............] [size_address-2-log2(nb_bank):0]
40	_bank_shift (_size_address_by_bank),
41	_bank_mask (gen_mask<Taddress_t>(static_cast<Taddress_t>(ceil(log2(_nb_bank))))),
42	_num_reg_shift (0),
43	_num_reg_mask (gen_mask<Taddress_t>(_size_address_by_bank)),
44	_nb_word_by_bank (_nb_word / _nb_bank),
45	_have_port_address (_size_address != 0),
46	_have_bank_port_address(_size_address_by_bank != 0)
47	{
48	log_printf(FUNC,RegisterFile_Multi_Banked,"Parameters","Begin");
49
50	if (_crossbar == PARTIAL_CROSSBAR)
51	{
52	log_printf(TRACE,RegisterFile_Multi_Banked,"Parameters","Case : _crossbar == PARTIAL_CROSSBAR");
53
54	// All port_src is connected with one port_dest on each bank
55
56	_link_port_read_to_bank_read = new uint32_t [_nb_port_read ];
57	_link_port_write_to_bank_write = new uint32_t [_nb_port_write];
58
59	// init
60	for (uint32_t i=0; i<_nb_port_read ;i++)
61	{
62	uint32_t x = i%_nb_port_read_by_bank;
63	_link_port_read_to_bank_read [i] = x;
64	}
65	for (uint32_t i=0; i<_nb_port_write;i++)
66	{
67	uint32_t x = i%_nb_port_write_by_bank;
68	_link_port_write_to_bank_write [i] = x;
69	}
70
71
72	log_printf(TRACE,RegisterFile_Multi_Banked,"Parameters"," * _link_port_read_to_bank_read");
73	for (uint32_t i=0; i<_nb_port_read ;i++)
74	{
75	log_printf(TRACE,RegisterFile_Multi_Banked,"Parameters"," * Read in [%d] to out [%d]",i,_link_port_read_to_bank_read [i]);
76	}
77	log_printf(TRACE,RegisterFile_Multi_Banked,"Parameters"," * _link_port_write_to_bank_write");
78	for (uint32_t i=0; i<_nb_port_write ;i++)
79	{
80	log_printf(TRACE,RegisterFile_Multi_Banked,"Parameters"," * Write in [%d] to out [%d]",i,_link_port_write_to_bank_write [i]);
81	}
82	}
83	// else : don't allocate
84
85	test();
86	log_printf(FUNC,RegisterFile_Multi_Banked,"Parameters","End");
87	};
88
89	Parameters::Parameters (Parameters & param):
90	_nb_port_read (param._nb_port_read ),
91	_nb_port_write (param._nb_port_write ),
92	_nb_word (param._nb_word ),
93	_size_word (param._size_word ),
94	_nb_bank (param._nb_bank ),
95	_nb_port_read_by_bank (param._nb_port_read_by_bank ),
96	_nb_port_write_by_bank (param._nb_port_write_by_bank),
97	_crossbar (param._crossbar ),
98	_size_address (param._size_address ),
99	_size_address_by_bank (param._size_address_by_bank ),
100	_bank_shift (param._bank_shift ),
101	_bank_mask (param._bank_mask ),
102	_num_reg_shift (param._num_reg_shift ),
103	_num_reg_mask (param._num_reg_mask ),
104	_nb_word_by_bank (param._nb_word_by_bank ),
105	_have_port_address (param._have_port_address ),
106	_have_bank_port_address(param._have_bank_port_address)
107	{
108	log_printf(FUNC,RegisterFile_Multi_Banked,"Parameters (copy)","Begin");
109
110	if (_crossbar == PARTIAL_CROSSBAR)
111	{
112	// All port_src is connected with one port_dest on each bank
113
114	_link_port_read_to_bank_read = new uint32_t [_nb_port_read ];
115	// _link_port_read_to_num_bank = new uint32_t [_nb_port_read ];
116	_link_port_write_to_bank_write = new uint32_t [_nb_port_write];
117	// _link_port_write_to_num_bank = new uint32_t [_nb_port_write];
118
119	for (uint32_t i=0; i<_nb_port_read ;i++)
120	{
121	_link_port_read_to_bank_read [i] = param._link_port_read_to_bank_read [i];
122	// _link_port_read_to_num_bank [i] = param._link_port_read_to_num_bank [i];
123	}
124	for (uint32_t i=0; i<_nb_port_write ;i++)
125	{
126	_link_port_write_to_bank_write [i] = param._link_port_write_to_bank_write [i];
127	// _link_port_write_to_num_bank [i] = param._link_port_write_to_num_bank [i];
128	}
129	}
130
131	test();
132	log_printf(FUNC,RegisterFile_Multi_Banked,"Parameters (copy)","End");
133	};
134
135	Parameters::~Parameters ()
136	{
137	log_printf(FUNC,RegisterFile_Multi_Banked,"~Parameters","Begin");
138
139	if (_crossbar == PARTIAL_CROSSBAR)
140	{
141	delete [] _link_port_read_to_bank_read ;
142	// delete [] _link_port_read_to_num_bank ;
143	delete [] _link_port_write_to_bank_write ;
144	// delete [] _link_port_write_to_num_bank ;
145	}
146	log_printf(FUNC,RegisterFile_Multi_Banked,"~Parameters","End");
147	};
148
149	}; // end namespace registerfile_multi_banked
150	}; // end namespace registerfile
151	}; // end namespace generic
152
153	}; // end namespace behavioural
154	}; // end namespace morpheo

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