source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_write.cpp @ 106

Last change on this file since 106 was 106, checked in by rosiere, 15 years ago

1) RAT : Fix bug when update and event in same cycle
2) Context State : Compute depth
3) Load Store Unit : In check logic, translate all access in little endian. More easy to check
4) UFPT : End Event

  • Property svn:keywords set to Id
File size: 2.5 KB
Line 
1#ifdef SYSTEMC
2//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
3/*
4 * $Id: RegisterFile_Multi_Banked_full_crossbar_genMealy_write.cpp 106 2009-02-09 22:55:26Z rosiere $
5 *
6 * [ Description ]
7 *
8 */
9
10#include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h"
11
12namespace morpheo                    {
13namespace behavioural {
14namespace generic {
15namespace registerfile {
16namespace registerfile_multi_banked {
17
18
19#undef  FUNCTION
20#define FUNCTION "RegisterFile_Multi_Banked::full_crossbar_genMealy_write"
21  void RegisterFile_Multi_Banked::full_crossbar_genMealy_write (void)
22  {
23    log_begin(RegisterFile_Multi_Banked,FUNCTION);
24    log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str());
25
26    bool write_port_use [_param->_nb_bank][_param->_nb_port_write_by_bank];
27
28    for (uint32_t i=0; i<_param->_nb_bank; i++)
29      for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++)
30        write_port_use [i][j]=false;
31
32    for (uint32_t i=0; i<_param->_nb_port_write; i++)
33      {
34        bool val = PORT_READ(in_WRITE_VAL    [i]);
35        bool ack = false;
36
37        log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION,"  * write [%d] : %d",i,val);
38
39        if (val == true)
40          {
41            val                = false;
42            // Compute the adress of the bank
43            Taddress_t address;
44            if (_param->_have_port_address == true)
45              address = PORT_READ(in_WRITE_ADDRESS[i]);
46            else
47              address = 0;
48            log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION,"    * address   : %d",address);
49            Taddress_t bank    = address_bank    (address);
50            log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION,"    * bank      : %d",bank   );
51
52            // Search loop
53            for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++)
54              {
55                // find a unbusy port on this bank
56                if (write_port_use[bank][j] == false)
57                  {
58                    // find !!!
59                    write_port_use[bank][j] = true;
60                    val                     = true; 
61                    ack                     = true;
62                   
63                    Taddress_t num_reg = address_num_reg (address);
64
65                    log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION,"    * num_reg   : %d",num_reg);
66                    log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION,"    * bank_port : %d",j      );
67                                   
68                    internal_WRITE_NUM_REG [i] = num_reg;
69                    break;
70                  }
71              }
72
73            internal_WRITE_BANK [i] = bank;
74          }
75
76        internal_WRITE_VAL [i] = val;
77
78        // Write output
79        PORT_WRITE(out_WRITE_ACK [i], ack);
80      }
81
82    log_end(RegisterFile_Multi_Banked,FUNCTION);
83  };
84
85}; // end namespace registerfile_multi_banked
86}; // end namespace registerfile
87}; // end namespace generic
88
89}; // end namespace behavioural
90}; // end namespace morpheo             
91#endif
92//#endif
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