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Makefile.Synthesis @ 113

Last change on this file since 113 was 113, checked in by rosiere, 15 years ago
1) Add modelsim simulation systemC 2) Modelsim cosimulation systemC / VHDL is not finish !!!! (cf execute_queue and write_unit) 3) Add multi architecture 5) Add template for comparator, multiplier and divider 6) Change Message Warning) Various test macro have change, many selftest can't compile
Property svn:keywords set to `Id`
File size: 5.5 KB

Line
1	#
2	# $Id: Makefile.Synthesis 113 2009-04-14 18:39:12Z rosiere $
3	#
4	# [ Description ]
5	#
6	# Makefile
7	#
8
9	#-----[ Variables ]----------------------------------------
10
11	DIR_VHDL = .
12	WORK_NAME = work
13	DIR_WORK = $(MORPHEO_TMP)/$(WORK_NAME)
14
15	FPGA_CFG_FILE_LOCAL = mkf.info
16	FPGA_CFG_FILE_GLOBAL_DIR = $(DIR_MORPHEO)/Behavioural
17	FPGA_CFG_FILE_GLOBAL = configure.mkf
18
19	FPGA_FILES = $(patsubst $(DIR_CFG_GEN)/%.cfg,%,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \
20	$(patsubst $(DIR_CFG_USER)/%.cfg,%,$(wildcard $(DIR_CFG_USER)/*.cfg))
21
22	FPGA_LOG_FILES = $(patsubst $(DIR_CFG_GEN)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \
23	$(patsubst $(DIR_CFG_USER)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_USER)/*.cfg))
24
25
26	#-----[ Rules ]--------------------------------------------
27	.PRECIOUS : $(DIR_LOG)/%.vhdl.log $(DIR_LOG)/%.sim.log
28
29	vhdl : $(EXEC_LOG)
30	@\
31	$(MAKE) vhdl_package; \
32	$(MAKE) vhdl_entity; \
33	$(MAKE) vhdl_testbench
34
35	vhdl_package : $(DIR_WORK)
36	@\
37	declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Pack.vhdl)); \
38	declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \
39	if $(TEST) $${#log_files[]} -ne 0; then $(MAKE) -k $${log_files[]/#$(DIR_VHDL)/$(DIR_LOG)}; fi;
40
41	vhdl_testbench : $(DIR_WORK)
42	@\
43	declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \
44	declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \
45	if $(TEST) $${#log_files[]} -ne 0; then $(MAKE) -k $${log_files[]/#$(DIR_VHDL)/$(DIR_LOG)}; fi;
46
47	vhdl_entity : $(DIR_WORK)
48	@\
49	declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl\|$(GREP_NOT) "(_Pack\.\|_Testbench\.)")); \
50	declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \
51	if $(TEST) $${#log_files[]} -ne 0; then $(MAKE) -k $${log_files[]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; \
52
53	#list :
54	# @\
55	# declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl\|$(GREP_NOT) "(_Pack\.\|_Testbench\.)")); \
56	# for file1 in $${vhdl_files[*]}; do \
57	# declare x=$$(basename $${file1} .vhdl); \
58	# declare -i count_x=$($(ECHO) $${x} \| ${WC} -m); \
59	# for file2 in $${vhdl_files[*]}; do \
60	# if $(TEST) "$${file1}" != "$${file2}"; then\
61	# declare y=$$(basename $${file2} .vhdl); \
62	# declare -i count_y=$($(ECHO) $${y} \| ${WC} -m); \
63	# if $(TEST) $${count_x} -gt $${count_y}; then \
64	# break; \
65	# fi; \
66	# $(ECHO) $${x}; \
67	# fi; \
68	# done; \
69	# done;
70
71	sim : vhdl
72	@\
73	declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \
74	declare -a log_files=($${vhdl_files[*]/%.vhdl/.sim.log}); \
75	if $(TEST) $${#log_files[]} -ne 0; then $(MAKE) -k $${log_files[]/#$(DIR_VHDL)/$(DIR_LOG)}; fi;
76
77	fpga : sim
78	@\
79	$(ECHO) -e "" > $(FPGA_CFG_FILE_LOCAL); \
80	$(ECHO) "files :::::::: $(FPGA_FILES)"; \
81	for file in $(FPGA_FILES); do \
82	declare -a files=($$($(LS) $$file*.vhdl\|$(GREP_NOT) "(_Testbench\.)")); \
83	$(ECHO) -e "# $$file" >> $(FPGA_CFG_FILE_LOCAL); \
84	$(ECHO) -e "target_dep\tall\t$$file.ngc" >> $(FPGA_CFG_FILE_LOCAL); \
85	$(ECHO) -e "target_dep\t$$file.ngc\t$$file.prj" >> $(FPGA_CFG_FILE_LOCAL); \
86	$(ECHO) -e "target_dep\t$$file.prj\t$${files[*]}" >> $(FPGA_CFG_FILE_LOCAL); \
87	$(ECHO) -e "" >> $(FPGA_CFG_FILE_LOCAL); \
88	done; \
89	($(XILINX_ENV); cd $(FPGA_CFG_FILE_GLOBAL_DIR); ./$(FPGA_CFG_FILE_GLOBAL)); \
90	$(MAKE) -k $(FPGA_LOG_FILES);
91
92	$(DIR_LOG)/%.fpga.log :
93	@\
94	$(ECHO) "Synthetis on FPGA : $*"; \
95	$(XILINX_ENV); $(MAKE) -f Makefile.mkf $*.ngc &> $@;
96
97	$(DIR_WORK) :
98	@\
99	$(ECHO) "Create work-space : $@"; \
100	$(MODELTECH_VLIB) $@; \
101	$(MODELTECH_VMAP) $(XILINX_LIBNAME) $(XILINX_LIBDIR); \
102	if $(TEST) $${?} -ne 0; then \
103	$(ECHO) "Xilinx corelib must be compiled to simulation tools"; \
104	$(ECHO) "Run manualy \"$(XILINX_COMPXLIB)\" with $(XILINX_CORELIB) directory"; \
105	fi;
106
107	$(DIR_LOG)/%.sim.log : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log
108	@\
109	$(ECHO) "VHDL's Simulation : $*"; \
110	$(MODELTECH_VSIM) "$(DIR_WORK).`$(BASENAME) $* \|$(UPPERtoLOWER)`" &> $@; \
111	declare -i count=`$(GREP) -ch "Test OK" $@`; \
112	if $(TEST) $$count -ne 0; \
113	then echo " $* ... OK"; \
114	else echo " $* ... KO"; exit 1; \
115	fi;
116
117	$(DIR_LOG)/%.vhdl.log : $(DIR_VHDL)/%.vhdl
118	@\
119	$(ECHO) "VHDL's Compilation : $*"; \
120	$(MODELTECH_VCOM) -work $(DIR_WORK) $< &> $@;
121
122	synthesis_clean :
123	@\
124	if $(TEST) -f Makefile.mkf; then $(MAKE) -f Makefile.mkf clean; fi; \
125	$(RM) $(DIR_WORK) transcript Makefile.mkf wlf modelsim.ini;
126
127	synthesis_clean_all : synthesis_clean
128
129	synthesis_help :
130	@\
131	$(ECHO) " -----[ Synthesis ]----------------------------------";\
132	$(ECHO) "";\
133	$(ECHO) " * vhdl : compile all vhdl's file";\
134	$(ECHO) " * sim : simulate all testbench's file";\
135	$(ECHO) " * fpga : synthetis with fpga's tools";\
136	$(ECHO) "";

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