source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis @ 3

# 
# $Id$
# 
# [ Description ]
# 
# Makefile
# 

#-----[ Variables ]----------------------------------------

DIR_VHDL                        = .
DIR_WORK                        = work

FPGA_CFG_FILE_LOCAL             = mkf.info
FPGA_CFG_FILE_GLOBAL_DIR        = $(DIR_MORPHEO)/Behavioural
FPGA_CFG_FILE_GLOBAL            = configure.mkf 

#-----[ Tools ]--------------------------------------------
VLIB                            = vlib
VCOM                            = vcom
VSIM                            = vsim -c -do "run -all; quit"

ENV_XILINX                      = source $(TOOLS)/xilinx/settings.sh

#-----[ Rules ]--------------------------------------------
.PRECIOUS                       : $(DIR_LOG)/%.vhdl.log $(DIR_LOG)/%.vhdl_sim.log

vhdl                            : execute $(DIR_WORK)
                                @declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Pack.vhdl));                                             \
                                declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log});                                              \
                                $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)};
                                @declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl));                                        \
                                declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log});                                              \
                                $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)};
                                @declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl|$(GREP_NOT) "(_Pack\.|_Testbench\.)"));             \
                                declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log});                                              \
                                $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)};

vhdl_sim                        : vhdl
                                @declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl));                                        \
                                declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl_sim.log});                                          \
                                $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)};

fpga                            : vhdl_sim
                                @$(ECHO) -e "" > $(FPGA_CFG_FILE_LOCAL)
                                @for file in $(patsubst $(DIR_CFG)/%.cfg,%,$(wildcard $(DIR_CFG)/*.cfg)); do                            \
                                        declare -a files=($$($(LS) $$file*.vhdl|$(GREP_NOT) "(_Testbench\.)"));                         \
                                        $(ECHO) -e "# $$file"                             >> $(FPGA_CFG_FILE_LOCAL);                    \
                                        $(ECHO) -e "target_dep\tall\t$$file.ngc"          >> $(FPGA_CFG_FILE_LOCAL);                    \
                                        $(ECHO) -e "target_dep\t$$file.ngc\t$$file.prj"   >> $(FPGA_CFG_FILE_LOCAL);                    \
                                        $(ECHO) -e "target_dep\t$$file.prj\t$${files[*]}" >> $(FPGA_CFG_FILE_LOCAL);                    \
                                        $(ECHO) -e ""                                     >> $(FPGA_CFG_FILE_LOCAL);                    \
                                done
                                @($(ENV_XILINX); $(CD) $(FPGA_CFG_FILE_GLOBAL_DIR); ./$(FPGA_CFG_FILE_GLOBAL))  
                                @$(MAKE) $(patsubst $(DIR_CFG)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG)/*.cfg))

$(DIR_LOG)/%.fpga.log           : 
                                @$(ECHO) "Synthetis on FPGA  : $*"
                                @$(ENV_XILINX); $(MAKE) -f Makefile.mkf $*.ngc > $@

$(DIR_WORK)                     :
                                @$(ECHO) "Create work-space  : $@"
                                @$(VLIB) $@

$(DIR_LOG)/%.vhdl_sim.log       : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log
                                @$(ECHO) "VHDL's Simulation: $*"
                                @$(VSIM) "$(DIR_WORK).`$(BASENAME) $* |$(UPPERtoLOWER)`" > $@
                                declare -i count=`$(GREP) -ch "Test KO" $@`;            \
                                if $(TEST) $$count -eq 0;                               \
                                then echo "                     $* ... OK";             \
                                else echo "                     $* ... KO"; exit 1;     \
                                fi;

$(DIR_LOG)/%.vhdl.log           : $(DIR_VHDL)/%.vhdl
                                @$(ECHO) "VHDL's Compilation : $*"
                                @$(VCOM) $< > $@

synthesis_clean                 :
                                @if $(TEST) -f Makefile.mkf; then $(MAKE) -f Makefile.mkf clean; fi
                                @$(RM) $(DIR_WORK) transcript Makefile.mkf

synthesis_help                  :
                                @$(ECHO) " -----[ Synthesis ]----------------------------------"
                                @$(ECHO) ""
                                @$(ECHO) " * vhdl                 : compile all vhdl's file"
                                @$(ECHO) " * vhdl_sim             : simulate all testbench's file"
                                @$(ECHO) " * fpga                 : synthetis with fpga's tools"
                                @$(ECHO) ""