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Last change
on this file since 67 was
67,
checked in by rosiere, 17 years ago
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Ajout d'un nouveau composant : fifo generic (un port lecture et un port ecriture).
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File size:
1.3 KB
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| 1 | # |
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| 2 | # $Id$ |
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| 3 | # |
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| 4 | # [ Description ] |
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| 5 | # |
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| 6 | |
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| 7 | #-----[ Simulator ]---------------------------------------- |
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| 8 | SIMULATOR = systemcass_deps |
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| 9 | #SIMULATOR = systemc |
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| 10 | |
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| 11 | # 3 simulators : |
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| 12 | # systemc - SystemC |
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| 13 | # systemcass - SystemCASS |
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| 14 | # systemcass_deps - Systemcass, and use port dependency information instead of sensitivity list |
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| 15 | |
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| 16 | #-----[ Flags ]-------------------------------------------- |
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| 17 | MORPHEO_FLAGS = -DSYSTEMC \ |
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| 18 | -DVHDL \ |
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| 19 | -DVHDL_TESTBENCH \ |
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| 20 | -DVHDL_TESTBENCH_ASSERT \ |
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| 21 | -DDEBUG=DEBUG_TRACE |
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| 22 | # |
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| 23 | # -DSTATISTICS \ |
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| 24 | # -DCONFIGURATION \ |
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| 25 | # -DPOSITION \ |
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| 26 | |
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| 27 | # Flags : |
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| 28 | # DEBUG={level} - Print Debug Message |
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| 29 | # SYSTEMC - To generate a systemc's model |
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| 30 | # VHDL - To generate a vhdl's models |
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| 31 | # VHDL_TESTBENCH (need SYSTEMC) - In the simulation, generate two testbench's file (input and ouput) to validate the vhdl's model |
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| 32 | # VHDL_TESTBENCH_ASSERT (need SYSTEMC) - In the simulation, generate in testbench's file an serie of assert |
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| 33 | # STATISTICS (need SYSTEMC) - In the simulation, generate a statistics's file |
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| 34 | # POSITION - To generate a position's files (it's input of viewer) |
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| 35 | # CONFIGURATION - To generate a configuration's file (it's input of viewer and generator) |
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