source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/src/Pattern_History_Table_vhdl_body.cpp @ 2

Last change on this file since 2 was 2, checked in by kane, 17 years ago

Import Morpheo

File size: 2.9 KB
Line 
1#ifdef VHDL
2/*
3 * $Id$
4 *
5 * [ Description ]
6 *
7 */
8
9#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace stage_1_ifetch {
14namespace predictor {
15namespace meta_predictor {
16namespace two_level_branch_predictor {
17namespace pattern_history_table {
18
19
20  void Pattern_History_Table::vhdl_body (Vhdl & vhdl)
21  {
22    log_printf(FUNC,Pattern_History_Table,"vhdl_body","Begin");
23
24    vhdl.set_body ("-- Output : always at '1'");
25    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
26      vhdl.set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';");
27    for (uint32_t i=0; i<_param._nb_prediction     ; i++)
28      vhdl.set_body ("out_PREDICT_ACK_"+toString(i)+"         <= '1';");
29    vhdl.set_body ("");
30
31    list<string> list_port_map;
32
33    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
34      {
35        vhdl.set_body_component_port_map (list_port_map," in_COUNTER_DATA_"+toString(i)+"     ","    in_BRANCH_COMPLETE_HISTORY_"+toString(i));
36        vhdl.set_body_component_port_map (list_port_map," in_COUNTER_ADDSUB_"+toString(i)+"   ","    in_BRANCH_COMPLETE_HIT_"+toString(i)    );
37        vhdl.set_body_component_port_map (list_port_map,"out_COUNTER_DATA_"+toString(i)+"     ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i));
38      }
39    vhdl.set_body_component ("component_Counter",_name+"_Counter",list_port_map);
40
41
42    list_port_map.clear();
43    vhdl.set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK");
44    for (uint32_t i=0; i<_param._nb_prediction; i++)
45      {
46        vhdl.set_body_component_port_map (list_port_map," in_READ_ENABLE_"+toString(i)+"  "," in_PREDICT_VAL_"+toString(i));
47        vhdl.set_body_component_port_map (list_port_map," in_READ_ADDRESS_"+toString(i)+" "," in_PREDICT_ADDRESS_"+toString(i));
48        vhdl.set_body_component_port_map (list_port_map,"out_READ_DATA_"+toString(i)+"    ","out_PREDICT_HISTORY_"+toString(i));   
49      }
50   
51    for (uint32_t i=0; i<_param._nb_branch_complete; i++)
52      {
53        vhdl.set_body_component_port_map (list_port_map," in_WRITE_ENABLE_"+toString(i)+" ","    in_BRANCH_COMPLETE_VAL_"+toString(i)+"");
54        vhdl.set_body_component_port_map (list_port_map," in_WRITE_ADDRESS_"+toString(i)+"","    in_BRANCH_COMPLETE_ADDRESS_"+toString(i));
55        vhdl.set_body_component_port_map (list_port_map," in_WRITE_DATA_"+toString(i)+"   ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i));
56      }
57    vhdl.set_body_component ("component_RegisterFile",_name+"_RegisterFile",list_port_map);
58
59    log_printf(FUNC,Pattern_History_Table,"vhdl_body","End");
60  };
61
62}; // end namespace pattern_history_table
63}; // end namespace two_level_branch_predictor
64}; // end namespace meta_predictor
65}; // end namespace predictor
66}; // end namespace stage_1_ifetch
67
68}; // end namespace behavioural
69}; // end namespace morpheo             
70#endif
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