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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h @ 105

Last change on this file since 105 was 105, checked in by rosiere, 15 years ago
1) Bug fix : Load Miss Speculation (in Commit_unit, Update Prediction Table and Context State) 2) Change address, in rob write address_next. 3) Move Meta_Predictor in save directory
Property svn:keywords set to `Id`
File size: 57.7 KB

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1	#ifndef morpheo_behavioural_Constants_h
2	#define morpheo_behavioural_Constants_h
3
4	/*
5	WARNING :
6
7	I Use reserved exception :
8
9	0x10 - EXCEPTION_MEMORY_MISS_SPECULATION - Load miss speculation
10	0x11 - EXCEPTION_MEMORY_LOAD_SPECULATIVE - The load is speculative : write in register file, but don't commit
11	0x12 - EXCEPTION_ALU_SPR_ACCESS_INVALID - SPR present in ALU but not compatible privilege
12	0x13 - EXCEPTION_ALU_SPR_ACCESS_MUST_READ - SPR not present in ALU
13	0x14 - EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE - SPR not present in ALU
14
15	I Use reserved SPR :
16	[0][21] - SPR_CID : Context Id
17	[0][22] - SPR_TID : Thread Id
18	[0][23] - SPR_TSR : Thread Status Register (Priority)
19	*/
20
21	#include "Common/include/ToString.h"
22
23	namespace morpheo {
24	namespace behavioural {
25
26	# define SET_FLAG( x,pos) {(x) \|= (1<<(pos));} while (0)
27	# define UNSET_FLAG( x,pos) {(x) &= ~(1<<(pos));} while (0)
28	# define IS_SET_FLAG( x,pos) (((x) & (1<<(pos))) != 0)
29	# define IS_UNSET_FLAG(x,pos) (((x) & (1<<(pos))) == 0)
30	# define CHANGE_FLAG( x,pos,f) \
31	{ \
32	if (f) \
33	{SET_FLAG(x,pos);} \
34	else \
35	{UNSET_FLAG(x,pos);} \
36	} while (0)
37
38	//=========================================================[ Type ]=====
39	typedef enum
40	{
41	TYPE_ALU = 0x0, // 00000 - unit multiple
42	TYPE_SHIFT = 0x1, // 00000 - unit multiple
43	TYPE_MOVE = 0x2, // 00000 - unit multiple
44	TYPE_TEST = 0x3, // 00000 - unit multiple
45	TYPE_MUL = 0x4, // 00000 - unit multiple
46	TYPE_DIV = 0x5, // 00000 - unit multiple, type optionnal
47	TYPE_EXTEND = 0x6, // 00000 - unit multiple, type optionnal
48	TYPE_FIND = 0x7, // 00000 - unit multiple, type optionnal
49	TYPE_SPECIAL = 0x8, // 00000 - unit uniq
50	TYPE_CUSTOM = 0x9, // 00000 - unit uniq , type optionnal
51	TYPE_BRANCH = 0xa, // 00000 - unit multiple
52	TYPE_MEMORY = 0xb // 00000 - unit uniq
53	} type_t;
54
55	//#define NB_TYPE 11
56	# define SIZE_TYPE 5
57	# define MAX_TYPE (1<<SIZE_TYPE)
58
59	# define is_type_valid(x) \
60	(( x == TYPE_ALU ) or \
61	( x == TYPE_SHIFT ) or \
62	( x == TYPE_MOVE ) or \
63	( x == TYPE_TEST ) or \
64	( x == TYPE_MUL ) or \
65	( x == TYPE_DIV ) or \
66	( x == TYPE_EXTEND ) or \
67	( x == TYPE_FIND ) or \
68	( x == TYPE_SPECIAL) or \
69	( x == TYPE_CUSTOM ) or \
70	( x == TYPE_BRANCH ) or \
71	( x == TYPE_MEMORY ))
72
73	//====================================================[ Operation ]=====
74
75	//-------------------------------------------------------[ Memory ]-----
76	# define OPERATION_MEMORY_LOAD_8_Z 0x08 // 0_1000
77	# define OPERATION_MEMORY_LOAD_16_Z 0x09 // 0_1001
78	# define OPERATION_MEMORY_LOAD_32_Z 0x0a // 0_1010
79	# define OPERATION_MEMORY_LOAD_64_Z 0x0b // 0_1011
80	# define OPERATION_MEMORY_LOAD_8_S 0x18 // 1_1000
81	# define OPERATION_MEMORY_LOAD_16_S 0x19 // 1_1001
82	# define OPERATION_MEMORY_LOAD_32_S 0x1a // 1_1010
83	# define OPERATION_MEMORY_LOAD_64_S 0x1b // 1_1011
84
85	# define OPERATION_MEMORY_STORE_8 0x0c // 0_1100
86	# define OPERATION_MEMORY_STORE_16 0x0d // 0_1101
87	# define OPERATION_MEMORY_STORE_32 0x0e // 0_1110
88	# define OPERATION_MEMORY_STORE_64 0x0f // 0_1111
89	# define OPERATION_MEMORY_STORE_HEAD_OK 0x1c // 1_1100
90	# define OPERATION_MEMORY_STORE_HEAD_KO 0x1d // 1_1101
91
92	# define OPERATION_MEMORY_LOCK 0x01 // 0_0001
93	# define OPERATION_MEMORY_INVALIDATE 0x02 // 0_0010
94	# define OPERATION_MEMORY_PREFETCH 0x03 // 0_0011
95	# define OPERATION_MEMORY_FLUSH 0x06 // 0_0110
96	# define OPERATION_MEMORY_SYNCHRONIZATION 0x07 // 0_0111
97
98	#define is_operation_memory_load(x) \
99	((x == OPERATION_MEMORY_LOAD_8_Z ) or \
100	(x == OPERATION_MEMORY_LOAD_16_Z) or \
101	(x == OPERATION_MEMORY_LOAD_32_Z) or \
102	(x == OPERATION_MEMORY_LOAD_64_Z) or \
103	(x == OPERATION_MEMORY_LOAD_8_S ) or \
104	(x == OPERATION_MEMORY_LOAD_16_S) or \
105	(x == OPERATION_MEMORY_LOAD_32_S) or \
106	(x == OPERATION_MEMORY_LOAD_64_S) )
107
108	#define is_operation_memory_store(x) \
109	((x == OPERATION_MEMORY_STORE_8 ) or \
110	(x == OPERATION_MEMORY_STORE_16 ) or \
111	(x == OPERATION_MEMORY_STORE_32 ) or \
112	(x == OPERATION_MEMORY_STORE_64 ) or \
113	(x == OPERATION_MEMORY_STORE_HEAD_OK) or \
114	(x == OPERATION_MEMORY_STORE_HEAD_KO))
115
116	#define is_operation_memory_store_head(x) \
117	((x == OPERATION_MEMORY_STORE_HEAD_OK) or \
118	(x == OPERATION_MEMORY_STORE_HEAD_KO))
119
120	#define is_operation_memory_load_signed(x) \
121	((x == OPERATION_MEMORY_LOAD_8_S ) or \
122	(x == OPERATION_MEMORY_LOAD_16_S) or \
123	(x == OPERATION_MEMORY_LOAD_32_S) or \
124	(x == OPERATION_MEMORY_LOAD_64_S) )
125
126	# define MEMORY_ACCESS_8 0x0
127	# define MEMORY_ACCESS_16 0x1
128	# define MEMORY_ACCESS_32 0x2
129	# define MEMORY_ACCESS_64 0x3
130
131	# define MEMORY_SIZE_8 8
132	# define MEMORY_SIZE_16 16
133	# define MEMORY_SIZE_32 32
134	# define MEMORY_SIZE_64 64
135
136	# define MASK_MEMORY_ACCESS_8 0x0
137	# define MASK_MEMORY_ACCESS_16 0x1
138	# define MASK_MEMORY_ACCESS_32 0x3
139	# define MASK_MEMORY_ACCESS_64 0x7
140
141	#define memory_size(x) \
142	(((x==OPERATION_MEMORY_LOAD_16_Z)or \
143	(x==OPERATION_MEMORY_LOAD_16_S)or \
144	(x==OPERATION_MEMORY_STORE_16 ))?MEMORY_SIZE_16: \
145	(((x==OPERATION_MEMORY_LOAD_32_Z)or \
146	(x==OPERATION_MEMORY_LOAD_32_S)or \
147	(x==OPERATION_MEMORY_STORE_32 ))?MEMORY_SIZE_32: \
148	(((x==OPERATION_MEMORY_LOAD_64_Z)or \
149	(x==OPERATION_MEMORY_LOAD_64_S)or \
150	(x==OPERATION_MEMORY_STORE_64 ))?MEMORY_SIZE_64:MEMORY_SIZE_8)))
151
152	#define memory_access(x) \
153	(((x==OPERATION_MEMORY_LOAD_16_Z)or \
154	(x==OPERATION_MEMORY_LOAD_16_S)or \
155	(x==OPERATION_MEMORY_STORE_16 ))?MEMORY_ACCESS_16: \
156	(((x==OPERATION_MEMORY_LOAD_32_Z)or \
157	(x==OPERATION_MEMORY_LOAD_32_S)or \
158	(x==OPERATION_MEMORY_STORE_32 ))?MEMORY_ACCESS_32: \
159	(((x==OPERATION_MEMORY_LOAD_64_Z)or \
160	(x==OPERATION_MEMORY_LOAD_64_S)or \
161	(x==OPERATION_MEMORY_STORE_64 ))?MEMORY_ACCESS_64:MEMORY_ACCESS_8)))
162
163	#define mask_memory_access(x) \
164	(((x==OPERATION_MEMORY_LOAD_16_Z)or \
165	(x==OPERATION_MEMORY_LOAD_16_S)or \
166	(x==OPERATION_MEMORY_STORE_16 ))?MASK_MEMORY_ACCESS_16: \
167	(((x==OPERATION_MEMORY_LOAD_32_Z)or \
168	(x==OPERATION_MEMORY_LOAD_32_S)or \
169	(x==OPERATION_MEMORY_STORE_32 ))?MASK_MEMORY_ACCESS_32: \
170	(((x==OPERATION_MEMORY_LOAD_64_Z)or \
171	(x==OPERATION_MEMORY_LOAD_64_S)or \
172	(x==OPERATION_MEMORY_STORE_64 ))?MASK_MEMORY_ACCESS_64:MASK_MEMORY_ACCESS_8)))
173
174	//---------------------------------------------[ Functionnal Unit ]-----
175	# define OPERATION_ALU_L_ADD 0x1 // 000_0000 l.add , l.addi
176	# define OPERATION_ALU_L_ADDC 0x2 // 000_0000 l.addc , l.addic
177	# define OPERATION_ALU_L_SUB 0x4 // 000_0000 l.sub
178	# define OPERATION_ALU_L_AND 0x8 // 000_0000 l.and , l.andi
179	# define OPERATION_ALU_L_OR 0x10 // 000_0000 l.or , l.ori
180	# define OPERATION_ALU_L_XOR 0x20 // 000_0000 l.xor , l.xori
181
182	# define OPERATION_SHIFT_L_SLL 0x1 // 000_0000 l.sll , l.slli
183	# define OPERATION_SHIFT_L_SRA 0x2 // 000_0000 l.sra , l.srai
184	# define OPERATION_SHIFT_L_SRL 0x4 // 000_0000 l.srl , l.srli
185	# define OPERATION_SHIFT_L_ROR 0x8 // 000_0000 l.ror , l.rori
186
187	# define OPERATION_MOVE_L_MOVHI 0x1 // 000_0000 l.movhi
188	# define OPERATION_MOVE_L_CMOV 0x2 // 000_0000 l.cmov
189
190	# define OPERATION_TEST_L_SFGES 0x41 // 000_0000 l.sfges , l.sfges
191	# define OPERATION_TEST_L_SFGEU 0x1 // 000_0000 l.sfgeu , l.sfgeu
192	# define OPERATION_TEST_L_SFGTS 0x42 // 000_0000 L.sfgts , l.sfgts
193	# define OPERATION_TEST_L_SFGTU 0x2 // 000_0000 l.sfgtu , l.sfgtu
194	# define OPERATION_TEST_L_SFLES 0x44 // 000_0000 l.sfles , l.sfles
195	# define OPERATION_TEST_L_SFLEU 0x4 // 000_0000 l.sfleu , l.sfleu
196	# define OPERATION_TEST_L_SFLTS 0x48 // 000_0000 l.sflts , l.sflts
197	# define OPERATION_TEST_L_SFLTU 0x8 // 000_0000 l.sfltu , l.sfltu
198	# define OPERATION_TEST_L_SFEQ 0x10 // 000_0000 l.sfeq , l.sfeqi
199	# define OPERATION_TEST_L_SFNE 0x20 // 000_0000 l.sfne , l.sfnei
200
201	# define OPERATION_MUL_L_MUL 0x1 // 000_0000 l.mul , l.muli
202	# define OPERATION_MUL_L_MULU 0x2 // 000_0000 l.mulu
203
204	# define OPERATION_DIV_L_DIV 0x1 // 000_0000 l.div
205	# define OPERATION_DIV_L_DIVU 0x2 // 000_0000 l.divu
206
207	# define OPERATION_EXTEND_L_EXTEND_Z 0x1 // 000_0000 l.extbz , l.exthz, l.extwz
208	# define OPERATION_EXTEND_L_EXTEND_S 0x2 // 000_0000 l.extbs , l.exths, l.extws
209
210	# define OPERATION_FIND_L_FF1 0x1 // 000_0000 l.ff1
211	# define OPERATION_FIND_L_FL1 0x2 // 000_0000 l.fl1
212
213	# define OPERATION_SPECIAL_L_NOP 0xff // 000_0000 l.nop
214	# define OPERATION_SPECIAL_L_MFSPR 0x1 // 000_0001 l.mfspr
215	# define OPERATION_SPECIAL_L_MTSPR 0x2 // 000_0010 l.mtspr
216	# define OPERATION_SPECIAL_L_RFE 0x4 // 000_0100 l.rfe
217	# define OPERATION_SPECIAL_L_MAC 0x11 // 001_0001 l.mac , l.maci
218	# define OPERATION_SPECIAL_L_MACRC 0x12 // 001_0010 l.macrc
219	# define OPERATION_SPECIAL_L_MSB 0x14 // 001_0100 l.msb
220	//#define OPERATION_SPECIAL_L_MSYNC 0x21 // 010_0001 l.msync
221	//#define OPERATION_SPECIAL_L_PSYNC 0x22 // 010_0010 l.psync
222	//#define OPERATION_SPECIAL_L_CSYNC 0x24 // 010_0100 l.csync
223	# define OPERATION_SPECIAL_L_SYS 0x41 // 100_0001 l.sys
224	# define OPERATION_SPECIAL_L_TRAP 0x42 // 100_0010 l.trap
225
226
227	# define OPERATION_BRANCH_NONE 0x1 // 000_0000 l.j
228	# define OPERATION_BRANCH_L_TEST_NF 0x2 // 000_0000 l.bnf
229	# define OPERATION_BRANCH_L_TEST_F 0x4 // 000_0000 l.bf
230	# define OPERATION_BRANCH_L_JALR 0x8 // 000_0000 l.jal , l.jalr , l.jr
231
232	//-------------------------------------------------------[ Custom ]-----
233
234	# define OPERATION_CUSTOM_L_1 0x40 // 100_0000
235	# define OPERATION_CUSTOM_L_2 0x41 // 100_0001
236	# define OPERATION_CUSTOM_L_3 0x42 // 100_0010
237	# define OPERATION_CUSTOM_L_4 0x43 // 100_0011
238	# define OPERATION_CUSTOM_L_5 0x44 // 100_0100
239	# define OPERATION_CUSTOM_L_6 0x45 // 100_0101
240	# define OPERATION_CUSTOM_L_7 0x46 // 100_0110
241	# define OPERATION_CUSTOM_L_8 0x47 // 100_0111
242	# define OPERATION_CUSTOM_LF_1_D 0x48 // 100_1000
243	# define OPERATION_CUSTOM_LF_1_S 0x49 // 100_1001
244	# define OPERATION_CUSTOM_LV_1 0x4c // 100_1100
245	# define OPERATION_CUSTOM_LV_2 0x4d // 100_1101
246	# define OPERATION_CUSTOM_LV_3 0x4e // 100_1110
247	# define OPERATION_CUSTOM_LV_4 0x4f // 100_1111
248
249	# define SIZE_OPERATION 7
250	# define MAX_OPERATION (1<<SIZE_OPERATION)
251
252	//====================================================[ Exception ]=====
253	// Exception - OpenRISC
254
255	# define SIZE_EXCEPTION 5
256	# define SIZE_EXCEPTION_USE 4
257	# define SIZE_EXCEPTION_MEMORY 5
258	# define SIZE_EXCEPTION_CUSTOM 5
259	# define SIZE_EXCEPTION_ALU 5
260	# define SIZE_EXCEPTION_DECOD 5
261	# define SIZE_EXCEPTION_IFETCH 5
262
263	# define EXCEPTION_NONE 0x00 // none exception
264	# define EXCEPTION_RESET 0x01 // software or hardware reset
265	# define EXCEPTION_BUS_ERROR 0x02 // Access at a invalid physical adress
266	# define EXCEPTION_DATA_PAGE 0x03 // No matching or page violation protection in pages tables
267	# define EXCEPTION_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables
268	# define EXCEPTION_TICK_TIMER 0x05 // Tick timer interruption
269	# define EXCEPTION_ALIGNMENT 0x06 // Load/Store access is not aligned
270	# define EXCEPTION_ILLEGAL_INSTRUCTION 0x07 // Instruction is illegal (no implemented)
271	# define EXCEPTION_INTERRUPT 0x08 // External interruption
272	# define EXCEPTION_DATA_TLB 0x09 // DTLB miss
273	# define EXCEPTION_INSTRUCTION_TLB 0x0a // ITLB miss
274	# define EXCEPTION_RANGE 0x0b // Overflow or access at a unimplemented register or context
275	# define EXCEPTION_SYSCALL 0x0c // System Call
276	# define EXCEPTION_FLOATING_POINT 0x0d // Caused by a floating instruction
277	# define EXCEPTION_TRAP 0x0e // L.trap or debug unit
278	# define EXCEPTION_RESERVED_0 0x0f // Reserved for a futur usage
279	# define EXCEPTION_RESERVED_1 0x10 // Reserved for a futur usage
280	# define EXCEPTION_RESERVED_2 0x11 // Reserved for a futur usage
281	# define EXCEPTION_RESERVED_3 0x12 // Reserved for a futur usage
282	# define EXCEPTION_RESERVED_4 0x13 // Reserved for a futur usage
283	# define EXCEPTION_RESERVED_5 0x14 // Reserved for a futur usage
284	# define EXCEPTION_RESERVED_6 0x15 // Reserved for implemented specific exceptions
285	# define EXCEPTION_RESERVED_7 0x16 // Reserved for implemented specific exceptions
286	# define EXCEPTION_RESERVED_8 0x17 // Reserved for implemented specific exceptions
287	# define EXCEPTION_RESERVED_9 0x18 // Reserved for implemented specific exceptions
288	# define EXCEPTION_CUSTOM_0 0x19 // Reserved for custom exceptions
289	# define EXCEPTION_CUSTOM_1 0x1a // Reserved for custom exceptions
290	# define EXCEPTION_CUSTOM_2 0x1b // Reserved for custom exceptions
291	# define EXCEPTION_CUSTOM_3 0x1c // Reserved for custom exceptions
292	# define EXCEPTION_CUSTOM_4 0x1d // Reserved for custom exceptions
293	# define EXCEPTION_CUSTOM_5 0x1e // Reserved for custom exceptions
294	# define EXCEPTION_CUSTOM_6 0x1f // Reserved for custom exceptions
295
296	//SR[14].EPH : Exception Prefix High
297	// EPH = 0 Exceptions vectors are located in memory area starting at 0x0
298	// EPH = 1 Exception vectors are located in memory area starting at 0xF0000000
299
300	#define exception_to_address(eph,x) (((eph==0)?0x0:0xF0000000)+(x<<8))
301
302	// Exception Execution
303	# define EXCEPTION_IFETCH_NONE 0x00 // Fetch Unit generate none exception
304	# define EXCEPTION_IFETCH_INSTRUCTION_TLB 0x0a // ITLB miss
305	# define EXCEPTION_IFETCH_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables
306	# define EXCEPTION_IFETCH_BUS_ERROR 0x02 // Access at a invalid physical address
307
308	# define EXCEPTION_DECOD_NONE 0x00 // none exception
309	# define EXCEPTION_DECOD_ILLEGAL_INSTRUCTION 0x01 // Instruction is illegal (no implemented)
310	# define EXCEPTION_DECOD_SYSCALL 0x02 // System Call
311	//#define EXCEPTION_DECOD_TRAP 0x0e // L.trap or debug unit (note : must read SR !)
312	# define EXCEPTION_DECOD_INSTRUCTION_TLB 0x0a // ITLB miss
313	# define EXCEPTION_DECOD_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables
314	# define EXCEPTION_DECOD_BUS_ERROR 0x02 // Access at a invalid physical address
315
316	# define EXCEPTION_ALU_NONE 0x00 // Functionnal unit generate none exception
317	# define EXCEPTION_ALU_RANGE 0x0b //
318	# define EXCEPTION_ALU_SPR_ACCESS_INVALID 0x12 // * SPR present in ALU but not compatible privilege
319	# define EXCEPTION_ALU_SPR_ACCESS_MUST_READ 0x13 // * SPR not present in ALU
320	# define EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE 0x14 // * SPR not present in ALU
321
322	# define EXCEPTION_MEMORY_NONE 0x00 // Load/Store generate none exception
323	# define EXCEPTION_MEMORY_ALIGNMENT 0x06 // Load/Store access is not aligned
324	# define EXCEPTION_MEMORY_DATA_TLB 0x09 // DTLB miss
325	# define EXCEPTION_MEMORY_DATA_PAGE 0x03 // No matching or page violation protection in pages tables
326	# define EXCEPTION_MEMORY_BUS_ERROR 0x02 // Access at a invalid physical address
327	# define EXCEPTION_MEMORY_MISS_SPECULATION 0x10 // * Load miss speculation
328	# define EXCEPTION_MEMORY_LOAD_SPECULATIVE 0x11 // * The load is speculative : write in register file, but don't commit
329
330	# define EXCEPTION_CUSTOM_NONE 0x00 // Custom unit generate none exception
331	# define EXCEPTION_CUSTOM_CUST_0 0x19 // Reserved for custom exceptions
332	# define EXCEPTION_CUSTOM_CUST_1 0x1a // Reserved for custom exceptions
333	# define EXCEPTION_CUSTOM_CUST_2 0x1b // Reserved for custom exceptions
334	# define EXCEPTION_CUSTOM_CUST_3 0x1c // Reserved for custom exceptions
335	# define EXCEPTION_CUSTOM_CUST_4 0x1d // Reserved for custom exceptions
336	# define EXCEPTION_CUSTOM_CUST_5 0x1e // Reserved for custom exceptions
337	# define EXCEPTION_CUSTOM_CUST_6 0x1f // Reserved for custom exceptions
338
339	# define EXCEPTION_USE_NONE 0x00 //
340	# define EXCEPTION_USE_ILLEGAL_INSTRUCTION 0x01 // illegal_instruction
341	# define EXCEPTION_USE_RANGE 0x02 // range
342	# define EXCEPTION_USE_MEMORY_WITH_ALIGNMENT 0x03 // TLB miss, page fault, bus error, alignment
343	# define EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT 0x04 // TLB miss, page fault, bus error
344	# define EXCEPTION_USE_SYSCALL 0x05 // syscall
345	# define EXCEPTION_USE_TRAP 0x06 // trap
346	# define EXCEPTION_USE_CUSTOM_0 0x07 //
347	# define EXCEPTION_USE_CUSTOM_1 0x08 //
348	# define EXCEPTION_USE_CUSTOM_2 0x09 //
349	# define EXCEPTION_USE_CUSTOM_3 0x0a //
350	# define EXCEPTION_USE_CUSTOM_4 0x0b //
351	# define EXCEPTION_USE_CUSTOM_5 0x0c //
352	# define EXCEPTION_USE_CUSTOM_6 0x0d //
353
354	# define exception_ifetch_to_exception_decod(x) x
355	# define exception_decod_to_exception(x) x
356	# define exception_alu_to_exception(x) x
357	# define exception_memory_to_exception(x) x
358	# define exception_custom_to_exception(x) x
359
360	//=======================================================[ icache ]=====
361
362	//--------------------------------------------------[ icache_type ]-----
363
364	# define SIZE_ICACHE_TYPE 2
365
366	# define ICACHE_TYPE_LOAD 0x0 // 0000
367	# define ICACHE_TYPE_LOCK 0x1 // 0001
368	# define ICACHE_TYPE_INVALIDATE 0x2 // 0010
369	# define ICACHE_TYPE_PREFETCH 0x3 // 0011
370
371	// just take the 2 less significative bits.
372	#define operation_to_icache_type(x) (x&0x3)
373
374	//-------------------------------------------------[ icache_error ]-----
375
376	# define SIZE_ICACHE_ERROR 1
377
378	# define ICACHE_ERROR_NONE 0x0
379	# define ICACHE_ERROR_BUS_ERROR 0x1
380
381	//=======================================================[ dcache ]=====
382
383	//--------------------------------------------------[ dcache_type ]-----
384
385	# define SIZE_DCACHE_TYPE 4
386
387	//#define DCACHE_TYPE_ 0x0 // 0000
388	# define DCACHE_TYPE_LOCK 0x1 // 0001
389	# define DCACHE_TYPE_INVALIDATE 0x2 // 0010
390	# define DCACHE_TYPE_PREFETCH 0x3 // 0011
391	//#define DCACHE_TYPE_ 0x4 // 0100
392	//#define DCACHE_TYPE_ 0x5 // 0101
393	# define DCACHE_TYPE_FLUSH 0x6 // 0110
394	# define DCACHE_TYPE_SYNCHRONIZATION 0x7 // 0111
395	# define DCACHE_TYPE_LOAD_8 0x8 // 1000
396	# define DCACHE_TYPE_LOAD_16 0x9 // 1001
397	# define DCACHE_TYPE_LOAD_32 0xa // 1010
398	# define DCACHE_TYPE_LOAD_64 0xb // 1011
399	# define DCACHE_TYPE_STORE_8 0xc // 1100
400	# define DCACHE_TYPE_STORE_16 0xd // 1101
401	# define DCACHE_TYPE_STORE_32 0xe // 1110
402	# define DCACHE_TYPE_STORE_64 0xf // 1111
403
404	// just take the 4 less significative bits.
405	#define operation_to_dcache_type(x) (x&0xf)
406
407	//-------------------------------------------------[ dcache_error ]-----
408
409	# define SIZE_DCACHE_ERROR 1
410
411	# define DCACHE_ERROR_NONE 0x0
412	# define DCACHE_ERROR_BUS_ERROR 0x1
413
414	//=================================================[ special_data ]=====
415
416	# define SIZE_SPECIAL_DATA 2
417
418	// Position of flag in "rename register SR" (NOT IN "SR")
419	# define FLAG_POSITION_F 0x0 // Conditionnal branch flag
420	# define FLAG_POSITION_CY 0x1 // Carry was produced by last arithmetic operation
421	# define FLAG_POSITION_OV 0x0 // Overflow occured during last arithmetic operation
422
423	# define FLAG_F (1<<FLAG_POSITION_F ) // Conditionnal branch flag
424	# define FLAG_CY (1<<FLAG_POSITION_CY) // Carry was produced by last arithmetic operation
425	# define FLAG_OV (1<<FLAG_POSITION_OV) // Overflow occured during last arithmetic operation
426
427	//==========================================================[ spr ]=====
428
429	enum
430	{
431	GROUP_SYSTEM_AND_CONTROL, // 0
432	GROUP_DMMU, // 1
433	GROUP_IMMU, // 2
434	GROUP_DCACHE, // 3
435	GROUP_ICACHE, // 4
436	GROUP_MAC, // 5
437	GROUP_DEBUG, // 6
438	GROUP_PERFORMANCE_COUNTER, // 7
439	GROUP_POWER_MANAGEMENT, // 8
440	GROUP_PIC, // 9
441	GROUP_TICK_TIMER, // 10
442	GROUP_FLOATING_POINT, // 11
443	GROUP_RESERVED_1, // 12
444	GROUP_RESERVED_2, // 13
445	GROUP_RESERVED_3, // 14
446	GROUP_RESERVED_4, // 15
447	GROUP_RESERVED_5, // 16
448	GROUP_RESERVED_6, // 17
449	GROUP_RESERVED_7, // 18
450	GROUP_RESERVED_8, // 19
451	GROUP_RESERVED_9, // 20
452	GROUP_RESERVED_10, // 21
453	GROUP_RESERVED_11, // 22
454	GROUP_RESERVED_12, // 23
455	GROUP_CUSTOM_1, // 24
456	GROUP_CUSTOM_2, // 25
457	GROUP_CUSTOM_3, // 26
458	GROUP_CUSTOM_4, // 27
459	GROUP_CUSTOM_5, // 28
460	GROUP_CUSTOM_6, // 29
461	GROUP_CUSTOM_7, // 30
462	GROUP_CUSTOM_8, // 31
463	NB_GROUP
464	};
465
466	# define NB_REG_GROUP_SYSTEM_AND_CONTROL 1536
467	# define NB_REG_GROUP_DMMU 1536
468	# define NB_REG_GROUP_IMMU 1536
469	# define NB_REG_GROUP_DCACHE 6
470	# define NB_REG_GROUP_ICACHE 4
471	# define NB_REG_GROUP_MAC 3
472	# define NB_REG_GROUP_DEBUG 22
473	# define NB_REG_GROUP_PERFORMANCE_COUNTER 16
474	# define NB_REG_GROUP_POWER_MANAGEMENT 1
475	# define NB_REG_GROUP_PIC 3
476	# define NB_REG_GROUP_TICK_TIMER 2
477	# define NB_REG_GROUP_FLOATING_POINT 0
478	# define NB_REG_GROUP_RESERVED_1 0
479	# define NB_REG_GROUP_RESERVED_2 0
480	# define NB_REG_GROUP_RESERVED_3 0
481	# define NB_REG_GROUP_RESERVED_4 0
482	# define NB_REG_GROUP_RESERVED_5 0
483	# define NB_REG_GROUP_RESERVED_6 0
484	# define NB_REG_GROUP_RESERVED_7 0
485	# define NB_REG_GROUP_RESERVED_8 0
486	# define NB_REG_GROUP_RESERVED_9 0
487	# define NB_REG_GROUP_RESERVED_10 0
488	# define NB_REG_GROUP_RESERVED_11 0
489	# define NB_REG_GROUP_RESERVED_12 0
490	# define NB_REG_GROUP_CUSTOM_1 0
491	# define NB_REG_GROUP_CUSTOM_2 0
492	# define NB_REG_GROUP_CUSTOM_3 0
493	# define NB_REG_GROUP_CUSTOM_4 0
494	# define NB_REG_GROUP_CUSTOM_5 0
495	# define NB_REG_GROUP_CUSTOM_6 0
496	# define NB_REG_GROUP_CUSTOM_7 0
497	# define NB_REG_GROUP_CUSTOM_8 0
498
499	static const uint32_t NB_REG_GROUP [] =
500	{NB_REG_GROUP_SYSTEM_AND_CONTROL ,
501	NB_REG_GROUP_DMMU ,
502	NB_REG_GROUP_IMMU ,
503	NB_REG_GROUP_DCACHE ,
504	NB_REG_GROUP_ICACHE ,
505	NB_REG_GROUP_MAC ,
506	NB_REG_GROUP_DEBUG ,
507	NB_REG_GROUP_PERFORMANCE_COUNTER ,
508	NB_REG_GROUP_POWER_MANAGEMENT ,
509	NB_REG_GROUP_PIC ,
510	NB_REG_GROUP_TICK_TIMER ,
511	NB_REG_GROUP_FLOATING_POINT ,
512	NB_REG_GROUP_RESERVED_1 ,
513	NB_REG_GROUP_RESERVED_2 ,
514	NB_REG_GROUP_RESERVED_3 ,
515	NB_REG_GROUP_RESERVED_4 ,
516	NB_REG_GROUP_RESERVED_5 ,
517	NB_REG_GROUP_RESERVED_6 ,
518	NB_REG_GROUP_RESERVED_7 ,
519	NB_REG_GROUP_RESERVED_8 ,
520	NB_REG_GROUP_RESERVED_9 ,
521	NB_REG_GROUP_RESERVED_10 ,
522	NB_REG_GROUP_RESERVED_11 ,
523	NB_REG_GROUP_RESERVED_12 ,
524	NB_REG_GROUP_CUSTOM_1 ,
525	NB_REG_GROUP_CUSTOM_2 ,
526	NB_REG_GROUP_CUSTOM_3 ,
527	NB_REG_GROUP_CUSTOM_4 ,
528	NB_REG_GROUP_CUSTOM_5 ,
529	NB_REG_GROUP_CUSTOM_6 ,
530	NB_REG_GROUP_CUSTOM_7 ,
531	NB_REG_GROUP_CUSTOM_8 };
532
533	// GROUP_SYSTEM_AND_CONTROL
534	# define SPR_VR 0 // Version register
535	# define SPR_UPR 1 // Unit Present register
536	# define SPR_CPUCFGR 2 // CPU Configuration register
537	# define SPR_DMMUCFGR 3 // Data MMU Configuration register
538	# define SPR_IMMUCFGR 4 // Instruction MMU Configuration register
539	# define SPR_DCCFGR 5 // Data Cache Configuration register
540	# define SPR_ICCFGR 6 // Instruction Cache Configuration register
541	# define SPR_DCFGR 7 // Debug Configuration register
542	# define SPR_PCCFGR 8 // Performance Counters Configuration register
543	# define SPR_NPC 16 // PC mapped to SPR space (next PC)
544	# define SPR_SR 17 // Supervision register
545	# define SPR_PPC 18 // PC mapped to SPR space (previous PC)
546	# define SPR_FPCSR 20 // FP Control Status register
547	# define SPR_CID 21 // Context Id
548	# define SPR_TID 22 // Thread Id
549	# define SPR_TSR 23 // Thread Priority
550	# define SPR_EPCR 32 // Exception PC register
551	# define SPR_EEAR 48 // Exception EA register
552	# define SPR_ESR 64 // Exception SR register
553	# define SPR_GPR 1024 // GPRs mappted to SPR space
554
555	// GROUP_DCACHE
556	# define SPR_DCCR 0 // DC Control register
557	# define SPR_DCBPR 1 // DC Block Prefetch register
558	# define SPR_DCBFR 2 // DC Block Flush register
559	# define SPR_DCBIR 3 // DC Block Invalidate register
560	# define SPR_DCBWR 4 // DC Block Write-back register
561	# define SPR_DCBLR 5 // DC Block Lock register
562
563	// GROUP_ICACHE
564	# define SPR_ICCR 0 // IC Control register
565	# define SPR_ICBPR 1 // IC Block Prefetch register
566	# define SPR_ICBIR 2 // IC Block Invalidate register
567	# define SPR_ICBLR 3 // IC Block Lock register
568
569	// GROUP_MAC
570	# define SPR_MACLO 1 // MAC Low
571	# define SPR_MACHI 2 // MAC High
572
573	// SR RENAME
574	# define NB_SPR_LOGIC 2
575	# define LOG2_NB_SPR_LOGIC 1
576	// SPR_LOGIC[0] = F
577	// SPR_LOGIC[1] = Carry, Overflow
578	# define SPR_LOGIC_SR_F 0x0 // Status register bit F (size = 1)
579	# define SPR_LOGIC_SR_CY_OV 0x1 // Status register bit overflow and carry (size = 2)
580
581	//----------------------------------------------[ spr_mode_access ]-----
582
583	# define SPR_ACCESS_MODE_NONE 0x0 // 000
584	# define SPR_ACCESS_MODE_READ_ONLY 0x1 // 001
585	# define SPR_ACCESS_MODE_WRITE_ONLY 0x2 // 010
586	# define SPR_ACCESS_MODE_READ_WRITE 0x3 // 011
587	# define SPR_ACCESS_MODE_READ_ONLY_COND 0x5 // 101 special read
588
589	//--------------------------------------------------------[ event ]-----
590	# define SIZE_EVENT_STATE 2
591
592	# define EVENT_STATE_NO_EVENT 0 // no event : current case
593	# define EVENT_STATE_EVENT 1 // Have a event : make necessary to manage the event
594	# define EVENT_STATE_WAITEND 2 // Wait end of manage event (restaure a good context)
595	# define EVENT_STATE_END 3 // CPU can continue
596
597	# define SIZE_EVENT_TYPE 3
598
599	# define EVENT_TYPE_NONE 0 // no event
600	# define EVENT_TYPE_BRANCH_MISS_SPECULATION 1 // miss of speculation (load or branch miss speculation)
601	# define EVENT_TYPE_LOAD_MISS_SPECULATION 2 // miss of speculation (load or branch miss speculation)
602	# define EVENT_TYPE_EXCEPTION 3 // exception or interruption occure
603	//#define EVENT_TYPE_BRANCH_NO_ACCURATE 3 // branch is no accurate (old speculation is a miss)
604	# define EVENT_TYPE_SPR_ACCESS 4 // decod a mtspr or mfspr instruction
605	# define EVENT_TYPE_MSYNC 5 // decod a memory synchronization
606	# define EVENT_TYPE_PSYNC 6 // decod a pipeline synchronization
607	# define EVENT_TYPE_CSYNC 7 // decod a context synchronization
608
609	//-------------------------------------------------[ branch_state ]-----
610	# define SIZE_BRANCH_STATE 2
611
612	# define BRANCH_STATE_NONE 0x0 // 0 0
613	# define BRANCH_STATE_NSPEC_TAKE 0x1 // 0 1 -> incondionnal
614	# define BRANCH_STATE_SPEC_NTAKE 0x2 // 1 0
615	# define BRANCH_STATE_SPEC_TAKE 0x3 // 1 1
616
617	//---------------------------------------------[ branch_condition ]-----
618
619	# define SIZE_BRANCH_CONDITION 4
620	# define MAX_BRANCH_CONDITION (1<<SIZE_BRANCH_CONDITION)
621	typedef enum
622	{
623	BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK = 0x0, // None condition (jump)
624	BRANCH_CONDITION_NONE_WITH_WRITE_STACK = 0x8, // None condition (jump)
625	BRANCH_CONDITION_FLAG_UNSET = 0x2, // Branch if Flag is clear
626	BRANCH_CONDITION_FLAG_SET = 0x3, // Branch if Flag is set
627	BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK = 0x4, // Branch if a register is read
628	BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK = 0xc, // Branch if a register is read
629	BRANCH_CONDITION_READ_STACK = 0xf // Branch with pop in stack pointer
630	} branch_condition_t;
631
632	# define is_branch_condition_valid(x) \
633	(( x == BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK ) or \
634	( x == BRANCH_CONDITION_NONE_WITH_WRITE_STACK ) or \
635	( x == BRANCH_CONDITION_FLAG_UNSET ) or \
636	( x == BRANCH_CONDITION_FLAG_SET ) or \
637	( x == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or \
638	( x == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or \
639	( x == BRANCH_CONDITION_READ_STACK ))
640
641
642	/*
643	enum
644	{
645	BRANCH_TYPE_SEQUENTIAL,
646	BRANCH_TYPE_JUMP,
647	BRANCH_TYPE_CONDITIONNAL,
648	BRANCH_TYPE_REGISTER,
649	BRANCH_TYPE_CALL,
650	BRANCH_TYPE_RETURN,
651	NB_BRANCH_TYPE
652	};
653
654	# define branch_condition_to_type(x) \
655	(x == BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK )?BRANCH_TYPE_JUMP: \
656	((x == BRANCH_CONDITION_NONE_WITH_WRITE_STACK )?BRANCH_TYPE_CALL: \
657	((x == BRANCH_CONDITION_FLAG_UNSET )?BRANCH_TYPE_CONDITIONNAL: \
658	((x == BRANCH_CONDITION_FLAG_SET )?BRANCH_TYPE_CONDITIONNAL: \
659	((x == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK)?BRANCH_TYPE_REGISTER: \
660	((x == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK )?BRANCH_TYPE_CALL: \
661	((x == BRANCH_CONDITION_READ_STACK )?BRANCH_TYPE_RETURN:BRANCH_TYPE_SEQUENTIAL))))));
662	*/
663
664	//--------------------------------------------------[ instruction ]-----
665	# define NB_INSTRUCTION 213 // 92 ORBIS, 30 ORFPX (15 simple, 15 double), 91 ORVDX (38 on byte, 41 on half, 12 independant format)
666
667	enum
668	{
669	// ORBIS
670	INSTRUCTION_L_ADD,
671	INSTRUCTION_L_ADDC,
672	INSTRUCTION_L_ADDI,
673	INSTRUCTION_L_ADDIC,
674	INSTRUCTION_L_AND,
675	INSTRUCTION_L_ANDI,
676	INSTRUCTION_L_BF,
677	INSTRUCTION_L_BNF,
678	INSTRUCTION_L_CMOV,
679	INSTRUCTION_L_CSYNC,
680	INSTRUCTION_L_CUST1,
681	INSTRUCTION_L_CUST2,
682	INSTRUCTION_L_CUST3,
683	INSTRUCTION_L_CUST4,
684	INSTRUCTION_L_CUST5,
685	INSTRUCTION_L_CUST6,
686	INSTRUCTION_L_CUST7,
687	INSTRUCTION_L_CUST8,
688	INSTRUCTION_L_DIV,
689	INSTRUCTION_L_DIVU,
690	INSTRUCTION_L_EXTBS,
691	INSTRUCTION_L_EXTBZ,
692	INSTRUCTION_L_EXTHS,
693	INSTRUCTION_L_EXTHZ,
694	INSTRUCTION_L_EXTWS,
695	INSTRUCTION_L_EXTWZ,
696	INSTRUCTION_L_FF1,
697	INSTRUCTION_L_FL1,
698	INSTRUCTION_L_J,
699	INSTRUCTION_L_JAL,
700	INSTRUCTION_L_JALR,
701	INSTRUCTION_L_JR,
702	INSTRUCTION_L_LBS,
703	INSTRUCTION_L_LBZ,
704	INSTRUCTION_L_LD,
705	INSTRUCTION_L_LHS,
706	INSTRUCTION_L_LHZ,
707	INSTRUCTION_L_LWS,
708	INSTRUCTION_L_LWZ,
709	INSTRUCTION_L_MAC,
710	INSTRUCTION_L_MACI,
711	INSTRUCTION_L_MACRC,
712	INSTRUCTION_L_MFSPR,
713	INSTRUCTION_L_MOVHI,
714	INSTRUCTION_L_MSB,
715	INSTRUCTION_L_MSYNC,
716	INSTRUCTION_L_MTSPR,
717	INSTRUCTION_L_MUL,
718	INSTRUCTION_L_MULI,
719	INSTRUCTION_L_MULU,
720	INSTRUCTION_L_NOP,
721	INSTRUCTION_L_OR,
722	INSTRUCTION_L_ORI,
723	INSTRUCTION_L_PSYNC,
724	INSTRUCTION_L_RFE,
725	INSTRUCTION_L_ROR,
726	INSTRUCTION_L_RORI,
727	INSTRUCTION_L_SB,
728	INSTRUCTION_L_SD,
729	INSTRUCTION_L_SFEQ,
730	INSTRUCTION_L_SFEQI,
731	INSTRUCTION_L_SFGES,
732	INSTRUCTION_L_SFGESI,
733	INSTRUCTION_L_SFGEU,
734	INSTRUCTION_L_SFGEUI,
735	INSTRUCTION_L_SFGTS,
736	INSTRUCTION_L_SFGTSI,
737	INSTRUCTION_L_SFGTU,
738	INSTRUCTION_L_SFGTUI,
739	INSTRUCTION_L_SFLES,
740	INSTRUCTION_L_SFLESI,
741	INSTRUCTION_L_SFLEU,
742	INSTRUCTION_L_SFLEUI,
743	INSTRUCTION_L_SFLTS,
744	INSTRUCTION_L_SFLTSI,
745	INSTRUCTION_L_SFLTU,
746	INSTRUCTION_L_SFLTUI,
747	INSTRUCTION_L_SFNE,
748	INSTRUCTION_L_SFNEI,
749	INSTRUCTION_L_SH,
750	INSTRUCTION_L_SLL,
751	INSTRUCTION_L_SLLI,
752	INSTRUCTION_L_SRA,
753	INSTRUCTION_L_SRAI,
754	INSTRUCTION_L_SRL,
755	INSTRUCTION_L_SRLI,
756	INSTRUCTION_L_SUB,
757	INSTRUCTION_L_SW,
758	INSTRUCTION_L_SYS,
759	INSTRUCTION_L_TRAP,
760	INSTRUCTION_L_XOR,
761	INSTRUCTION_L_XORI,
762	// ORFPX
763	INSTRUCTION_LF_ADD_D,
764	INSTRUCTION_LF_ADD_S,
765	INSTRUCTION_LF_CUST1_D,
766	INSTRUCTION_LF_CUST1_S,
767	INSTRUCTION_LF_DIV_D,
768	INSTRUCTION_LF_DIV_S,
769	INSTRUCTION_LF_FTOI_D,
770	INSTRUCTION_LF_FTOI_S,
771	INSTRUCTION_LF_ITOF_D,
772	INSTRUCTION_LF_ITOF_S,
773	INSTRUCTION_LF_MADD_D,
774	INSTRUCTION_LF_MADD_S,
775	INSTRUCTION_LF_MUL_D,
776	INSTRUCTION_LF_MUL_S,
777	INSTRUCTION_LF_REM_D,
778	INSTRUCTION_LF_REM_S,
779	INSTRUCTION_LF_SFEQ_D,
780	INSTRUCTION_LF_SFEQ_S,
781	INSTRUCTION_LF_SFGE_D,
782	INSTRUCTION_LF_SFGE_S,
783	INSTRUCTION_LF_SFGT_D,
784	INSTRUCTION_LF_SFGT_S,
785	INSTRUCTION_LF_SFLE_D,
786	INSTRUCTION_LF_SFLE_S,
787	INSTRUCTION_LF_SFLT_D,
788	INSTRUCTION_LF_SFLT_S,
789	INSTRUCTION_LF_SFNE_D,
790	INSTRUCTION_LF_SFNE_S,
791	INSTRUCTION_LF_SUB_D,
792	INSTRUCTION_LF_SUB_S,
793	// ORVDX
794	INSTRUCTION_LV_ADD_B,
795	INSTRUCTION_LV_ADD_H,
796	INSTRUCTION_LV_ADDS_B,
797	INSTRUCTION_LV_ADDS_H,
798	INSTRUCTION_LV_ADDU_B,
799	INSTRUCTION_LV_ADDU_H,
800	INSTRUCTION_LV_ADDUS_B,
801	INSTRUCTION_LV_ADDUS_H,
802	INSTRUCTION_LV_ALL_EQ_B,
803	INSTRUCTION_LV_ALL_EQ_H,
804	INSTRUCTION_LV_ALL_GE_B,
805	INSTRUCTION_LV_ALL_GE_H,
806	INSTRUCTION_LV_ALL_GT_B,
807	INSTRUCTION_LV_ALL_GT_H,
808	INSTRUCTION_LV_ALL_LE_B,
809	INSTRUCTION_LV_ALL_LE_H,
810	INSTRUCTION_LV_ALL_LT_B,
811	INSTRUCTION_LV_ALL_LT_H,
812	INSTRUCTION_LV_ALL_NE_B,
813	INSTRUCTION_LV_ALL_NE_H,
814	INSTRUCTION_LV_AND,
815	INSTRUCTION_LV_ANY_EQ_B,
816	INSTRUCTION_LV_ANY_EQ_H,
817	INSTRUCTION_LV_ANY_GE_B,
818	INSTRUCTION_LV_ANY_GE_H,
819	INSTRUCTION_LV_ANY_GT_B,
820	INSTRUCTION_LV_ANY_GT_H,
821	INSTRUCTION_LV_ANY_LE_B,
822	INSTRUCTION_LV_ANY_LE_H,
823	INSTRUCTION_LV_ANY_LT_B,
824	INSTRUCTION_LV_ANY_LT_H,
825	INSTRUCTION_LV_ANY_NE_B,
826	INSTRUCTION_LV_ANY_NE_H,
827	INSTRUCTION_LV_AVG_B,
828	INSTRUCTION_LV_AVG_H,
829	INSTRUCTION_LV_CMP_EQ_B,
830	INSTRUCTION_LV_CMP_EQ_H,
831	INSTRUCTION_LV_CMP_GE_B,
832	INSTRUCTION_LV_CMP_GE_H,
833	INSTRUCTION_LV_CMP_GT_B,
834	INSTRUCTION_LV_CMP_GT_H,
835	INSTRUCTION_LV_CMP_LE_B,
836	INSTRUCTION_LV_CMP_LE_H,
837	INSTRUCTION_LV_CMP_LT_B,
838	INSTRUCTION_LV_CMP_LT_H,
839	INSTRUCTION_LV_CMP_NE_B,
840	INSTRUCTION_LV_CMP_NE_H,
841	INSTRUCTION_LV_CUST1,
842	INSTRUCTION_LV_CUST2,
843	INSTRUCTION_LV_CUST3,
844	INSTRUCTION_LV_CUST4,
845	INSTRUCTION_LV_MADDS_H,
846	INSTRUCTION_LV_MAX_B,
847	INSTRUCTION_LV_MAX_H,
848	INSTRUCTION_LV_MERGE_B,
849	INSTRUCTION_LV_MERGE_H,
850	INSTRUCTION_LV_MIN_B,
851	INSTRUCTION_LV_MIN_H,
852	INSTRUCTION_LV_MSUBS_H,
853	INSTRUCTION_LV_MULS_H,
854	INSTRUCTION_LV_NAND,
855	INSTRUCTION_LV_NOR,
856	INSTRUCTION_LV_OR,
857	INSTRUCTION_LV_PACK_B,
858	INSTRUCTION_LV_PACK_H,
859	INSTRUCTION_LV_PACKS_B,
860	INSTRUCTION_LV_PACKS_H,
861	INSTRUCTION_LV_PACKUS_B,
862	INSTRUCTION_LV_PACKUS_H,
863	INSTRUCTION_LV_PERM_N,
864	INSTRUCTION_LV_RL_B,
865	INSTRUCTION_LV_RL_H,
866	INSTRUCTION_LV_SLL,
867	INSTRUCTION_LV_SLL_B,
868	INSTRUCTION_LV_SLL_H,
869	INSTRUCTION_LV_SRA_B,
870	INSTRUCTION_LV_SRA_H,
871	INSTRUCTION_LV_SRL,
872	INSTRUCTION_LV_SRL_B,
873	INSTRUCTION_LV_SRL_H,
874	INSTRUCTION_LV_SUB_B,
875	INSTRUCTION_LV_SUB_H,
876	INSTRUCTION_LV_SUBS_B,
877	INSTRUCTION_LV_SUBS_H,
878	INSTRUCTION_LV_SUBU_B,
879	INSTRUCTION_LV_SUBU_H,
880	INSTRUCTION_LV_SUBUS_B,
881	INSTRUCTION_LV_SUBUS_H,
882	INSTRUCTION_LV_UNPACK_B,
883	INSTRUCTION_LV_UNPACK_H,
884	INSTRUCTION_LV_XOR
885	};
886
887	//-----------------------------------------------[ Code Operation ]-----
888
889	# define MAX_OPCOD_0 64 // Instructions with immediat
890	# define MAX_OPCOD_1 64 // Instruction ORFPX32/64
891	# define MAX_OPCOD_2 256 // Instruction ORVDX64
892	# define MAX_OPCOD_3 256 // Instructions Register-Register
893	# define MAX_OPCOD_4 32 // Instructions "set flag" with register
894	# define MAX_OPCOD_5 32 // Instructions "set flag" with immediat
895	# define MAX_OPCOD_6 4 // Instruction Shift/Rotate with immediat
896	# define MAX_OPCOD_7 16 // Instructions multiply with HI-LO
897	# define MAX_OPCOD_8 2 // Instructions acces at HI-LO
898	# define MAX_OPCOD_9 8 // Instructions special
899	# define MAX_OPCOD_10 4 // Instructions no operation
900	# define MAX_OPCOD_11 4 // Instruction Shift/Rotate with register
901	# define MAX_OPCOD_12 4 // Instructions extend
902	# define MAX_OPCOD_13 4 // Instructions extend (64b)
903
904	// OPCOD_0 - [31:26] Instructions with immediat
905	# define OPCOD_L_J 0x00 // 000_000
906	# define OPCOD_L_JAL 0x01 // 000_001
907	# define OPCOD_L_BNF 0x03 // 000_011
908	# define OPCOD_L_BF 0x04 // 000_100
909	# define OPCOD_L_RFE 0x09 // 001_001
910	# define OPCOD_L_JR 0x11 // 010_001
911	# define OPCOD_L_JALR 0x12 // 010_010
912	# define OPCOD_L_MACI 0x13 // 010_011
913	# define OPCOD_L_CUST1 0x1c // 011_100
914	# define OPCOD_L_CUST2 0x1d // 011_101
915	# define OPCOD_L_CUST3 0x1e // 011_110
916	# define OPCOD_L_CUST4 0x1f // 011_111
917	# define OPCOD_L_CUST5 0x3c // 111_100
918	# define OPCOD_L_CUST6 0x3d // 111_101
919	# define OPCOD_L_CUST7 0x3e // 111_110
920	# define OPCOD_L_CUST8 0x3f // 111_111
921	# define OPCOD_L_LD 0x20 // 100_000
922	# define OPCOD_L_LWZ 0x21 // 100_001
923	# define OPCOD_L_LWS 0x22 // 100_010
924	# define OPCOD_L_LBZ 0x23 // 100_011
925	# define OPCOD_L_LBS 0x24 // 100_100
926	# define OPCOD_L_LHZ 0x25 // 100_101
927	# define OPCOD_L_LHS 0x26 // 100_110
928	# define OPCOD_L_ADDI 0x27 // 100_111
929	# define OPCOD_L_ADDIC 0x28 // 101_000
930	# define OPCOD_L_ANDI 0x29 // 101_001
931	# define OPCOD_L_ORI 0x2a // 101_010
932	# define OPCOD_L_XORI 0x2b // 101_011
933	# define OPCOD_L_MULI 0x2c // 101_100
934	# define OPCOD_L_MFSPR 0x2d // 101_101
935	# define OPCOD_L_MTSPR 0x30 // 110_000
936	# define OPCOD_L_SD 0x34 // 110_100
937	# define OPCOD_L_SW 0x35 // 110_101
938	# define OPCOD_L_SB 0x36 // 110_110
939	# define OPCOD_L_SH 0x37 // 110_111
940
941	# define OPCOD_1 0x33 // 110_011 // Instruction ORFPX32/64
942	# define OPCOD_2 0x0a // 001_010 // Instruction ORVDX64
943	# define OPCOD_3 0x38 // 111_000 // Instructions Register-Register
944	# define OPCOD_4 0x39 // 111_001 // Instructions "set flag" with register
945	# define OPCOD_5 0x2f // 101_111 // Instructions "set flag" with immediat
946	# define OPCOD_6 0x2e // 101_110 // Instruction Shift/Rotate with immediat
947	# define OPCOD_7 0x31 // 110_001 // Instructions multiply with HI-LO
948	# define OPCOD_8 0x06 // 000_110 // Instructions acces at HI-LO
949	# define OPCOD_9 0x08 // 001_000 // Instructions special
950	# define OPCOD_10 0x05 // 000_101 // Instructions no operation
951
952	// OPCOD_3 instructions - [9:8] [3:0] Instructions Register-Register
953	# define OPCOD_L_ADD 0x00 // 00_0000
954	# define OPCOD_L_ADDC 0x01 // 00_0001
955	# define OPCOD_L_SUB 0x02 // 00_0010
956	# define OPCOD_L_AND 0x03 // 00_0011
957	# define OPCOD_L_OR 0x04 // 00_0100
958	# define OPCOD_L_XOR 0x05 // 00_0101
959	# define OPCOD_L_CMOV 0x0e // 00_1110
960	# define OPCOD_L_FF1 0x0f // 00_1111
961	# define OPCOD_L_FL1 0x1f // 01_1111
962	# define OPCOD_L_MUL 0x36 // 11_0110
963	# define OPCOD_L_DIV 0x39 // 11_1001
964	# define OPCOD_L_DIVU 0x3a // 11_1010
965	# define OPCOD_L_MULU 0x3b // 11_1011
966
967	# define OPCOD_11 0x8 // 1000 // Instruction Shift/Rotate with register
968	# define OPCOD_12 0xc // 1100 // Instructions extend
969	# define OPCOD_13 0xd // 1101 // Instructions extend (64b)
970
971	// OPCOD_4 instructions - [25:21] Instructions "set flag" with register
972	# define OPCOD_L_SFEQ 0x00 // 00000
973	# define OPCOD_L_SFNE 0x01 // 00001
974	# define OPCOD_L_SFGTU 0x02 // 00010
975	# define OPCOD_L_SFGEU 0x03 // 00011
976	# define OPCOD_L_SFLTU 0x04 // 00100
977	# define OPCOD_L_SFLEU 0x05 // 00101
978	# define OPCOD_L_SFGTS 0x0a // 01010
979	# define OPCOD_L_SFGES 0x0b // 01011
980	# define OPCOD_L_SFLTS 0x0c // 01100
981	# define OPCOD_L_SFLES 0x0d // 01101
982
983	// OPCOD_5 instructions - [25:21] Instructions "set flag" with immediat
984	# define OPCOD_L_SFEQI 0x00 // 00000
985	# define OPCOD_L_SFNEI 0x01 // 00001
986	# define OPCOD_L_SFGTUI 0x02 // 00010
987	# define OPCOD_L_SFGEUI 0x03 // 00011
988	# define OPCOD_L_SFLTUI 0x04 // 00100
989	# define OPCOD_L_SFLEUI 0x05 // 00101
990	# define OPCOD_L_SFGTSI 0x0a // 01010
991	# define OPCOD_L_SFGESI 0x0b // 01011
992	# define OPCOD_L_SFLTSI 0x0c // 01100
993	# define OPCOD_L_SFLESI 0x0d // 01101
994
995	// OPCOD_6 instructions - [7:6] Instruction Shift/Rotate with immediat
996	# define OPCOD_L_SLLI 0x0 // 00
997	# define OPCOD_L_SRLI 0x1 // 01
998	# define OPCOD_L_SRAI 0x2 // 10
999	# define OPCOD_L_RORI 0x3 // 11
1000
1001	// OPCOD_7 instructions - [3:0] Instructions multiply with HI-LO
1002	# define OPCOD_L_MAC 0x1 // 0001
1003	# define OPCOD_L_MSB 0x2 // 0010
1004
1005	// OPCOD_8 instructions - [17] Instructions acces at HI-LO
1006	# define OPCOD_L_MOVHI 0x0 // 0
1007	# define OPCOD_L_MACRC 0x1 // 1
1008
1009	// OPCOD_9 instructions - [25:23] Instruction special
1010	# define OPCOD_L_SYS 0x0 // 000
1011	# define OPCOD_L_TRAP 0x2 // 010
1012	# define OPCOD_L_MSYNC 0x4 // 100
1013	# define OPCOD_L_PSYNC 0x5 // 101
1014	# define OPCOD_L_CSYNC 0x6 // 110
1015
1016	// OPCOD_10 instructions - [25:24] Instruction no operation
1017	# define OPCOD_L_NOP 0x1 // 01
1018
1019	// OPCOD_11 instructions - [7:6] Instruction Shift/Rotate with register
1020	# define OPCOD_L_SLL 0x0 // 00
1021	# define OPCOD_L_SRL 0x1 // 01
1022	# define OPCOD_L_SRA 0x2 // 10
1023	# define OPCOD_L_ROR 0x3 // 11
1024
1025	// OPCOD_12 instructions - [9:6] Instructions extend
1026	# define OPCOD_L_EXTHS 0x0 // 0000
1027	# define OPCOD_L_EXTHZ 0x2 // 0010
1028	# define OPCOD_L_EXTBS 0x1 // 0001
1029	# define OPCOD_L_EXTBZ 0x3 // 0011
1030
1031	// OPCOD_13 instructions - [9:6] Instructions extend (64b)
1032	# define OPCOD_L_EXTWS 0x0 // 0000
1033	# define OPCOD_L_EXTWZ 0x1 // 0001
1034
1035	}; // end namespace behavioural
1036
1037	template<> inline std::string toString<morpheo::behavioural::type_t>(const morpheo::behavioural::type_t& x)
1038	{
1039	switch (x)
1040	{
1041	case morpheo::behavioural::TYPE_ALU : return "ALU" ;
1042	case morpheo::behavioural::TYPE_SHIFT : return "SHIFT" ;
1043	case morpheo::behavioural::TYPE_MOVE : return "MOVE" ;
1044	case morpheo::behavioural::TYPE_TEST : return "TEST" ;
1045	case morpheo::behavioural::TYPE_MUL : return "MUL" ;
1046	case morpheo::behavioural::TYPE_DIV : return "DIV" ;
1047	case morpheo::behavioural::TYPE_EXTEND : return "EXTEND" ;
1048	case morpheo::behavioural::TYPE_FIND : return "FIND" ;
1049	case morpheo::behavioural::TYPE_SPECIAL : return "SPECIAL" ;
1050	case morpheo::behavioural::TYPE_CUSTOM : return "CUSTOM" ;
1051	case morpheo::behavioural::TYPE_BRANCH : return "BRANCH" ;
1052	case morpheo::behavioural::TYPE_MEMORY : return "MEMORY" ;
1053	default : return "";
1054	}
1055	};
1056
1057	template<> inline std::string toString<morpheo::behavioural::branch_condition_t>(const morpheo::behavioural::branch_condition_t& x)
1058	{
1059	switch (x)
1060	{
1061	case morpheo::behavioural::BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : return "none_without_write_stack" ;
1062	case morpheo::behavioural::BRANCH_CONDITION_NONE_WITH_WRITE_STACK : return "none_with_write_stack" ;
1063	case morpheo::behavioural::BRANCH_CONDITION_FLAG_UNSET : return "flag_unset" ;
1064	case morpheo::behavioural::BRANCH_CONDITION_FLAG_SET : return "flag_set" ;
1065	case morpheo::behavioural::BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : return "read_register_without_write_stack";
1066	case morpheo::behavioural::BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : return "read_register_with_write_stack" ;
1067	case morpheo::behavioural::BRANCH_CONDITION_READ_STACK : return "read_stack" ;
1068	default : return "";
1069	}
1070	};
1071
1072	// template<> inline std::string toString<morpheo::behavioural::event_state_t>(const morpheo::behavioural::event_state_t& x)
1073	// {
1074	// switch (x)
1075	// {
1076	// case morpheo::behavioural::EVENT_STATE_NO_EVENT : return "EVENT_STATE_NO_EVENT";
1077	// case morpheo::behavioural::EVENT_STATE_EVENT : return "EVENT_STATE_EVENT" ;
1078	// case morpheo::behavioural::EVENT_STATE_WAITEND : return "EVENT_STATE_WAITEND" ;
1079	// case morpheo::behavioural::EVENT_STATE_END : return "EVENT_STATE_END" ;
1080	// default : return "";
1081	// }
1082	// };
1083
1084	// template<> inline std::string toString<morpheo::behavioural::event_type_t>(const morpheo::behavioural::event_type_t& x)
1085	// {
1086	// switch (x)
1087	// {
1088	// case morpheo::behavioural::EVENT_TYPE_NONE : return "EVENT_TYPE_NONE" ;
1089	// case morpheo::behavioural::EVENT_TYPE_MISS_SPECULATION : return "EVENT_TYPE_MISS_SPECULATION" ;
1090	// case morpheo::behavioural::EVENT_TYPE_EXCEPTION : return "EVENT_TYPE_EXCEPTION" ;
1091	// case morpheo::behavioural::EVENT_TYPE_BRANCH_NO_ACCURATE : return "EVENT_TYPE_BRANCH_NO_ACCURATE";
1092	// case morpheo::behavioural::EVENT_TYPE_SPR_ACCESS : return "EVENT_TYPE_SPR_ACCESS" ;
1093	// case morpheo::behavioural::EVENT_TYPE_MSYNC : return "EVENT_TYPE_MSYNC" ;
1094	// case morpheo::behavioural::EVENT_TYPE_PSYNC : return "EVENT_TYPE_PSYNC" ;
1095	// case morpheo::behavioural::EVENT_TYPE_CSYNC : return "EVENT_TYPE_CSYNC" ;
1096	// default : return "";
1097	// }
1098	// };
1099
1100	}; // end namespace morpheo
1101
1102	#endif

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