1 | #ifndef morpheo_behavioural_Constants_h |
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2 | #define morpheo_behavioural_Constants_h |
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3 | |
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4 | namespace morpheo { |
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5 | namespace behavioural { |
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6 | |
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7 | //=========================================================[ Type ]===== |
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8 | # define TYPE_ALU 0x0 // 00000 - unit multiple |
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9 | # define TYPE_SHIFT 0x1 // 00000 - unit multiple |
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10 | # define TYPE_MOVE 0x2 // 00000 - unit multiple |
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11 | # define TYPE_TEST 0x3 // 00000 - unit multiple |
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12 | # define TYPE_MUL_DIV 0x4 // 00000 - unit multiple |
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13 | # define TYPE_EXTEND 0x5 // 00000 - unit multiple, type optionnal |
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14 | # define TYPE_FIND 0x6 // 00000 - unit multiple, type optionnal |
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15 | # define TYPE_SPECIAL 0x7 // 00000 - unit uniq |
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16 | # define TYPE_CUSTOM 0x8 // 00000 - unit uniq , type optionnal |
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17 | # define TYPE_BRANCH 0x9 // 00000 - unit multiple |
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18 | # define TYPE_MEMORY 0xa // 00000 - unit uniq |
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19 | |
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20 | # define SIZE_TYPE 5 |
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21 | # define MAX_TYPE (1<<SIZE_TYPE) |
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22 | |
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23 | //====================================================[ Operation ]===== |
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24 | |
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25 | //-------------------------------------------------------[ Memory ]----- |
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26 | # define OPERATION_MEMORY_LOAD 0x0 // 000_0000 |
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27 | # define OPERATION_MEMORY_LOAD_8_Z 0x0 // 000_0000 |
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28 | # define OPERATION_MEMORY_LOAD_16_Z 0x20 // 010_0000 |
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29 | # define OPERATION_MEMORY_LOAD_32_Z 0x40 // 100_0000 |
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30 | # define OPERATION_MEMORY_LOAD_64_Z 0x60 // 110_0000 |
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31 | # define OPERATION_MEMORY_LOAD_8_S 0x10 // 001_0000 |
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32 | # define OPERATION_MEMORY_LOAD_16_S 0x30 // 011_0000 |
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33 | # define OPERATION_MEMORY_LOAD_32_S 0x50 // 101_0000 |
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34 | # define OPERATION_MEMORY_LOAD_64_S 0x70 // 111_0000 |
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35 | |
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36 | # define OPERATION_MEMORY_STORE_8 0x8 // 000_1000 |
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37 | # define OPERATION_MEMORY_STORE_16 0x9 // 000_1001 |
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38 | # define OPERATION_MEMORY_STORE_32 0xa // 000_1010 |
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39 | # define OPERATION_MEMORY_STORE_64 0xb // 000_1011 |
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40 | # define OPERATION_MEMORY_STORE_HEAD_OK 0xc // 000_1100 |
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41 | # define OPERATION_MEMORY_STORE_HEAD_KO 0xd // 000_1101 |
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42 | |
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43 | # define OPERATION_MEMORY_LOCK 0x1 // 000_0001 |
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44 | # define OPERATION_MEMORY_INVALIDATE 0x2 // 000_0010 |
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45 | # define OPERATION_MEMORY_PREFETCH 0x3 // 000_0011 |
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46 | # define OPERATION_MEMORY_FLUSH 0x6 // 000_0110 |
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47 | # define OPERATION_MEMORY_SYNCHRONIZATION 0x7 // 000_0111 |
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48 | |
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49 | #define is_operation_memory_load(x) \ |
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50 | ((x == OPERATION_MEMORY_LOAD_8_Z ) or \ |
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51 | (x == OPERATION_MEMORY_LOAD_16_Z) or \ |
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52 | (x == OPERATION_MEMORY_LOAD_32_Z) or \ |
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53 | (x == OPERATION_MEMORY_LOAD_64_Z) or \ |
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54 | (x == OPERATION_MEMORY_LOAD_8_S ) or \ |
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55 | (x == OPERATION_MEMORY_LOAD_16_S) or \ |
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56 | (x == OPERATION_MEMORY_LOAD_32_S) or \ |
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57 | (x == OPERATION_MEMORY_LOAD_64_S) ) |
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58 | |
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59 | #define is_operation_memory_store(x) \ |
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60 | ((x == OPERATION_MEMORY_STORE_8 ) or \ |
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61 | (x == OPERATION_MEMORY_STORE_16 ) or \ |
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62 | (x == OPERATION_MEMORY_STORE_32 ) or \ |
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63 | (x == OPERATION_MEMORY_STORE_64 ) or \ |
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64 | (x == OPERATION_MEMORY_STORE_HEAD_OK) or \ |
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65 | (x == OPERATION_MEMORY_STORE_HEAD_KO)) |
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66 | |
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67 | #define is_operation_memory_store_head(x) \ |
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68 | ((x == OPERATION_MEMORY_STORE_HEAD_OK) or \ |
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69 | (x == OPERATION_MEMORY_STORE_HEAD_KO)) |
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70 | |
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71 | #define is_operation_memory_load_signed(x) \ |
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72 | ((x == OPERATION_MEMORY_LOAD_8_S ) or \ |
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73 | (x == OPERATION_MEMORY_LOAD_16_S) or \ |
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74 | (x == OPERATION_MEMORY_LOAD_32_S) or \ |
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75 | (x == OPERATION_MEMORY_LOAD_64_S) ) |
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76 | |
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77 | # define MEMORY_ACCESS_8 0x0 |
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78 | # define MEMORY_ACCESS_16 0x1 |
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79 | # define MEMORY_ACCESS_32 0x2 |
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80 | # define MEMORY_ACCESS_64 0x3 |
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81 | |
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82 | # define MEMORY_SIZE_8 8 |
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83 | # define MEMORY_SIZE_16 16 |
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84 | # define MEMORY_SIZE_32 32 |
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85 | # define MEMORY_SIZE_64 64 |
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86 | |
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87 | # define MASK_MEMORY_ACCESS_8 0x0 |
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88 | # define MASK_MEMORY_ACCESS_16 0x1 |
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89 | # define MASK_MEMORY_ACCESS_32 0x3 |
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90 | # define MASK_MEMORY_ACCESS_64 0x7 |
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91 | |
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92 | #define memory_size(x) \ |
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93 | (((x==OPERATION_MEMORY_LOAD_16_Z)or \ |
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94 | (x==OPERATION_MEMORY_LOAD_16_S)or \ |
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95 | (x==OPERATION_MEMORY_STORE_16 ))?MEMORY_SIZE_16: \ |
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96 | (((x==OPERATION_MEMORY_LOAD_32_Z)or \ |
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97 | (x==OPERATION_MEMORY_LOAD_32_S)or \ |
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98 | (x==OPERATION_MEMORY_STORE_32 ))?MEMORY_SIZE_32: \ |
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99 | (((x==OPERATION_MEMORY_LOAD_64_Z)or \ |
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100 | (x==OPERATION_MEMORY_LOAD_64_S)or \ |
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101 | (x==OPERATION_MEMORY_STORE_64 ))?MEMORY_SIZE_64:MEMORY_SIZE_8))) |
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102 | |
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103 | #define memory_access(x) \ |
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104 | (((x==OPERATION_MEMORY_LOAD_16_Z)or \ |
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105 | (x==OPERATION_MEMORY_LOAD_16_S)or \ |
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106 | (x==OPERATION_MEMORY_STORE_16 ))?MEMORY_ACCESS_16: \ |
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107 | (((x==OPERATION_MEMORY_LOAD_32_Z)or \ |
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108 | (x==OPERATION_MEMORY_LOAD_32_S)or \ |
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109 | (x==OPERATION_MEMORY_STORE_32 ))?MEMORY_ACCESS_32: \ |
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110 | (((x==OPERATION_MEMORY_LOAD_64_Z)or \ |
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111 | (x==OPERATION_MEMORY_LOAD_64_S)or \ |
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112 | (x==OPERATION_MEMORY_STORE_64 ))?MEMORY_ACCESS_64:MEMORY_ACCESS_8))) |
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113 | |
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114 | #define mask_memory_access(x) \ |
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115 | (((x==OPERATION_MEMORY_LOAD_16_Z)or \ |
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116 | (x==OPERATION_MEMORY_LOAD_16_S)or \ |
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117 | (x==OPERATION_MEMORY_STORE_16 ))?MASK_MEMORY_ACCESS_16: \ |
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118 | (((x==OPERATION_MEMORY_LOAD_32_Z)or \ |
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119 | (x==OPERATION_MEMORY_LOAD_32_S)or \ |
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120 | (x==OPERATION_MEMORY_STORE_32 ))?MASK_MEMORY_ACCESS_32: \ |
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121 | (((x==OPERATION_MEMORY_LOAD_64_Z)or \ |
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122 | (x==OPERATION_MEMORY_LOAD_64_S)or \ |
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123 | (x==OPERATION_MEMORY_STORE_64 ))?MASK_MEMORY_ACCESS_64:MASK_MEMORY_ACCESS_8))) |
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124 | |
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125 | //---------------------------------------------[ Functionnal Unit ]----- |
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126 | # define OPERATION_ALU_L_ADD 0x1 // 000_0000 l.add , l.addi |
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127 | # define OPERATION_ALU_L_ADDC 0x2 // 000_0000 l.addc , l.addic |
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128 | # define OPERATION_ALU_L_SUB 0x4 // 000_0000 l.sub |
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129 | # define OPERATION_ALU_L_AND 0x8 // 000_0000 l.and , l.andi |
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130 | # define OPERATION_ALU_L_OR 0x10 // 000_0000 l.or , l.ori |
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131 | # define OPERATION_ALU_L_XOR 0x20 // 000_0000 l.xor , l.xori |
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132 | |
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133 | # define OPERATION_SHIFT_L_SLL 0x1 // 000_0000 l.sll , l.slli |
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134 | # define OPERATION_SHIFT_L_SRA 0x2 // 000_0000 l.sra , l.srai |
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135 | # define OPERATION_SHIFT_L_SRL 0x4 // 000_0000 l.srl , l.srli |
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136 | # define OPERATION_SHIFT_L_ROR 0x8 // 000_0000 l.ror , l.rori |
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137 | |
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138 | # define OPERATION_MOVE_L_MOVHI 0x1 // 000_0000 l.movhi |
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139 | # define OPERATION_MOVE_L_CMOV 0x2 // 000_0000 l.cmov |
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140 | |
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141 | # define OPERATION_TEST_L_SFGES 0x41 // 000_0000 l.sfges , l.sfges |
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142 | # define OPERATION_TEST_L_SFGEU 0x1 // 000_0000 l.sfgeu , l.sfgeu |
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143 | # define OPERATION_TEST_L_SFGTS 0x42 // 000_0000 L.sfgts , l.sfgts |
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144 | # define OPERATION_TEST_L_SFGTU 0x2 // 000_0000 l.sfgtu , l.sfgtu |
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145 | # define OPERATION_TEST_L_SFLES 0x44 // 000_0000 l.sfles , l.sfles |
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146 | # define OPERATION_TEST_L_SFLEU 0x4 // 000_0000 l.sfleu , l.sfleu |
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147 | # define OPERATION_TEST_L_SFLTS 0x48 // 000_0000 l.sflts , l.sflts |
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148 | # define OPERATION_TEST_L_SFLTU 0x8 // 000_0000 l.sfltu , l.sfltu |
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149 | # define OPERATION_TEST_L_SFEQ 0x10 // 000_0000 l.sfeq , l.sfeqi |
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150 | # define OPERATION_TEST_L_SFNE 0x20 // 000_0000 l.sfne , l.sfnei |
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151 | |
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152 | # define OPERATION_MUL_DIV_L_MUL 0x1 // 000_0000 l.mul , l.muli |
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153 | # define OPERATION_MUL_DIV_L_MULU 0x2 // 000_0000 l.mulu |
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154 | # define OPERATION_MUL_DIV_L_DIV 0x4 // 000_0000 l.div |
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155 | # define OPERATION_MUL_DIV_L_DIVU 0x8 // 000_0000 l.divu |
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156 | |
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157 | # define OPERATION_EXTEND_L_EXTEND_Z 0x1 // 000_0000 l.extbz , l.exthz, l.extwz |
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158 | # define OPERATION_EXTEND_L_EXTEND_S 0x2 // 000_0000 l.extbs , l.exths, l.extws |
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159 | |
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160 | # define OPERATION_FIND_L_FF1 0x1 // 000_0000 l.ff1 |
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161 | # define OPERATION_FIND_L_FL1 0x2 // 000_0000 l.fl1 |
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162 | |
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163 | # define OPERATION_SPECIAL_L_MFSPR 0x1 // 000_0000 l.mfspr |
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164 | # define OPERATION_SPECIAL_L_MTSPR 0x2 // 000_0000 l.mtspr |
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165 | # define OPERATION_SPECIAL_L_MAC 0x4 // 000_0000 l.mac , l.maci |
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166 | # define OPERATION_SPECIAL_L_MACRC 0x8 // 000_0000 l.macrc |
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167 | # define OPERATION_SPECIAL_L_MSB 0x10 // 000_0000 l.msb |
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168 | |
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169 | # define OPERATION_BRANCH_L_TEST_NF 0x1 // 000_0000 l.bnf |
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170 | # define OPERATION_BRANCH_L_TEST_F 0x2 // 000_0000 l.bf |
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171 | # define OPERATION_BRANCH_L_JALR 0x4 // 000_0000 l.jal , l.jalr , l.jr |
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172 | |
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173 | //-------------------------------------------------------[ Custom ]----- |
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174 | |
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175 | # define OPERATION_CUSTOM_L_1 0x40 // 100_0000 |
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176 | # define OPERATION_CUSTOM_L_2 0x41 // 100_0001 |
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177 | # define OPERATION_CUSTOM_L_3 0x42 // 100_0010 |
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178 | # define OPERATION_CUSTOM_L_4 0x43 // 100_0011 |
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179 | # define OPERATION_CUSTOM_L_5 0x44 // 100_0100 |
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180 | # define OPERATION_CUSTOM_L_6 0x45 // 100_0101 |
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181 | # define OPERATION_CUSTOM_L_7 0x46 // 100_0110 |
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182 | # define OPERATION_CUSTOM_L_8 0x47 // 100_0111 |
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183 | # define OPERATION_CUSTOM_LF_1_D 0x48 // 100_1000 |
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184 | # define OPERATION_CUSTOM_LF_1_S 0x49 // 100_1001 |
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185 | # define OPERATION_CUSTOM_LV_1 0x4c // 100_1100 |
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186 | # define OPERATION_CUSTOM_LV_2 0x4d // 100_1101 |
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187 | # define OPERATION_CUSTOM_LV_3 0x4e // 100_1110 |
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188 | # define OPERATION_CUSTOM_LV_4 0x4f // 100_1111 |
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189 | |
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190 | # define SIZE_OPERATION 7 |
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191 | # define MAX_OPERATION (1<<SIZE_OPERATION) |
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192 | |
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193 | //====================================================[ Exception ]===== |
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194 | // Exception - OpenRISC |
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195 | |
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196 | # define SIZE_EXCEPTION 5 |
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197 | |
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198 | # define EXCEPTION_NONE 0x00 // none exception |
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199 | # define EXCEPTION_RESET 0x01 // software or hardware reset |
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200 | # define EXCEPTION_BUS_ERROR 0x02 // Access at a invalid physical adress |
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201 | # define EXCEPTION_DATA_PAGE 0x03 // No matching or page violation protection in pages tables |
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202 | # define EXCEPTION_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables |
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203 | # define EXCEPTION_TICK_TIMER 0x05 // Tick timer interruption |
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204 | # define EXCEPTION_ALIGNMENT 0x06 // Load/Store access is not aligned |
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205 | # define EXCEPTION_ILLEGAL_INSTRUCTION 0x07 // Instruction is illegal (no implemented) |
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206 | # define EXCEPTION_INTERRUPT 0x08 // External interruption |
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207 | # define EXCEPTION_DATA_TLB 0x09 // DTLB miss |
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208 | # define EXCEPTION_INSTRUCTION_TLB 0x0a // ITLB miss |
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209 | # define EXCEPTION_RANGE 0x0b // Overflow or access at a unimplemented register or context |
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210 | # define EXCEPTION_SYSCALL 0x0c // System Call |
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211 | # define EXCEPTION_FLOATING_POINT 0x0d // Caused by a floating instruction |
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212 | # define EXCEPTION_TRAP 0x0e // L.trap or debug unit |
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213 | # define EXCEPTION_RESERVED_0 0x0f // Reserved for a futur usage |
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214 | # define EXCEPTION_RESERVED_1 0x10 // Reserved for a futur usage |
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215 | # define EXCEPTION_RESERVED_2 0x11 // Reserved for a futur usage |
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216 | # define EXCEPTION_RESERVED_3 0x12 // Reserved for a futur usage |
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217 | # define EXCEPTION_RESERVED_4 0x13 // Reserved for a futur usage |
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218 | # define EXCEPTION_RESERVED_5 0x14 // Reserved for a futur usage |
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219 | # define EXCEPTION_RESERVED_6 0x15 // Reserved for implemented specific exceptions |
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220 | # define EXCEPTION_RESERVED_7 0x16 // Reserved for implemented specific exceptions |
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221 | # define EXCEPTION_RESERVED_8 0x17 // Reserved for implemented specific exceptions |
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222 | # define EXCEPTION_RESERVED_9 0x18 // Reserved for implemented specific exceptions |
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223 | # define EXCEPTION_CUSTOM_0 0x19 // Reserved for custom exceptions |
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224 | # define EXCEPTION_CUSTOM_1 0x1a // Reserved for custom exceptions |
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225 | # define EXCEPTION_CUSTOM_2 0x1b // Reserved for custom exceptions |
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226 | # define EXCEPTION_CUSTOM_3 0x1c // Reserved for custom exceptions |
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227 | # define EXCEPTION_CUSTOM_4 0x1d // Reserved for custom exceptions |
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228 | # define EXCEPTION_CUSTOM_5 0x1e // Reserved for custom exceptions |
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229 | # define EXCEPTION_CUSTOM_6 0x1f // Reserved for custom exceptions |
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230 | |
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231 | #define exception_to_address(x) (x<<8) |
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232 | |
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233 | // Exception Execution |
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234 | # define EXCEPTION_MEMORY_NONE 0x0 // Load/Store generate none exception |
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235 | # define EXCEPTION_MEMORY_ALIGNMENT 0x1 // Load/Store access is not aligned |
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236 | # define EXCEPTION_MEMORY_DATA_TLB 0x2 // DTLB miss |
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237 | # define EXCEPTION_MEMORY_DATA_PAGE 0x3 // No matching or page violation protection in pages tables |
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238 | # define EXCEPTION_MEMORY_BUS_ERROR 0x4 // Access at a invalid physical address |
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239 | # define EXCEPTION_MEMORY_MISS_SPECULATION 0x5 // Load miss speculation |
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240 | # define EXCEPTION_MEMORY_LOAD_SPECULATIVE 0x6 // The load is speculative : write in register file, but don't commit |
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241 | |
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242 | # define EXCEPTION_CUSTOM_NONE 0x1 // Custom unit generate none exception |
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243 | # define EXCEPTION_CUSTOM_CUST_0 0x1 // Reserved for custom exceptions |
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244 | # define EXCEPTION_CUSTOM_CUST_1 0x2 // Reserved for custom exceptions |
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245 | # define EXCEPTION_CUSTOM_CUST_2 0x3 // Reserved for custom exceptions |
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246 | # define EXCEPTION_CUSTOM_CUST_3 0x4 // Reserved for custom exceptions |
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247 | # define EXCEPTION_CUSTOM_CUST_4 0x5 // Reserved for custom exceptions |
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248 | # define EXCEPTION_CUSTOM_CUST_5 0x6 // Reserved for custom exceptions |
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249 | # define EXCEPTION_CUSTOM_CUST_6 0x7 // Reserved for custom exceptions |
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250 | |
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251 | # define EXCEPTION_ALU_NONE 0x0 // Functionnal unit generate none exception |
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252 | # define EXCEPTION_ALU_RANGE 0x1 // |
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253 | # define EXCEPTION_ALU_SPR_ACCESS_INVALID 0x2 // SPR present in ALU but not compatible privilege |
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254 | # define EXCEPTION_ALU_SPR_ACCESS_NOT_COMPLETE 0x3 // SPR not present in ALU |
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255 | |
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256 | //=======================================================[ dcache ]===== |
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257 | |
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258 | //--------------------------------------------------[ dcache_type ]----- |
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259 | |
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260 | # define SIZE_DCACHE_TYPE 4 |
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261 | |
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262 | # define DCACHE_TYPE_LOAD 0x0 // 0000 |
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263 | # define DCACHE_TYPE_LOCK 0x1 // 0001 |
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264 | # define DCACHE_TYPE_INVALIDATE 0x2 // 0010 |
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265 | # define DCACHE_TYPE_PREFETCH 0x3 // 0011 |
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266 | //#define DCACHE_TYPE_ 0x4 // 0100 |
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267 | //#define DCACHE_TYPE_ 0x5 // 0101 |
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268 | # define DCACHE_TYPE_FLUSH 0x6 // 0110 |
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269 | # define DCACHE_TYPE_SYNCHRONIZATION 0x7 // 0111 |
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270 | # define DCACHE_TYPE_STORE_8 0x8 // 1000 |
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271 | # define DCACHE_TYPE_STORE_16 0x9 // 1001 |
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272 | # define DCACHE_TYPE_STORE_32 0xa // 1010 |
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273 | # define DCACHE_TYPE_STORE_64 0xb // 1011 |
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274 | //#define DCACHE_TYPE_ 0xc // 1100 |
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275 | //#define DCACHE_TYPE_ 0xd // 1101 |
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276 | //#define DCACHE_TYPE_ 0xe // 1110 |
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277 | //#define DCACHE_TYPE_ 0xf // 1111 |
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278 | |
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279 | // just take the 4 less significative bits. |
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280 | #define operation_to_dcache_type(x) (x&0xf) |
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281 | |
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282 | //-------------------------------------------------[ dcache_error ]----- |
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283 | |
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284 | # define SIZE_DCACHE_ERROR 1 |
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285 | |
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286 | # define DCACHE_ERROR_NONE 0x0 |
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287 | # define DCACHE_ERROR_BUS_ERROR 0x1 |
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288 | |
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289 | //=================================================[ special_data ]===== |
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290 | |
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291 | # define SIZE_SPECIAL_DATA 2 |
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292 | |
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293 | // Position of flag in "rename register SR" (NOT IN "SR") |
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294 | # define FLAG_POSITION_F 0x0 // Conditionnal branch flag |
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295 | # define FLAG_POSITION_CY 0x1 // Carry was produced by last arithmetic operation |
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296 | # define FLAG_POSITION_OV 0x0 // Overflow occured during last arithmetic operation |
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297 | |
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298 | # define FLAG_F (1<<FLAG_POSITION_F ) // Conditionnal branch flag |
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299 | # define FLAG_CY (1<<FLAG_POSITION_CY) // Carry was produced by last arithmetic operation |
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300 | # define FLAG_OV (1<<FLAG_POSITION_OV) // Overflow occured during last arithmetic operation |
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301 | |
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302 | //==========================================================[ spr ]===== |
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303 | |
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304 | enum |
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305 | { |
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306 | GROUP_SYSTEM_AND_CONTROL, // 0 |
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307 | GROUP_DMMU, // 1 |
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308 | GROUP_IMMU, // 2 |
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309 | GROUP_DCACHE, // 3 |
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310 | GROUP_ICACHE, // 4 |
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311 | GROUP_MAC, // 5 |
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312 | GROUP_DEBUG, // 6 |
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313 | GROUP_PERFORMANCE_COUNTER, // 7 |
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314 | GROUP_POWER_MANAGEMENT, // 8 |
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315 | GROUP_PIC, // 9 |
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316 | GROUP_TICK_TIMER, // 10 |
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317 | GROUP_FLOATING_POINT, // 11 |
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318 | GROUP_RESERVED_1, // 12 |
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319 | GROUP_RESERVED_2, // 13 |
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320 | GROUP_RESERVED_3, // 14 |
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321 | GROUP_RESERVED_4, // 15 |
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322 | GROUP_RESERVED_5, // 16 |
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323 | GROUP_RESERVED_6, // 17 |
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324 | GROUP_RESERVED_7, // 18 |
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325 | GROUP_RESERVED_8, // 19 |
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326 | GROUP_RESERVED_9, // 20 |
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327 | GROUP_RESERVED_10, // 21 |
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328 | GROUP_RESERVED_11, // 22 |
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329 | GROUP_RESERVED_12, // 23 |
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330 | GROUP_CUSTOM_1, // 24 |
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331 | GROUP_CUSTOM_2, // 25 |
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332 | GROUP_CUSTOM_3, // 26 |
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333 | GROUP_CUSTOM_4, // 27 |
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334 | GROUP_CUSTOM_5, // 28 |
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335 | GROUP_CUSTOM_6, // 29 |
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336 | GROUP_CUSTOM_7, // 30 |
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337 | GROUP_CUSTOM_8 // 31 |
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338 | }; |
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339 | |
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340 | # define NB_GROUP 32 |
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341 | # define NB_REG_GROUP_SYSTEM_AND_CONTROL 1536 |
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342 | # define NB_REG_GROUP_DMMU 1536 |
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343 | # define NB_REG_GROUP_IMMU 1536 |
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344 | # define NB_REG_GROUP_DCACHE 6 |
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345 | # define NB_REG_GROUP_ICACHE 4 |
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346 | # define NB_REG_GROUP_MAC 3 |
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347 | # define NB_REG_GROUP_DEBUG 22 |
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348 | # define NB_REG_GROUP_PERFORMANCE_COUNTER 16 |
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349 | # define NB_REG_GROUP_POWER_MANAGEMENT 1 |
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350 | # define NB_REG_GROUP_PIC 3 |
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351 | # define NB_REG_GROUP_TICK_TIMER 2 |
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352 | # define NB_REG_GROUP_FLOATING_POINT 0 |
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353 | # define NB_REG_GROUP_RESERVED_1 0 |
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354 | # define NB_REG_GROUP_RESERVED_2 0 |
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355 | # define NB_REG_GROUP_RESERVED_3 0 |
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356 | # define NB_REG_GROUP_RESERVED_4 0 |
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357 | # define NB_REG_GROUP_RESERVED_5 0 |
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358 | # define NB_REG_GROUP_RESERVED_6 0 |
---|
359 | # define NB_REG_GROUP_RESERVED_7 0 |
---|
360 | # define NB_REG_GROUP_RESERVED_8 0 |
---|
361 | # define NB_REG_GROUP_RESERVED_9 0 |
---|
362 | # define NB_REG_GROUP_RESERVED_10 0 |
---|
363 | # define NB_REG_GROUP_RESERVED_11 0 |
---|
364 | # define NB_REG_GROUP_RESERVED_12 0 |
---|
365 | # define NB_REG_GROUP_CUSTOM_1 0 |
---|
366 | # define NB_REG_GROUP_CUSTOM_2 0 |
---|
367 | # define NB_REG_GROUP_CUSTOM_3 0 |
---|
368 | # define NB_REG_GROUP_CUSTOM_4 0 |
---|
369 | # define NB_REG_GROUP_CUSTOM_5 0 |
---|
370 | # define NB_REG_GROUP_CUSTOM_6 0 |
---|
371 | # define NB_REG_GROUP_CUSTOM_7 0 |
---|
372 | # define NB_REG_GROUP_CUSTOM_8 0 |
---|
373 | |
---|
374 | |
---|
375 | // GROUP_MAC |
---|
376 | # define SPR_MACLO 1 // MAC Low |
---|
377 | # define SPR_MACHI 2 // MAC High |
---|
378 | |
---|
379 | //----------------------------------------------[ spr_mode_access ]----- |
---|
380 | |
---|
381 | # define SPR_ACCESS_MODE_NONE 0x0 // 000 |
---|
382 | # define SPR_ACCESS_MODE_READ_ONLY 0x1 // 001 |
---|
383 | # define SPR_ACCESS_MODE_WRITE_ONLY 0x2 // 010 |
---|
384 | # define SPR_ACCESS_MODE_READ_WRITE 0x3 // 011 |
---|
385 | # define SPR_ACCESS_MODE_READ_ONLY_COND 0x5 // 101 special read |
---|
386 | |
---|
387 | /* |
---|
388 | #define _size_instruction 32 |
---|
389 | #define _size_instruction_log2 5 |
---|
390 | |
---|
391 | //----------------------------------------------------[ Operation ]----- |
---|
392 | // #define _nb_operation 32 |
---|
393 | // #define _size_operation 5 |
---|
394 | |
---|
395 | #define _operation_none 0x0 |
---|
396 | #define _operation_l_adds 0x1 |
---|
397 | #define _operation_l_addu 0x2 |
---|
398 | #define _operation_l_subs 0x3 |
---|
399 | #define _operation_l_and 0x4 |
---|
400 | #define _operation_l_or 0x5 |
---|
401 | #define _operation_l_xor 0x6 |
---|
402 | #define _operation_l_cmove 0x7 |
---|
403 | #define _operation_l_read_imm 0x8 |
---|
404 | #define _operation_l_movhi 0x9 |
---|
405 | #define _operation_l_muls 0xa |
---|
406 | #define _operation_l_mulu 0xb |
---|
407 | #define _operation_l_divs 0xc |
---|
408 | #define _operation_l_divu 0xd |
---|
409 | #define _operation_l_exts 0xe |
---|
410 | #define _operation_l_extz 0xf |
---|
411 | #define _operation_l_ff1 0x10 |
---|
412 | #define _operation_l_fl1 0x11 |
---|
413 | #define _operation_l_sll 0x12 |
---|
414 | #define _operation_l_sla 0x13 |
---|
415 | #define _operation_l_srl 0x14 |
---|
416 | #define _operation_l_ror 0x15 |
---|
417 | #define _operation_l_cmp_eq 0x16 |
---|
418 | #define _operation_l_cmp_ne 0x17 |
---|
419 | #define _operation_l_cmp_ges 0x18 |
---|
420 | #define _operation_l_cmp_geu 0x19 |
---|
421 | #define _operation_l_cmp_gts 0x1a |
---|
422 | #define _operation_l_cmp_gtu 0x1b |
---|
423 | #define _operation_l_cmp_les 0x1c |
---|
424 | #define _operation_l_cmp_leu 0x1d |
---|
425 | #define _operation_l_cmp_lts 0x1e |
---|
426 | #define _operation_l_cmp_ltu 0x1f |
---|
427 | |
---|
428 | //--------------------------------------------------[ destination ]----- |
---|
429 | #define _size_destination1 4 |
---|
430 | |
---|
431 | #define cst_DESTINATION1_NONE 0x0 |
---|
432 | #define mask_DESTINATION1_GPR 0x1 |
---|
433 | #define mask_DESTINATION1_MEMORY 0x2 |
---|
434 | #define mask_DESTINATION1_SPR 0x4 |
---|
435 | #define mask_DESTINATION1_MAC_UNIT 0x8 |
---|
436 | |
---|
437 | #define _size_destination2 3 |
---|
438 | |
---|
439 | #define cst_DESTINATION2_NONE 0x0 |
---|
440 | #define mask_DESTINATION2_COMMIT 0x1 |
---|
441 | #define mask_DESTINATION2_MEMORY 0x2 |
---|
442 | #define mask_DESTINATION2_SPR 0x4 |
---|
443 | |
---|
444 | //----------------------------------------------------[ exec_flag ]----- |
---|
445 | #define _size_exec_flag 2 |
---|
446 | |
---|
447 | #define mask_EXEC_FLAG_NONE 0x1 |
---|
448 | #define mask_EXEC_FLAG_CARRY 0x1 |
---|
449 | #define mask_EXEC_FLAG_FLAG 0x1 |
---|
450 | #define mask_EXEC_FLAG_OVERFLOW 0x2 |
---|
451 | |
---|
452 | //---------------------------------------------------[ exec_excep ]----- |
---|
453 | #define _size_exec_excep 1 |
---|
454 | |
---|
455 | #define mask_EXEC_EXCEP_NONE 0x0 |
---|
456 | #define mask_EXEC_EXCEP_RANGE 0x1 |
---|
457 | |
---|
458 | //----------------------------------------------------[ Condition ]----- |
---|
459 | #define _size_condition 3 |
---|
460 | |
---|
461 | #define cst_CONDITION_UNCONDITIONAL 0x0 // None condition (jump) |
---|
462 | #define mask_CONDITION_CONDITIONAL 0x2 |
---|
463 | #define mask_CONDITION_CONDITIONAL_NF 0x0 // Branch if Flag is clear |
---|
464 | #define mask_CONDITION_CONDITIONAL_F 0x1 // Branch if Flag is set |
---|
465 | #define mask_CONDITION_REG 0x4 // Branch if a register is read |
---|
466 | #define mask_CONDITION_STACK 0x8 // Branch with pop in stack pointer |
---|
467 | |
---|
468 | //-------------------------------------------------[ branch_state ]----- |
---|
469 | #define cst_BRANCH_STATE_NONE 0x0 // 0 0 |
---|
470 | #define cst_BRANCH_STATE_NSPEC_TAKE 0x1 // 0 1 -> incondionnal |
---|
471 | #define cst_BRANCH_STATE_SPEC_NTAKE 0x2 // 1 0 |
---|
472 | #define cst_BRANCH_STATE_SPEC_TAKE 0x3 // 1 1 |
---|
473 | */ |
---|
474 | |
---|
475 | /* |
---|
476 | #define M_CPU_SIZE_INST 32 |
---|
477 | |
---|
478 | //---------------------------------------------------- |
---|
479 | // Exception type |
---|
480 | //---------------------------------------------------- |
---|
481 | |
---|
482 | #define M_CPU_LOG2_NB_EXCP 5 |
---|
483 | #define M_CPU_NB_EXCP 32 |
---|
484 | |
---|
485 | #define EXCP_NO 0x00 // none exception |
---|
486 | #define EXCP_RESET 0x01 // software or hardware reset |
---|
487 | #define EXCP_BERR 0x02 // Access at a invalid physical adress |
---|
488 | #define EXCP_D_PAGE 0x03 // No matching or page violation protection in pages tables |
---|
489 | #define EXCP_I_PAGE 0x04 // No matching or page violation protection in pages tables |
---|
490 | #define EXCP_TICK_TIMER 0x05 // Tick timer interruption |
---|
491 | #define EXCP_ALIGNMENT 0x06 // Load/Store access is not aligned |
---|
492 | #define EXCP_ILL_INST 0x07 // Instruction is illegal (no implemented) |
---|
493 | #define EXCP_IRQ 0x08 // External interruption |
---|
494 | #define EXCP_D_TLB 0x09 // DTLB miss |
---|
495 | #define EXCP_I_TLB 0x0a // ITLB miss |
---|
496 | #define EXCP_RANGE 0x0b // Overflow or access at a unimplemented register or context |
---|
497 | #define EXCP_SYSCALL 0x0c // System Call |
---|
498 | #define EXCP_FP 0x0d // Caused by a floating instruction |
---|
499 | #define EXCP_TRAP 0x0e // L.trap or debug unit |
---|
500 | #define EXCP_RES0 0x0f // Reserved for a futur usage |
---|
501 | #define EXCP_RES1 0x10 // Reserved for a futur usage |
---|
502 | #define EXCP_RES2 0x11 // Reserved for a futur usage |
---|
503 | #define EXCP_RES3 0x12 // Reserved for a futur usage |
---|
504 | #define EXCP_RES4 0x13 // Reserved for a futur usage |
---|
505 | #define EXCP_RES5 0x14 // Reserved for a futur usage |
---|
506 | #define EXCP_RES6 0x15 // Reserved for implemented specific exceptions |
---|
507 | #define EXCP_RES7 0x16 // Reserved for implemented specific exceptions |
---|
508 | #define EXCP_RES8 0x17 // Reserved for implemented specific exceptions |
---|
509 | #define EXCP_RES9 0x18 // Reserved for implemented specific exceptions |
---|
510 | #define EXCP_CUST0 0x19 // Reserved for custom exceptions |
---|
511 | #define EXCP_CUST1 0x1a // Reserved for custom exceptions |
---|
512 | #define EXCP_CUST2 0x1b // Reserved for custom exceptions |
---|
513 | #define EXCP_CUST3 0x1c // Reserved for custom exceptions |
---|
514 | #define EXCP_CUST4 0x1d // Reserved for custom exceptions |
---|
515 | #define EXCP_CUST5 0x1e // Reserved for custom exceptions |
---|
516 | #define EXCP_CUST6 0x1f // Reserved for custom exceptions |
---|
517 | |
---|
518 | //---------------------------------------------------- |
---|
519 | // Flags |
---|
520 | //---------------------------------------------------- |
---|
521 | |
---|
522 | #define M_CPU_NB_FLAG 3 |
---|
523 | |
---|
524 | // Integer flags |
---|
525 | #define FLAG_F 0x1 // Conditionnal branch flag |
---|
526 | #define FLAG_CY 0x2 // Carry was produced by last arithmétic operation |
---|
527 | #define FLAG_OV 0x4 // Overflow occured during last arithmetic operation |
---|
528 | |
---|
529 | // Floating flags |
---|
530 | #define FLAG_OVF 0x004 // Overflow occured during last arithmetic operation |
---|
531 | #define FLAG_UNF 0x008 // Underflow flags |
---|
532 | #define FLAG_SNF 0x010 // Result SNAN |
---|
533 | #define FLAG_QNF 0x020 // Result QNAN |
---|
534 | #define FLAG_ZF 0x040 // Result is nul |
---|
535 | #define FLAG_IXF 0x080 // Result is inexact |
---|
536 | #define FLAG_IVF 0x100 // Result is invalid |
---|
537 | #define FLAG_INF 0x200 // Result is infinite |
---|
538 | #define FLAG_DZF 0x400 // Division by zero |
---|
539 | |
---|
540 | // Position of flag in "rename register SR" (NOT IN "SR") |
---|
541 | #define FLAG_POS_F 0x0 // Conditionnal branch flag |
---|
542 | #define FLAG_POS_CY 0x1 // Carry was produced by last arithmétic operation |
---|
543 | #define FLAG_POS_OV 0x0 // Overflow occured during last arithmetic operation |
---|
544 | |
---|
545 | //---------------------------------------------------- |
---|
546 | // Instruction type |
---|
547 | //---------------------------------------------------- |
---|
548 | |
---|
549 | #define M_CPU_LOG2_NB_TYPE 4 |
---|
550 | |
---|
551 | #define TYPE_NOP 0x0 |
---|
552 | #define TYPE_ALU_F 0x1 // Instruction ALU with flag using (ADD, SUB, ADDC ...) |
---|
553 | #define TYPE_ALU_NF 0x2 // Instruction ALU without flag using (AND, OR ...) |
---|
554 | #define TYPE_MAC 0x3 // Instruction ALU with utilisation of register HI/LO |
---|
555 | #define TYPE_J 0x4 // Branch instruction |
---|
556 | #define TYPE_SPR_READ 0x5 // Instruction special : l.mfspr |
---|
557 | #define TYPE_SPR_WRITE 0x6 // Instruction special : l.mtspr |
---|
558 | #define TYPE_SPECIAL 0x7 // Instruction execute in decode stage |
---|
559 | #define TYPE_CUSTOM 0x8 // Instruction Custom |
---|
560 | |
---|
561 | #define TYPE_LOAD_Z 0x9 // Load access (extended by zero) |
---|
562 | #define TYPE_LOAD_S 0xa // Load access (sign extended) |
---|
563 | #define TYPE_STORE 0xc // Store access |
---|
564 | |
---|
565 | //---------------------------------------------------- |
---|
566 | // Condition to branch |
---|
567 | //---------------------------------------------------- |
---|
568 | |
---|
569 | #define M_CPU_LOG2_NB_COND 4 |
---|
570 | |
---|
571 | #define COND_NONE 0x0 // None condition (jump) |
---|
572 | #define COND_F 0x2 // Branch if Flag is set |
---|
573 | #define COND_NF 0x3 // Branch if Flag is clear |
---|
574 | #define COND_REG 0x4 // Branch if a register is read |
---|
575 | #define COND_STACK 0x8 // Branch with pop in stack pointer |
---|
576 | |
---|
577 | //---------------------------------------------------- |
---|
578 | // Event : State and Type |
---|
579 | //---------------------------------------------------- |
---|
580 | |
---|
581 | #define EVENT_STATE_NO_EVENT 0 // no event : current case |
---|
582 | #define EVENT_STATE_EVENT 1 // Have a event : make necessary to manage the event |
---|
583 | #define EVENT_STATE_WAITEND 2 // Wait end of manage event (restaure a good context) |
---|
584 | #define EVENT_STATE_END 3 // CPU can continue |
---|
585 | |
---|
586 | #define EVENT_TYPE_MISS 0 // miss of speculation |
---|
587 | #define EVENT_TYPE_EXCP 1 // exception or interruption occure |
---|
588 | |
---|
589 | // SPEC? TAKE? |
---|
590 | #define BRANCH_STATE_NONE 0 // 0 0 |
---|
591 | #define BRANCH_STATE_NSPEC_TAKE 1 // 0 1 -> incondionnal |
---|
592 | #define BRANCH_STATE_SPEC_NTAKE 2 // 1 0 |
---|
593 | #define BRANCH_STATE_SPEC_TAKE 3 // 1 1 |
---|
594 | |
---|
595 | //---------------------------------------------------- |
---|
596 | // Name to particular register |
---|
597 | //---------------------------------------------------- |
---|
598 | |
---|
599 | //~~~~~~~~~~~~~~~~~~~~~~~~~~ |
---|
600 | // GENERAL PURPOSE REGISTER |
---|
601 | //~~~~~~~~~~~~~~~~~~~~~~~~~~ |
---|
602 | #define M_CPU_LOG2_NB_GPR_LOG 5 |
---|
603 | #define M_CPU_NB_GPR_LOG (1<<M_CPU_LOG2_NB_GPR_LOG) |
---|
604 | |
---|
605 | #define GPR_LOG_LR 0x09 // Link register |
---|
606 | #define REG_PHY_SR 0x00 // Status register |
---|
607 | |
---|
608 | //~~~~~~~~~~~~~~~~~~~~~~~~~~ |
---|
609 | // SPECIAL PURPOSE REGISTER |
---|
610 | //~~~~~~~~~~~~~~~~~~~~~~~~~~ |
---|
611 | #define M_CPU_LOG2_NB_SPR_LOG 1 |
---|
612 | #define M_CPU_NB_SPR_LOG (1<<M_CPU_LOG2_NB_SPR_LOG) |
---|
613 | #define M_CPU_SPR_SIZE_DATA 2 // Size of the most great register |
---|
614 | |
---|
615 | #define SPR_LOG_SR_F 0x00 // Status register bit F (size = 1) |
---|
616 | #define SPR_LOG_SR_CY_OV 0x01 // Status register bit overflow and carry (size = 2) |
---|
617 | //#define SPR_LOG_SR_LO 0x02 // MAC LSB (size = 32) |
---|
618 | //#define SPR_LOG_SR_HI 0x03 // MAC MSB (size = 32) |
---|
619 | */ |
---|
620 | |
---|
621 | /* |
---|
622 | //---------------------------------------------------- |
---|
623 | // Code Operation (before decode) |
---|
624 | //---------------------------------------------------- |
---|
625 | |
---|
626 | // Codop - [31:26] Instructions with immediat |
---|
627 | #define OPCOD_L_J 0x00 // 000_000 |
---|
628 | #define OPCOD_L_JAL 0x01 // 000_001 |
---|
629 | #define OPCOD_L_BNF 0x03 // 000_011 |
---|
630 | #define OPCOD_L_BF 0x04 // 000_100 |
---|
631 | #define OPCOD_L_RFE 0x09 // 001_001 |
---|
632 | #define OPCOD_L_JR 0x11 // 010_001 |
---|
633 | #define OPCOD_L_JALR 0x12 // 010_010 |
---|
634 | #define OPCOD_L_MACI 0x13 // 010_011 |
---|
635 | #define OPCOD_L_CUST1 0x1c // 011_100 |
---|
636 | #define OPCOD_L_CUST2 0x1d // 011_101 |
---|
637 | #define OPCOD_L_CUST3 0x1e // 011_110 |
---|
638 | #define OPCOD_L_CUST4 0x1f // 011_111 |
---|
639 | #define OPCOD_L_CUST5 0x3c // 111_100 |
---|
640 | #define OPCOD_L_CUST6 0x3d // 111_101 |
---|
641 | #define OPCOD_L_CUST7 0x3e // 111_110 |
---|
642 | #define OPCOD_L_CUST8 0x3f // 111_111 |
---|
643 | #define OPCOD_L_LD 0x20 // 100_000 |
---|
644 | #define OPCOD_L_LWZ 0x21 // 100_001 |
---|
645 | #define OPCOD_L_LWS 0x22 // 100_010 |
---|
646 | #define OPCOD_L_LBZ 0x23 // 100_011 |
---|
647 | #define OPCOD_L_LBS 0x24 // 100_100 |
---|
648 | #define OPCOD_L_LHZ 0x25 // 100_101 |
---|
649 | #define OPCOD_L_LHS 0x26 // 100_110 |
---|
650 | #define OPCOD_L_ADDI 0x27 // 100_111 |
---|
651 | #define OPCOD_L_ADDIC 0x28 // 101_000 |
---|
652 | #define OPCOD_L_ANDI 0x29 // 101_001 |
---|
653 | #define OPCOD_L_ORI 0x2a // 101_010 |
---|
654 | #define OPCOD_L_XORI 0x2b // 101_011 |
---|
655 | #define OPCOD_L_MULI 0x2c // 101_100 |
---|
656 | #define OPCOD_L_MFSPR 0x2d // 101_101 |
---|
657 | #define OPCOD_L_MTSPR 0x30 // 110_000 |
---|
658 | #define OPCOD_L_SD 0x32 // 110_010 |
---|
659 | #define OPCOD_L_SW 0x35 // 110_101 |
---|
660 | #define OPCOD_L_SB 0x36 // 110_110 |
---|
661 | #define OPCOD_L_SH 0x37 // 110_111 |
---|
662 | |
---|
663 | #define OPCOD_INST_LV 0x0a // 001_010 // Instruction ORVDX64 |
---|
664 | #define OPCOD_INST_LF 0x33 // 110_011 // Instruction ORFPX32/64 |
---|
665 | |
---|
666 | #define OPCOD_SPECIAL 0x38 // 111_000 // Instructions Register-Register |
---|
667 | #define OPCOD_SPECIAL_1 0x39 // 111_001 // Instructions "set flag" with register |
---|
668 | #define OPCOD_SPECIAL_2 0x2f // 101_111 // Instructions "set flag" with immediat |
---|
669 | #define OPCOD_SPECIAL_6 0x2e // 101_110 // Instruction Shift/Rotate with immediat |
---|
670 | #define OPCOD_SPECIAL_7 0x31 // 110_001 // Instructions multiply with HI-LO |
---|
671 | #define OPCOD_SPECIAL_8 0x06 // 000_110 // Instructions acces at HI-LO |
---|
672 | |
---|
673 | // OPCOD_SPECIAL instructions - [9:8] [3:0] Instructions Register-Register |
---|
674 | #define OPCOD_L_ADD 0x00 // 00_0000 |
---|
675 | #define OPCOD_L_ADDC 0x01 // 00_0001 |
---|
676 | #define OPCOD_L_SUB 0x02 // 00_0010 |
---|
677 | #define OPCOD_L_AND 0x03 // 00_0011 |
---|
678 | #define OPCOD_L_OR 0x04 // 00_0100 |
---|
679 | #define OPCOD_L_XOR 0x05 // 00_0101 |
---|
680 | #define OPCOD_L_CMOV 0x0e // 00_1110 |
---|
681 | #define OPCOD_L_FF1 0x0f // 00_1111 |
---|
682 | #define OPCOD_L_FL1 0x1f // 01_1111 |
---|
683 | #define OPCOD_L_MUL 0x36 // 11_0110 |
---|
684 | #define OPCOD_L_DIV 0x39 // 11_1001 |
---|
685 | #define OPCOD_L_DIVU 0x3a // 11_1010 |
---|
686 | #define OPCOD_L_MULU 0x3b // 11_1011 |
---|
687 | |
---|
688 | #define OPCOD_SPECIAL_3 0xc // 1100 // Instructions extend |
---|
689 | #define OPCOD_SPECIAL_4 0xd // 1101 // Instructions extend (64b) |
---|
690 | #define OPCOD_SPECIAL_5 0x8 // 1000 // Instruction Shift/Rotate with register |
---|
691 | |
---|
692 | // OPCOD_SPECIAL_1 instructions - [25:21] Instructions "set flag" with register |
---|
693 | #define OPCOD_L_SFEQ 0x00 // 00000 |
---|
694 | #define OPCOD_L_SFNE 0x01 // 00001 |
---|
695 | #define OPCOD_L_SFGTU 0x02 // 00010 |
---|
696 | #define OPCOD_L_SFGEU 0x03 // 00011 |
---|
697 | #define OPCOD_L_SFLTU 0x04 // 00100 |
---|
698 | #define OPCOD_L_SFLEU 0x05 // 00101 |
---|
699 | #define OPCOD_L_SFGTS 0x0a // 01010 |
---|
700 | #define OPCOD_L_SFGES 0x0b // 01011 |
---|
701 | #define OPCOD_L_SFLTS 0x0c // 01100 |
---|
702 | #define OPCOD_L_SFLES 0x0d // 01101 |
---|
703 | |
---|
704 | // OPCOD_SPECIAL_2 instructions - [25:21] Instructions "set flag" with immediat |
---|
705 | #define OPCOD_L_SFEQI 0x00 // 00000 |
---|
706 | #define OPCOD_L_SFNEI 0x01 // 00001 |
---|
707 | #define OPCOD_L_SFGTUI 0x02 // 00010 |
---|
708 | #define OPCOD_L_SFGEUI 0x03 // 00011 |
---|
709 | #define OPCOD_L_SFLTUI 0x04 // 00100 |
---|
710 | #define OPCOD_L_SFLEUI 0x05 // 00101 |
---|
711 | #define OPCOD_L_SFGTSI 0x0a // 01010 |
---|
712 | #define OPCOD_L_SFGESI 0x0b // 01011 |
---|
713 | #define OPCOD_L_SFLTSI 0x0c // 01100 |
---|
714 | #define OPCOD_L_SFLESI 0x0d // 01101 |
---|
715 | |
---|
716 | // OPCOD_SPECIAL_3 instructions - [9:6] Instructions extend |
---|
717 | #define OPCOD_L_EXTHS 0x0 // 0000 |
---|
718 | #define OPCOD_L_EXTHZ 0x2 // 0010 |
---|
719 | #define OPCOD_L_EXTBS 0x1 // 0001 |
---|
720 | #define OPCOD_L_EXTBZ 0x3 // 0011 |
---|
721 | |
---|
722 | // OPCOD_SPECIAL_4 instructions - [9:6] Instructions extend (64b) |
---|
723 | #define OPCOD_L_EXTWS 0x0 // 0000 |
---|
724 | #define OPCOD_L_EXTWZ 0x1 // 0001 |
---|
725 | |
---|
726 | // OPCOD_SPECIAL_5 instructions - [7:6] Instruction Shift/Rotate with register |
---|
727 | #define OPCOD_L_SLL 0x0 // 00 |
---|
728 | #define OPCOD_L_SRL 0x1 // 01 |
---|
729 | #define OPCOD_L_SRA 0x2 // 10 |
---|
730 | #define OPCOD_L_ROR 0x3 // 11 |
---|
731 | |
---|
732 | // OPCOD_SPECIAL_6 instructions - [7:6] Instruction Shift/Rotate with immediat |
---|
733 | #define OPCOD_L_SLLI 0x0 // 00 |
---|
734 | #define OPCOD_L_SRLI 0x1 // 01 |
---|
735 | #define OPCOD_L_SRAI 0x2 // 10 |
---|
736 | #define OPCOD_L_RORI 0x3 // 11 |
---|
737 | |
---|
738 | // OPCOD_SPECIAL_7 instructions - [3:0] Instructions multiply with HI-LO |
---|
739 | #define OPCOD_L_MAC 0x1 // 0001 |
---|
740 | #define OPCOD_L_MSB 0x2 // 0010 |
---|
741 | |
---|
742 | // OPCOD_SPECIAL_8 instructions - [17] Instructions acces at HI-LO |
---|
743 | #define OPCOD_L_MOVHI 0x0 // 0 |
---|
744 | #define OPCOD_L_MACRC 0x1 // 1 |
---|
745 | |
---|
746 | // Particular case Instructions systems |
---|
747 | #define OPCOD_L_MSYNC 0x22000000 |
---|
748 | #define OPCOD_L_CSYNC 0x23000000 |
---|
749 | #define OPCOD_L_PSYNC 0x22800000 |
---|
750 | #define OPCOD_L_NOP 0x1500 |
---|
751 | #define OPCOD_L_SYS 0x2000 |
---|
752 | #define OPCOD_L_TRAP 0x2100 |
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753 | |
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754 | //---------------------------------------------------- |
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755 | // Code Operation (after decode) |
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756 | //---------------------------------------------------- |
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757 | |
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758 | typedef enum |
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759 | { |
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760 | // ##### WARNING : This opcode must be the first##### |
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761 | INST_L_NO_IMPLEMENTED , // Operation is not implemented |
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762 | |
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763 | INST_L_ADD , // L.ADD , L.ADDI , L.ADDC , L.ADDIC |
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764 | INST_L_AND , // L.AND , L.ANDI |
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765 | INST_L_OR , // L.OR , L.ORI |
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766 | INST_L_XOR , // L.XOR , L.XORI |
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767 | INST_L_CMOV , // L.CMOV |
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768 | INST_L_SUB , // L.SUB |
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769 | INST_L_FF1 , // L.FF1 |
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770 | INST_L_EXTBS , // L.EXTBS |
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771 | INST_L_EXTBZ , // L.EXTBZ |
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772 | INST_L_EXTHS , // L.EXTHS |
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773 | INST_L_EXTHZ , // L.EXTHZ |
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774 | INST_L_EXTWS , // L.EXTWS |
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775 | INST_L_EXTWZ , // L.EXTWZ |
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776 | INST_L_e , // |
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777 | INST_L_f , // |
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778 | INST_L_MUL , // L.MUL , L.MULI |
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779 | INST_L_MULU , // L.MULU |
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780 | INST_L_DIV , // L.DIV |
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781 | INST_L_DIVU , // L.DIVU |
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782 | INST_L_SLL , // L.SLL , L.SLLI |
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783 | INST_L_SRL , // L.SRL , L.SRLI |
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784 | INST_L_SRA , // L.SRA , L.SRAI |
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785 | INST_L_ROR , // L.ROR , L.RORI |
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786 | INST_L_SFGES , // L.SFGES , L.SFGESI |
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787 | INST_L_SFGEU , // L.SFGEU , L.SFGEUI |
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788 | INST_L_SFGTS , // L.SFGTS , L.SFGTSI |
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789 | INST_L_SFGTU , // L.SFGTU , L.SFGTUI |
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790 | INST_L_SFLES , // L.SFLES , L.SFLESI |
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791 | INST_L_SFLEU , // L.SFLEU , L.SFLEUI |
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792 | INST_L_SFLTS , // L.SFLTS , L.SFLTSI |
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793 | INST_L_SFLTU , // L.SFLTU , L.SFLTUI |
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794 | INST_L_SFEQ , // L.SFEQ , L.SFEQI |
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795 | INST_L_SFNE , // L.SFNE , L.SFNEI |
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796 | INST_L_READ , // L.BNF , L.BF , L.JR |
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797 | INST_L_MOVHI , // L.MOVI |
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798 | INST_L_CSYNC , // L.CSYNC |
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799 | INST_L_MSYNC , // L.MSYNC |
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800 | INST_L_PSYNC , // L.PSYNC |
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801 | INST_L_RFE , // L.RFE |
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802 | INST_L_MAC , // L.MAC , L.MACI |
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803 | INST_L_MSB , // L.MSB |
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804 | INST_L_MACRC , // L.MACRC |
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805 | INST_L_2b , // |
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806 | INST_L_MEMB , // L.LBS , L.LBZ , L.SB |
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807 | INST_L_MEMH , // L.LHS , L.LHZ , L.SH |
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808 | INST_L_MEMW , // L.LWS , L.LWZ , L.SW |
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809 | INST_L_MEMD , // L.LD , L.SD |
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810 | INST_L_CUST1 , // L.CUST1 |
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811 | INST_L_CUST2 , // L.CUST2 |
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812 | INST_L_CUST3 , // L.CUST3 |
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813 | INST_L_CUST4 , // L.CUST4 |
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814 | INST_L_CUST5 , // L.CUST5 |
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815 | INST_L_CUST6 , // L.CUST6 |
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816 | INST_L_CUST7 , // L.CUST7 |
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817 | INST_L_CUST8 , // L.CUST8 |
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818 | INST_L_38 , // |
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819 | INST_L_39 , // |
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820 | INST_L_3a , // |
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821 | INST_L_3b , // |
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822 | INST_L_3c , // |
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823 | INST_L_3d , // |
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824 | INST_L_3e , // |
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825 | INST_NOP // L.NOP |
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826 | } opcod_t; |
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827 | |
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828 | #define LOG2_NB_INST_L 6 |
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829 | #define NB_INST_L 64 // +1 -> INST_L_NO_IMPLEMENTED |
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830 | //#define NB_INST_L (INST_L_NO_IMPLEMENTED+1) |
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831 | */ |
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832 | |
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833 | }; // end namespace behavioural |
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834 | }; // end namespace morpheo |
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835 | |
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836 | #endif |
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