|
Last change
on this file since 57 was
57,
checked in by rosiere, 17 years ago
|
- VHDL - RegisterFile_Multi_Banked (only partial_crossbar)
- SystemC - modif Component, interface and co -> ajout du type Tusage_T pour instancier un coposant mais ne demander que le VHDL ou le systemC.
- Séminaire interne
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|
File size:
876 bytes
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| Line | |
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| 1 | set size 1.0, 1.0 |
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| 2 | set terminal postscript eps enhanced color |
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| 3 | |
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| 4 | set out "../Schema_eps/synthese_FPGA-registerfile.eps" |
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| 5 | |
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| 6 | unset label |
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| 7 | unset log |
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| 8 | |
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| 9 | set data style boxes |
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| 10 | set boxwidth 10 |
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| 11 | set style fill solid 1.000000 border -1 |
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| 12 | |
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| 13 | set grid |
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| 14 | set xlabel "Architecture" |
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| 15 | set ylabel "Nombre LUTs" |
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| 16 | set yrange [1:100000] |
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| 17 | unset logscale; set logscale y |
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| 18 | set xtics rotate by -25 ('R:1 W:1' 0 , \ |
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| 19 | 'R:2 W:1' 60 , \ |
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| 20 | 'R:4 W:1' 120 , \ |
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| 21 | 'R:8 W:1' 180 , \ |
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| 22 | 'R:1 W:2' 240 , \ |
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| 23 | 'R:1 W:4' 300 , \ |
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| 24 | 'R:1 W:8' 360 ) |
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| 25 | |
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| 26 | plot "synthese_FPGA-registerfile_monolithic.dat" title "monolithic",\ |
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| 27 | "synthese_FPGA-registerfile_1_bank.dat" title "1 banc" ,\ |
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| 28 | "synthese_FPGA-registerfile_2_bank.dat" title "2 bancs" ,\ |
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| 29 | "synthese_FPGA-registerfile_4_bank.dat" title "4 bancs" ,\ |
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| 30 | "synthese_FPGA-registerfile_8_bank.dat" title "8 bancs" |
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| 31 | |
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| 32 | |
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