source: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/VHDL_methodologie.fig @ 57

Last change on this file since 57 was 57, checked in by rosiere, 17 years ago
  • VHDL - RegisterFile_Multi_Banked (only partial_crossbar)
  • SystemC - modif Component, interface and co -> ajout du type Tusage_T pour instancier un coposant mais ne demander que le VHDL ou le systemC.
  • Séminaire interne
File size: 2.5 KB
Line 
1#FIG 3.2
2Landscape
3Center
4Inches
5Letter 
6100.00
7Single
8-2
91200 2
106 -1425 -600 2850 4050
111 1 0 1 0 6 51 -1 20 0.000 1 0.0000 -750 750 600 225 -750 750 -150 525
121 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 2175 600 225 1500 2175 2100 1950
131 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 3075 600 225 1500 3075 2100 2850
142 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2
15        3 0 1.00 60.00 120.00
16         1650 600 2250 1050
172 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2
18        3 0 1.00 60.00 120.00
19         1350 600 1050 1050
202 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2
21        3 0 1.00 60.00 120.00
22         750 1500 1350 1950
232 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2
24        3 0 1.00 60.00 120.00
25         2250 1500 1650 1950
262 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 5
27        3 0 1.00 60.00 120.00
28         900 2175 0 2175 0 900 450 900 450 1050
292 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
30        3 0 1.00 60.00 120.00
31         1500 2400 1500 2850
322 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
33        3 0 1.00 60.00 120.00
34         1500 3300 1500 3750
352 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
36        3 0 1.00 60.00 120.00
37         -150 750 750 750 750 1050
382 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 4
39        3 0 1.00 60.00 120.00
40         -750 525 -750 -75 1200 -75 1200 150
412 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
42        3 0 1.00 60.00 120.00
43         900 3075 -750 3075 -750 975
442 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
45        3 0 1.00 60.00 120.00
46         1500 -300 1500 150
472 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 5
48         2100 -300 900 -300 900 -600 2100 -600 2100 -300
492 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 5
50         2100 4050 900 4050 900 3750 2100 3750 2100 4050
512 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5
52         2100 600 900 600 900 150 2100 150 2100 600
532 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5
54         1350 1500 150 1500 150 1050 1350 1050 1350 1500
552 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5
56         2850 1500 1650 1500 1650 1050 2850 1050 2850 1500
574 1 0 50 -1 2 8 0.0000 0 75 240 1500 2175 Test\001
584 1 0 50 -1 2 8 0.0000 0 90 990 2250 1275 TestBench VHDL\001
594 1 0 50 -1 2 8 0.0000 0 105 1005 750 1275 G\351n\351rateur VHDL\001
604 1 0 50 -1 2 8 0.0000 0 105 465 1500 375 SystemC\001
614 1 0 50 -1 2 8 0.0000 0 90 1050 -750 675 Modification locale\001
624 1 0 50 -1 2 8 0.0000 0 105 1035 -750 825 (micro architecture)\001
634 1 0 50 -1 2 8 0.0000 0 105 315 1500 -450 D\351but\001
644 1 0 50 -1 2 8 0.0000 0 135 810 1500 3075 Synth\350tisable ?\001
654 1 0 50 -1 2 8 0.0000 0 90 195 1500 3900 Fin\001
66-6
674 0 0 51 -1 0 8 0.0000 0 75 120 1575 3450 ok\001
684 0 0 51 -1 0 8 0.0000 0 75 315 -75 675 locale\001
694 0 0 51 -1 0 8 0.0000 0 90 375 -675 450 globale\001
704 2 0 51 -1 0 8 0.0000 0 75 120 900 3000 ko\001
714 2 0 51 -1 0 8 0.0000 0 75 120 900 2100 ko\001
724 0 0 51 -1 0 8 0.0000 0 75 120 1575 2550 ok\001
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