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source: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_allocation.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 15 years ago
Almost complete design with Test and test platform
Property svn:keywords set to `Id`
File size: 12.7 KB

Line
1	/*
2	* $Id: Morpheo_allocation.cpp 88 2008-12-10 18:31:39Z rosiere $
3	*
4	* [ Description ]
5	*
6	*/
7
8	#include "TopLevel/include/Morpheo.h"
9	#include "Behavioural/include/Allocation.h"
10
11	namespace morpheo {
12
13	#undef FUNCTION
14	#define FUNCTION "Morpheo::allocation"
15	void Morpheo::allocation
16	(
17	#ifdef STATISTICS
18	morpheo::behavioural::Parameters_Statistics * param_statistics
19	#else
20	void
21	#endif
22	)
23	{
24	log_begin(Morpheo,FUNCTION);
25
26	_component = new behavioural::Component (_usage);
27
28	behavioural::Entity * entity = _component->set_entity (_name
29	,"Morpheo"
30	#ifdef POSITION
31	,COMBINATORY
32	#endif
33	);
34
35	_interfaces = entity->set_interfaces();
36
37	// ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
38	{
39	behavioural::Interface * interface = _interfaces->set_interface(""
40	#ifdef POSITION
41	,IN
42	,SOUTH,
43	"Generalist interface"
44	#endif
45	);
46
47	in_CLOCK = interface->set_signal_clk ("clock" ,1, behavioural::CLOCK_VHDL_YES);
48	in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, behavioural::RESET_VHDL_YES);
49	}
50
51
52	// ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
53	{
54	ALLOC1_INTERFACE("icache_req",WEST,OUT,_("Request to instruction cache"),_nb_icache_port);
55
56	ALLOC1_VALACK_OUT(out_ICACHE_REQ_VAL ,behavioural::VAL);
57	ALLOC1_VALACK_IN ( in_ICACHE_REQ_ACK ,behavioural::ACK);
58	ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID ,"thread_id",Ticache_context_t ,_size_icache_thread_id);
59	ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID ,"packet_id",Ticache_packet_t ,_size_icache_packet_id);
60	ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_address_t ,_size_icache_address );
61	ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_size_icache_type );
62	}
63
64	// ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
65	{
66	ALLOC1_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port);
67
68	ALLOC1_VALACK_IN ( in_ICACHE_RSP_VAL ,behavioural::VAL);
69	ALLOC1_VALACK_OUT(out_ICACHE_RSP_ACK ,behavioural::ACK);
70	ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Ticache_context_t ,_size_icache_thread_id);
71	ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Ticache_packet_t ,_size_icache_packet_id);
72	ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_size_icache_error);
73	}
74	{
75	ALLOC2_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port,_icache_nb_instruction[it1]);
76
77	_ALLOC2_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION ,"instruction",Ticache_instruction_t,_size_icache_instruction,_nb_icache_port,_icache_nb_instruction[it1]);
78	}
79
80	// ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
81	{
82	ALLOC1_INTERFACE("dcache_req", OUT, NORTH, _("Request to data cache"),_nb_dcache_port);
83
84	ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,behavioural::VAL);
85	ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK ,behavioural::ACK);
86	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_THREAD_ID ,"thread_id",Tdcache_context_t ,_size_dcache_thread_id);
87	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID ,"packet_id",Tdcache_packet_t ,_size_dcache_packet_id);
88	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS ,"address" ,Tdcache_address_t ,_size_dcache_address);
89	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_size_dcache_data);
90	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_size_dcache_type);
91	}
92
93	// ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
94	{
95	ALLOC1_INTERFACE("dcache_rsp", IN , NORTH, _("Respons from data cache"),_nb_dcache_port);
96
97	ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,behavioural::VAL);
98	ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK ,behavioural::ACK);
99	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_THREAD_ID ,"thread_id",Tdcache_context_t ,_size_dcache_thread_id);
100	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID ,"packet_id",Tdcache_packet_t ,_size_dcache_packet_id);
101	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_size_dcache_data);
102	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t ,_size_dcache_error);
103	}
104
105	// ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
106	{
107	ALLOC1_INTERFACE("interrupt", IN , NORTH, _("Interruption line"),_nb_thread);
108
109	ALLOC1_SIGNAL_IN ( in_INTERRUPT_ENABLE ,"enable",Tcontrol_t ,1);
110	}
111
112	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
113
114	std::string name;
115
116	{
117	name = _name+"_core";
118	log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str());
119
120	_component_core = new morpheo::behavioural::core::Core
121	(name.c_str()
122	#ifdef STATISTICS
123	,param_statistics
124	#endif
125	,_param_core
126	,_usage);
127
128	_component->set_component (_component_core->_component
129	#ifdef POSITION
130	, 50, 50, 10, 10
131	#endif
132	);
133	}
134
135	// ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
136	std::string src,dest;
137
138	// ===================================================================
139	// =====[ core ]======================================================
140	// ===================================================================
141	{
142	src = _name+"_core";
143	log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str());
144
145	// ~~~~~[ Interface "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
146	{
147	dest = _name;
148	#ifdef POSITION
149	_component->interface_map (src ,"",
150	dest,"");
151	#endif
152	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
153	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
154	}
155
156	// ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
157	for (uint32_t i=0; i<_nb_icache_port; ++i)
158	{
159	dest = _name;
160	#ifdef POSITION
161	_component->interface_map (src ,"icache_req_"+toString(i),
162	dest,"icache_req_"+toString(i));
163	#endif
164
165	PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_VAL" ,
166	dest,"out_ICACHE_REQ_"+toString(i)+"_VAL" );
167	PORT_MAP(_component,src , "in_ICACHE_REQ_"+toString(i)+"_ACK" ,
168	dest, "in_ICACHE_REQ_"+toString(i)+"_ACK" );
169	if (_have_port_icache_thread_id)
170	PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_THREAD_ID",
171	dest,"out_ICACHE_REQ_"+toString(i)+"_THREAD_ID");
172	if (_have_port_icache_packet_id)
173	PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_PACKET_ID",
174	dest,"out_ICACHE_REQ_"+toString(i)+"_PACKET_ID");
175	PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_ADDRESS" ,
176	dest,"out_ICACHE_REQ_"+toString(i)+"_ADDRESS" );
177	PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_TYPE" ,
178	dest,"out_ICACHE_REQ_"+toString(i)+"_TYPE" );
179	}
180
181	// ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
182	for (uint32_t i=0; i<_nb_icache_port; ++i)
183	{
184	dest = _name;
185	#ifdef POSITION
186	_component->interface_map (src ,"icache_rsp_"+toString(i),
187	dest,"icache_rsp_"+toString(i));
188	#endif
189
190	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_VAL" ,
191	dest, "in_ICACHE_RSP_"+toString(i)+"_VAL" );
192	PORT_MAP(_component,src ,"out_ICACHE_RSP_"+toString(i)+"_ACK" ,
193	dest,"out_ICACHE_RSP_"+toString(i)+"_ACK" );
194	if (_have_port_icache_thread_id)
195	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_THREAD_ID",
196	dest, "in_ICACHE_RSP_"+toString(i)+"_THREAD_ID");
197	if (_have_port_icache_packet_id)
198	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_PACKET_ID",
199	dest, "in_ICACHE_RSP_"+toString(i)+"_PACKET_ID");
200	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_ERROR" ,
201	dest, "in_ICACHE_RSP_"+toString(i)+"_ERROR" );
202
203	for (uint32_t j=0; j<_icache_nb_instruction[i]; ++j)
204	{
205	dest = _name;
206	#ifdef POSITION
207	_component->interface_map (src ,"icache_rsp_"+toString(i)+"_"+toString(j),
208	dest,"icache_rsp_"+toString(i)+"_"+toString(j));
209	#endif
210
211	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_"+toString(j)+"_INSTRUCTION",
212	dest, "in_ICACHE_RSP_"+toString(i)+"_"+toString(j)+"_INSTRUCTION");
213	}
214	}
215
216	// ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
217	for (uint32_t i=0; i<_nb_dcache_port; ++i)
218	{
219	dest = _name;
220	#ifdef POSITION
221	_component->interface_map (src ,"dcache_req_"+toString(i),
222	dest,"dcache_req_"+toString(i));
223	#endif
224
225	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_VAL" ,
226	dest,"out_DCACHE_REQ_"+toString(i)+"_VAL" );
227	PORT_MAP(_component,src , "in_DCACHE_REQ_"+toString(i)+"_ACK" ,
228	dest, "in_DCACHE_REQ_"+toString(i)+"_ACK" );
229	if (_have_port_dcache_thread_id)
230	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_THREAD_ID",
231	dest,"out_DCACHE_REQ_"+toString(i)+"_THREAD_ID");
232	if (_have_port_dcache_packet_id)
233	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_PACKET_ID",
234	dest,"out_DCACHE_REQ_"+toString(i)+"_PACKET_ID");
235	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_ADDRESS" ,
236	dest,"out_DCACHE_REQ_"+toString(i)+"_ADDRESS" );
237	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_WDATA" ,
238	dest,"out_DCACHE_REQ_"+toString(i)+"_WDATA" );
239	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_TYPE" ,
240	dest,"out_DCACHE_REQ_"+toString(i)+"_TYPE" );
241	}
242
243	// ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
244	for (uint32_t i=0; i<_nb_dcache_port; ++i)
245	{
246	dest = _name;
247	#ifdef POSITION
248	_component->interface_map (src ,"dcache_rsp_"+toString(i),
249	dest,"dcache_rsp_"+toString(i));
250	#endif
251
252	PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_VAL" ,
253	dest, "in_DCACHE_RSP_"+toString(i)+"_VAL" );
254	PORT_MAP(_component,src ,"out_DCACHE_RSP_"+toString(i)+"_ACK" ,
255	dest,"out_DCACHE_RSP_"+toString(i)+"_ACK" );
256	if (_have_port_dcache_thread_id)
257	PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_THREAD_ID",
258	dest, "in_DCACHE_RSP_"+toString(i)+"_THREAD_ID");
259	if (_have_port_dcache_packet_id)
260	PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_PACKET_ID",
261	dest, "in_DCACHE_RSP_"+toString(i)+"_PACKET_ID");
262	PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_RDATA" ,
263	dest, "in_DCACHE_RSP_"+toString(i)+"_RDATA" );
264	PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_ERROR" ,
265	dest, "in_DCACHE_RSP_"+toString(i)+"_ERROR" );
266	}
267
268	// ~~~~~[ Interface "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
269	for (uint32_t i=0; i<_nb_thread; ++i)
270	{
271	dest = _name;
272	#ifdef POSITION
273	_component->interface_map (src ,"interrupt_"+toString(i),
274	dest,"interrupt_"+toString(i));
275	#endif
276
277	PORT_MAP(_component,src , "in_INTERRUPT_"+toString(i)+"_ENABLE",
278	dest, "in_INTERRUPT_"+toString(i)+"_ENABLE");
279	}
280	}
281
282
283	// ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
284	if (DEBUG_Morpheo == true)
285	_component->test_map();
286
287	#ifdef POSITION
288	if (usage_is_set(_usage,USE_POSITION))
289	_component->generate_file();
290	#endif
291
292	log_end(Morpheo,FUNCTION);
293	};
294	}; // end namespace morpheo

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